DE2144870C3 - - Google Patents

Description

The invention relates to a monolithic half-memory according to the preamble of claim 1.

In the case of matrix memories with magnetic cores, attempts have been made to replace the defective memory locations by providing a plurality of lines, ie memory cells, than are actually required for the required memory capacity. Now occurs at a memory location in e ^; If a fault occurs in a word line or bit line, then the entire word line or bit line is rendered ineffective and one of the redundant lines is controlled in its place by switches located between the decoders and the memory matrix. This kind of

Compensation for defective memory cells within a matrix memory, however, has the disadvantage that Whole cell groups in the memory are redundant, which significantly increases the price of the memory. Above all it has been shown that such a compensation

of defective storage locations in semiconductor memories cannot be used, since an essential factor in the manufacture of semiconductor memories greater error rate occurs within a memory plate, as is the case with ferrite core memories

The US Pat. No. 32 22 653 a circuit arrangement for compensation is more defective Memory cells become known, which are identified by an additional error marking bit Storage cells within a memory via a

Control network replaced automatically. If the memory call z. B. a defective memory cell controlled, then a comparison circuit causes an alternative address, which is a free one, not Defective memory cell called, is automatically controlled. This circuit arrangement for the automatic However, replacing a defective memory cell has the disadvantage that it is very expensive Switching means and time is required to replace a defective bit position.

Furthermore, from laid-open specification 15 24 788 a circuit arrangement for compensating for defective memory cells within matrix memories has become known in semiconductor technology, which is characterized in that each data block is a Overflow block in the memory is assigned that the control of the memory block and the count known from a block address counter, which contains the respective starting block address, and one Block counter that counts the data blocks transferred, as well as a word address counter that counts the Word cells within a block are determined by an increment of 1 and a word counter that displays the transmitted words counts, takes place, and that a circuit in the presence of a defective word cell A signal is generated within a block that the word counter is switched on at this point in time prevents the word counter from reaching the nominal value after calling all word cells in a block stands and the transfer of the remaining words of one via existing, known addressing circuits Controls data blocks in an assigned overflow block. Apart from the high technical level However, this circuit arrangement is complex

with this solution the serious disadvantage that the presence of these many counters also has one There is a source of error that does not allow proper work to the desired extent

In the laid-open specification 19 01 806 there is another Circuit arrangement for compensating for defective memory cells in monolithic memories has become known, the Tut works in an error correction memory assigned to the main memory and thereby characterized in that the error correction memory in ι ο approximately the same ratio of defective storage locations to non-defective memory locations, such as the main memory and that in the error correction memory both the defective memory location in the main memory and corrected bit information are stored can be and that access circuits are available which access the main memory and the error correction memory act at the same time, so that the information read out from the main memory is transferred to the downstream registers are entered and that the word read out from the error correction memory is given to the input of a downstream associative memory, so that if the match pending information with information stored in the associative memory about downstream Control circuits localized the defective memory location in the main memory and corrected them in the register will.

Although this solution is particularly suitable for monolithic semiconductor memories, it still has the Disadvantage that associative memory must be available and that also an additional error correction memory is required

In addition, the FR-PS 16 01 156 shows a semiconductor memory, in which, for the purpose of eliminating defects, platelets are checked and the Location of the defect on the wafer is determined. However, this memory has the disadvantage that the defective memory locations are addressed despite the error and only then corrected in their effect can be.

The invention is therefore based on the object of a structure of a monolithic semiconductor memory, which consists of several memory plates attached to carrier cards, the defective memory locations have within known sectors to create, in which partially defective memory chips are used and you can still work with related addresses without complicated circuits for address transformation are required.

The solution to the problem according to the invention consists in the characterizing part of claim 1.

The great advantage of the present solution is that the presorting and arrangement of the individual memory platelets within a storage unit, a relatively simple one without additional effort Localization of the faulty bits when addressing is possible so that the cells are in order only by a transformation circuit in logically connected address locations instead of the faulty ones can be called. The erroneous bit positions are only in higher address locations translated that are normally not addressed.

This provides a solution that works both very quickly and with extremely little circuit complexity required to compensate for the erroneous bit positions. It should also be noted that there is a very large storage space utilization or memory yield is achieved.

An embodiment of the invention is shown in the drawings and will be described in more detail below described. It shows

F i g. 1 is a schematic block diagram of a monolithic memory;

FIG. 2 is a more detailed block diagram of a wafer of the type shown in FIG. 1 shown memory,

F i g. 3a and 3b show a block diagram and a table of an address buffer for a memory which only consists of flawless platelets are built up (full memory),

F i g. 4a and 4b show a schematic block diagram and a table of a "half-memory";

F i g. 5a and 5b show a block diagram and table of an address buffer for use in a half or Full memory,

F i g. 6a and 6b are a schematic block diagram and table of a memory address buffer for use as quarter, half, three-quarter or full memory and

7 shows a schematic block diagram of a system which combines a plurality of partial memories.

The memory according to FIG. 1 consists of several cards 10, each having a bit position of a word in a three-dimensional memory included. The memory is stored in an address register 12 by a memory Address addressed, which runs via the address buffer 14.

Each card 10 consists of several modules 16 and each module of four plates 18. A single one The chip is shown in more detail in Fig. 2, the bit addresses on a chip are arbitrary in logical quadrants, and the two binary address buses that address these quadrants are Called quadrant address.

The output 20 from the address buffer 14 is connected to all the chips in the memory and is decoded, to select a single bit cell on the wafer, which is more detailed in connection with FIG. 2 described will

The output 22 of the address buffer 14 drives a V decoder 24 and the output 26 drives an X decoder 28 on the card. The decoded outputs from the Y and Λ decoders excite a single platelet at the intersection.

In Figure 2, a single plate 18 is more precise Word decoder 30 and bit decoder 32 decode output 20 from address buffer, what to select a single bit on the wafer at the intersection of the energized decoder output lines leads

Each plate is also equipped with a plate selector circuit 34 which is responsive to the X and Y lines. When the appropriate X and I 'lines are energized, the die select circuit 34 actuates the read-write control circuit 36. When the read-write input of the circuit is energized, the data on the data input line is in the Selected memory cell stored in the chip. Only the memory cell selected by the word decoder and the bit decoder is used for storage.

Similarly, data is sensed by the sense amplifier 38 associated with the card is connected that it responds to data read from the memory cell that is decoded by the word and the bit decoder is energized.

In Fig. 3a is the organization of an address buffer ft

the use in a memory with defect-free platelets and full capacity is shown. The outputs 0 to 14 from the address register are not changed by the address buffer and as shown in Fig.3a driven on module, plate, quadrant and low-order address positions.

F i g. 3b shows a diagram of the selectable quadrant and plate addresses for a memory with full capacity. The memory has no defective chips and therefore all addresses A 0, A 1 ... A 15 can be used in the module.

The only address bit positions of interest for explaining the invention are positions 4 and 5, which represent the die address, and positions 6 and 7, which represent an arbitrary quadrant address. Since a plate in FIG. 2 has a total of 256 memory cells, each quadrant contains a total of 64 different bit addresses; the quadrant addresses are in FIG. 3b shown as Λ 0, Λ 1, Λ 2 and A 3 for plate 0. The address positions of FIG. 3b are contiguous as selected by the address buffer 14 of FIG. 3a, that is, when a binary sequence is given to the input of the address buffer 14, the addresses generated at the output are sequential. The addresses naturally run from one module to the other.

F i g. 4 is a circuit diagram for the address buffer 14 which provides a half memory, i.e. h, a memory in which half of the quadrant addresses are not selected. However, the selected quadrant addresses are contiguous.

A half size memory is constructed as follows. First, the tiles are sorted according to the Sorted tiles that have incorrect addresses only in the second and / or third quadrant 1 or 2 and platelets that have defects only in the first and / or second quadrant 0 and 1. Plate with Errors in the second and / or third quadrant 1 and 2, respectively, are placed in the platelet position 0 and 1 of each Module set. Tiles with defects in the first and / or second quadrant 0 or 1 are placed in the second and third platelet position of the module set Since the memory is only half the size, the Position 0 of the address register is not used and all address lines are in the next bit position shifted, as shown in Fig.4a. The address register bit positions 5, 6 and 7 are cross-wired as shown for the four module inputs, the die address and the Correspond to quadrant address. This creates contiguous addresses for the eight good quadrants within a module according to the in F i g. 4b is generated

F i g. Figure 5a shows the internal circuitry required in address buffer 14 to create full and half size memory, respectively. The circuit can be used in a memory that is equipped with nothing but good circuit cards or with circuit cards that contain errors in connection with FIGS. 4a and 4b have the type described. This use takes place with the aid of the circuit shown in FIG. If half size memory is desired, the 0 input will not be energized and the circuit will behave exactly like that shown in Figure 4a. However, when addressing a full size memory, the 0 position is used and the exclusive OR element 50 generates a pattern as shown in Figure 5b. Thus, the addresses are contiguous, starting with AO to An and continue with the next address BO to Bn , thus providing a full-size memory.

FIG. 6a shows a circuit which can be used in the address buffer and which supplies a memory with a size of ¹ A, '/ 2, ³ A or. If a Ά memory is desired, the modules are sorted out according to four different classes. The modules with defects in platelet quadrants 1, 2 and 3 are placed in the O-platelet position, those with defects in quadrants 0.2 and 3 in platelet position 1 on the module, those with defects in quadrants 0.1 and 3 in die position 2 on the module and finally those with errors in quadrants 0, 1 and 2 in die position 3 on the module. Since this is a quarter of the memory, the more significant bit positions 0 and 1 of the address register are not required and are therefore not energized. In this case, the exclusive OR elements 52 and 54 have no influence on the circuit, and the address sequence is A 0, A 1, A2 ... Aη (see FIG. 6b). If half memory is desired, the 1-bit position input to buffer register 14 is energized, whereby exclusive OR gate 54 provides the sequential addresses above An , ie BO, Bi, B2 ... Bn.

Similarly, for a ³ A memory, the non-equivalence elements 52 and 54 generate the next higher address positions CO to Cn in the order. Finally, for a ⁴ A memory, the next address positions in the series, namely DO to Dn, are generated using the last positions of the chip.

In Fig. 7 the memories A, B, C, D, E and F are combined in such a way that only a fraction of each memory is used in such a way that the entire combination is addressed by contiguous memory addresses. The result is a combination of memories that appears to the user as a logical memory.

Each memory 15 contains 32 K addressable locations. The memories C, D, E and F are used up to 75%. The memories A and B are used up to 50%. Each memory is equipped with a decoder 14 which can decode up to 15 binary inputs which provide output signals for selecting the memory locations. Addresses are supplied to the memory system via an address register 12 which stores a 15 bit binary address. The high-value address positions are supplied by the block address register 13.

For addresses with lower numbers, however, the high-value bit positions 0 and 1 of the address register 12 do not excite the AND gate 17. The output signal of the AND element 17 is negative, is inverted and thereby excites an input of the AND element 19. The block address register contains 13 zeros for the low addresses. The output 1, which is negative, is reversed and excites the other input de; AND gate 19, as a result of which the output signal »selects memory Qi is generated and memory C is selected. The memory C remains selected for approximately 24 K contiguous addresses until the address f is reached at which the high-order bit positions 0 and 1 of the address register 12 are excited. Characterized eil output signal is supplied from the AND gate 17 and because: energized AND gate 21, whose output signal wiederun to a signal "Select memory Λ" leads and dei half latch A chooses The entrance to the address buffer 1 of the memory A is connected to the werthcV s Position 1 at there

Block address register 13 connected. This ensures the excitation of the address buffer, namely only the lower value bit positions 2 to 14. Memory A is only used for ¹ A during the first selection

Addressed memory addresses. The second choice of memory A selects the remaining quarter of the usable positions. This is shown by the following table, which shows the election sequence.

block Address Choose Storage C. address register Choose Storage A (first '/ 4) 00 00 AX- X Choose Storage D. 00 HXX-X Choose Storage A (second ¹ A) 01 00XX— X Choose Storage E. 01 11XX-X Choose Storage B (first 1/4) 10 00XX-X Choose Storage F. 10 11XX-X Choose Storage B (second ¹ A) 11th ooxx-x 11th HXX-X

Thus, contiguous binary addresses given to address register 12 and block address register 13 select non-contiguous memory addresses in memories A to F.

For this purpose 4 sheets of drawings

Claims (6)

Patent claims: 1. Monolithic semiconductor memory, made up of several on carrier cards There is memory platelets that have defective memory cells within known sectors by during the manufacturing and testing process, the die in sectors or quadrants divided and then sorted according to the location of the error in dsn sectors, thereby characterized in that the memory platelets (18) in relation to one another on a carrier card (bit card) are arranged that all bit maps (to) with respect to the platelet sectors, the defective memory cells contained, are identical, and that by a transformation circuit (14, 50) the addresses so be transformed so that the non-defective memory cells are logically connected Address locations are arranged. 2. Monolithic semiconductor memory according to claim 1, characterized in that from the partially defective memory ^{plate (18) 3} At-, '/ 2-, ¹ At-, · / "- partially used memory (15) with associated address buffer memory (14) is formed are. 3. Monolithic semiconductor memory according to Claims 1 and 2, characterized in that partially used memory (15) with their address buffer memory (14) to a common memory are interconnected by the address buffer memory (14) via a common address register (12) can be controlled and by a block address register (13) and the conjunctively linked The highest digits (0 and 1) of the address register (12) can be selected so that the faulty ones are not Memory cells of all memories (15) are logically arranged in contiguous address locations (Fig. 7). 4. Monolithic semiconductor memory according to claim 1, characterized in that each memory plate (18) is assigned a word decoder (30) and a bit decoder (32) and a plate selection switch (34) and that the address buffer (14) with the two decoders mentioned (30 and 32) are connected via the X and y decoders (28 and 24) of a memory card, memory chips (18) with errors in the second and / or third quadrant being arranged in positions 0 and 1 of each memory card and memory chips (18) with errors in the first and / or second quadrant are arranged in the second and third positions of the memory card. 5. Monolithic semiconductor memory according to claim 4, characterized in that at one Half memory position 0 of the address register (12) is not used and all address lines are in the next lower bit position are shifted, while bit positions (e.g. 5, 6 and 7) in the Address register (12) or address buffer (14) are wired crosswise. 6. Monolithic semiconductor memory according to claim 4, characterized in that a full-size or half-size memory at the 0 input of the address buffer (14) has an exclusive OR circuit (50) that the 0 input is not energized for the desired half memory and the desired full memory is excited, as a result of which the addresses are formed consecutively, starting with AO to An, continuing with the next address BO to ßnusw.