JPH0536293A - Digital signal delivering system, digital audio signal processing circuit and signal converting circuit - Google Patents

Abstract

PURPOSE:To provide a digital signal delivering system to realize the selling of information, etc., having the commercial value in the condition of the mode of a digital signal, an audio processing circuit suitable for it, a signal processing circuit, etc. CONSTITUTION:In the delivery of a digital signal, a digital signal supply source and a player are directly connected, the specified information is received and stored, and the information stored by the player itself is reproduced. A terminal device 100 plays the role of an information server and is arranged at the station store, etc. The terminal device 100 is constituted of an input part 102, a storage part 103 and an output part 104, each circuit block is connected by a VME bus 105, and a digital signal and respective types of control signals are given and received. A memory card 101 (a player) with a reproduction function illustrated by dotted lines is connected and a special digital signal as merchandise is delivered as it is.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal delivery system, a digital voice signal processing circuit and a signal conversion circuit, for example, delivering specified voice information in the form of an electric signal to a specified person for sale. The present invention relates to a digital signal delivery system that has been realized or provided, and a technology effectively used for a digital audio signal processing circuit and a signal conversion circuit, and a data compression and expansion circuit suitable for the system.

[0002]

2. Description of the Related Art As an example of commercialization of information and the like, there have been newspapers and magazines for printing characters and the like on paper for sale for a long time. In some cases, instead of the above paper, various software and the like are sold through a storage medium such as a floppy disk memory or an IC card. In addition, news and broadcast programs are also provided to specific persons who have contracted through communication means such as cable television and satellite broadcasting.

Further, unlike conventional notebook personal computers and electronic notebooks, messages can be sent to other people, databases can be accessed, and information can be easily processed without being restricted by time and place. A portable computer adapted for operation is proposed in "Nikkei Electronic", pages 116 to 124, dated November 26, 1990. In this system, it has been proposed that data is transmitted to a portable terminal through a public telephone or FM broadcasting, and an IC card is provided by a bookstore or a station shop.

Further, Japanese Patent Application Laid-Open No. 63-61391 also discloses a system for providing and receiving information.

A digital-to-analog converter that can be realized by a digital circuit has been proposed in Japanese Patent Laid-Open No. 61-236222.

[0006]

[Problems to be Solved by the Invention] When commercializing and selling information and the like using paper such as newspapers and magazines as a medium, it takes time to print and transport and is not suitable for timely sales of information. Instead, it will lead to a deterioration of the global environment, such as deforestation to make paper and discharging garbage when it is no longer needed. In addition, when an IC card or a floppy disk is used as a medium such as an electronic notebook, not only a terminal device such as an electronic notebook or a personal computer is required, but also these terminal devices have information like an electronic notebook. Since it is premised on processing, its operation is relatively complicated and inconvenient to use, which hinders its general spread. In addition, when a large amount of data is sent using FM broadcasting, not only is it troublesome to select the necessary information, but also other necessary information as in the satellite broadcasting and cable television broadcasting. Even unnecessary information is received as a single contract, which is inefficient.

Therefore, the inventors of the present invention have made it possible to transfer information in the form of electric signals in the same form as general products, and to carry the received information in an ultra-thin reproducing function. We have developed a digital signal transfer system for reproducing with a built-in memory card, and a digital audio signal processing circuit and signal conversion circuit suitable for it.

An object of the present invention is to provide a digital signal delivery system which realizes sale of information and the like which has a commercial value in the form of an electric digital signal.

Another object of the present invention is to transfer digital signals between the digital signal supply source and the memory card with a reproducing function at a speed higher than at least a signal to be processed in the digital signal transfer system. To realize that.

Still another object of the present invention is to provide a terminal device suitable for the above digital signal delivery system.

Still another object of the present invention is to provide a reproducing method and an apparatus which are suitable for the digital signal passing system and have high quality of the memory card with the reproducing function.

Still another object of the present invention is to provide a method and apparatus for efficient transfer of information and security of information in the above digital signal passing system.

[0013]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, in the delivery of digital signals, an ultra-compact ultra-thin card-shaped player having earphones as a memory card with a playback function is connected in one-to-one correspondence with a terminal device as a digital signal supply source,
That is, the specified digital signal is received as it is, stored in the storage circuit, and reproduced by the player alone.

For example, in the digital signal transfer system, the digital signal is transferred between the digital signal supply source and the memory card with the reproducing function at a speed higher than at least the signal to be processed. Further, between the digital signal supply source and the digital signal supply source, the digital signal is received from the supply source via a communication line or an appropriate storage medium as necessary, and stored, and the memory card with the reproducing function ( Player)
Is connected via a connector to exchange the specified digital signal. Further, the storage capacity of the terminal device is the same as or larger than the storage capacity of the storage circuit on the memory card (player) with a reproducing function, and the terminal device has a relatively large storage capacity. Using a magnetic disk memory device as a backup memory, a buffer memory composed of a semiconductor memory capable of high-speed access to a digital signal that has a large transfer amount with a memory card with a playback function or a digital signal that is updated over time By storing it, information is efficiently delivered. Further, it manages a storage area for a storage circuit in the memory card with a reproducing function. In addition, the terminal device has a function of reproducing a part of a designated digital signal for a fixed time and outputting the same, and further, delaying the listening by the silent period control, fast listening, and removing the quantization noise. It is intended to realize a digital signal transfer system that has a small, ultra-thin memory card with playback function.

[0015]

Since the player receives the digital signal in the form of an electric signal and reproduces it independently, the value of the delivered digital signal can be exerted as it is. This makes it possible to easily process, manufacture, and construct a sales system because the digital signal form can be maintained, and the player configuration is simple and the operation is easy because it is an ultra-small and ultra-thin card. But I can handle it. Deteriorate voice quality by substantially extending or extending the silence period of a digital voice signal.

Without this, fast listening and slow listening are possible.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of essential parts of an embodiment of a digital signal delivery system according to the present invention. This embodiment is directed to a system aimed at commercializing and selling digital signals. That is, one form of delivery of digital signals is sales of digital signals.

FIG. 1 shows a block diagram of a terminal device in the digital signal selling system. The terminal device 100 corresponds to a vending machine for soft drinks such as cigarettes and juice. The terminal device 100 plays a role as an information server, and is not particularly limited, but is connected to a digital signal distributor through a wide band digital communication line B-ISDN to receive a digital signal as a product. By adopting such a system, the digital signal is transferred only to the terminal device 100 specified by passing through the communication line like the commodity such as the above-mentioned cigarette and juice. In the case of digital signals as products in this case, data as a large amount of products can be produced at high speed without causing traffic congestion and air pollution unlike the transportation of general products such as cigarettes and juice. Transfers can be made. The terminal device 100 is installed at a storefront of a store such as a station shop, a cigarette shop, or a bookstore.

The terminal device 100 is roughly composed of an input unit 102, a storage unit 103, and an output unit 104,
The respective circuit blocks are connected by the VME bus 105 to exchange digital signals and various control signals. The terminal device 100 is connected to a memory card 101 (hereinafter referred to as a player) having a reproducing function, which is shown by a dotted line in FIG.

FIG. 2 shows the input section 1 of the terminal device 100.
A block diagram of 02 is shown. The terminal device 100
The input section 102 of the B-IS is a wideband digital communication line.
A digital input interface compatible with DN and an analog input interface that receives an input signal in the form of an analog signal (right analog input, left analog input)
have. Analog input interface is right input Ri
The low-pass filter 202 corresponding to n and the left input Lin
a and 202b are provided respectively, and the analog input signal R
Extra frequency band components contained in in and Lin are removed in advance. Then, these input signals Rin and Lin
Are alternately selected in time through the multiplexer 203, taken into the sample and hold circuit 204, and converted into a digital signal by the analog / digital conversion circuit 205. At this time, the 2-channel (stereo) digital signals of the right channel signal and the left channel signal are time-divisionally output from the analog / digital conversion circuit 205 in a time-sequential manner and taken into the digital input interface 207. Such an analog input interface is used, for example, to convert a music program sent by broadcasting or the like, a regular news program, stock information, or various commodity market conditions into a digital signal and store it in a storage circuit.

The monaural signal is input using the right or left input signal. For an input signal with a wide band such as a music program, the low-pass filters 202a, 20a
The band of 2b may be widened, and a function of switching the band of the low-pass filters 202a and 202b to a narrow band for an input having a narrow band such as a news program may be added. 20
6 is an input control circuit, and 201 is the B-IS.
This is a network interface compatible with DN.

The analog input interface may be connected to a telephone line to receive a message from an answering machine. In this case, a telephone function may be added to the terminal device 100, and the terminal device 100 may be connected to the above answering machine to receive the recorded message. When the analog input interface is used as described above, the message transfer time becomes long. Therefore, a subscriber having a digital line can receive a plurality of recorded messages in a very short time by converting the messages into digital signals and storing them by a digital answering machine. By doing so, it is possible to listen to the message at any time, such as while traveling by means of transportation etc. at the destination.

FIG. 3 shows a block diagram of an embodiment of the storage unit in the terminal device 100. The storage unit includes an external storage device such as a hard disk memory 301, a RAM (random access memory) 308 as a buffer memory, an information processing program for digital input or analog input as described above,
A ROM (Read Only Memory) 307 storing various programs such as data exchange with the hard disk memory 301, a display operation of the liquid crystal display device 303, and a data transfer operation with the player 101 connected to the output unit, and the above program. It includes a microprocessor 306 for performing the following information processing and control operation. Although not particularly limited, the RAM 308 has a storage capacity of about 1 MB, and the ROM 307
Has a storage capacity of about 512 KB (kilobytes, the same applies hereinafter). The hard disk memory 301 has a storage capacity of about 250 MB (megabytes, the same applies hereinafter), although it is not particularly limited, and has a function as a backup memory at the time of power shutoff, as well as a warehouse for storing various kinds of digital signals. Play a role. The hard disk memory 301 is connected to the internal bus 309 via the hard disk control circuit 302, and
According to the instruction of 6, data writing and reading are performed.

A liquid crystal display device 303 is used for displaying information menus, operating instructions, and the like.
A touch key function is added to the surface to select a display menu and switch the display. For example, player 1
When 01 is inserted, the information menu that is first displayed on the display screen is 1. Music, 2. News, 3. Weather forecast, 4. Stock market conditions, 5. Readings etc. are displayed. And
One of them, eg 2. The screen changes when news is specified. NHK, 2. FEN, 3. Transportation information,
4. Sports news etc. are displayed. Then, by designating a desired news program, the player 101 receives a digital signal corresponding thereto.

For example, 1. In the case of music, music genres such as classical music, popular music, popular songs, and jazz are displayed, and when a specific music genre is selected, the music titles available for sale are displayed. This music information is not particularly limited, but it is assumed to be stored in a specific area of the ROM 307 or the hard disk memory 301. When there is no corresponding song in the hard disk memory 301, it is connected to the digital signal sales source through the communication line B-ISDN, receives the desired music program, and is delivered to the player 101. The liquid crystal display device 303 is connected to the internal bus 309 via the LCD control circuit 304, and the above-described display and touch key input corresponding thereto are performed.

The bus interface 305 is a VME bus interface for connecting the internal bus 309 and the VME bus 105.

A buffer memory 403 provided in an output unit to be described later is used for information that needs to be replaced with the latest information over time, such as the news and stock market conditions.
To be stored in. As a result, the hard disk memory 301 can be immediately transferred to the player 101 without accessing it. In addition, even in the case of a music program with a large sales volume, the buffer memory 40
3 may be stored. In this case, the top ten of the sales volume corresponding to each music genre may be displayed as a display menu to facilitate the user's selection.

The output unit of the terminal device 100 is composed of an output interface 401 connected to the VME bus 105, a player control circuit 402, a buffer memory 403, a monitor control circuit 404, a monitor circuit 405, etc., as shown in FIG. To be done. The output unit has a connector for connecting to the player 101, is connected to the player 101 via a connector, and transfers a digital signal as a product. Buffer memory 403 is about 96MB
Has a relatively large storage capacity, which corresponds to about 10 times the maximum storage capacity of 8 MB of the player 101 as described later.

The monitor circuit 405, which is not particularly limited, is provided with a speaker 406 and a headphone output, and is used for listening to a portion of the music when a music program is selected. This function is, so to speak, a browsing function of a bookstore, and is effective in promoting sales of intangible digital signals and preventing mistakes in selecting digital signals.
The monitor output function described above is not particularly limited, but is about 1
About 0 seconds is set as the maximum time, and the touch key or the like is output only during the ON state. As a result, the monitor output is stopped as soon as the purpose is achieved, so that the dead time of the monitor reproduction can be eliminated. As the monitor circuit 405 and its monitor control circuit 404, the same circuit as the reproducing circuit of the player 101 described later is used.

As described above, commodities such as tobacco and juice sold by the vending machine are put in a package or a container and sold integrally with the package or the container. Further, conventional commercialized information and the like are sold by using printed matter using paper as a medium, floppy and IC memory as a medium, and playing a role as a package or a container. And the music program is also sold together with a storage medium such as a magnetic tape or a compact disc. These media have no commercial value of their own. When combined with terminal devices such as electronic notebooks and personal computers,
Information as a product is taken out and processed. Also,
The value of the product will not be exhibited until the music program is also combined with a cassette tape recorder and a playback device.

On the other hand, in the present application, a digital signal as a product is delivered as it is without interposing a storage medium serving as a container as described above. A memory circuit 701, which will be described later, is mounted on the player 101 for transferring such digital signals. The digital signal taken into the storage circuit 701 can be reproduced by the player 101 alone by the reproduction circuit of the player 101. That is, the delivered product immediately exhibits its value as a product. These two characteristics are very different from the conventional product transactions. Further, as described above, in the system in which the player 101 is connected to the terminal device 100 and the digital signal as a product is transferred, only necessary information can be specified and sold when necessary.

In FIG. 4, 407 is a power supply circuit,
Although not particularly limited, operating power is supplied from the terminal device 100 for high-speed transmission of a digital signal to the player 101, in other words, for writing operation.
In addition, as a power source of the player 101, a rechargeable secondary battery is used instead of a primary battery as described below,
In the case where the primary battery and the secondary battery are built in, when the player 101 is connected to the terminal device 100, the above digital signal is passed and the secondary battery is supplied by the power supply circuit 407. A quick charge to is also performed. Examples of signals exchanged between the output section and the player 101 include the operating voltage V, the digital signal D, the address signal A, the control signal C, and the status signal S.

In the current cassette tape recorder, etc., information storage time and reproduction time are basically the same. this is,
In the system for automatically selling information as proposed in this application, it becomes a big problem for users. Therefore, in the above digital signal transfer system, it is desirable to speed up the transfer of the digital signal between the terminal device 100 and the player 101 in consideration of the user's convenience. This function is performed by the buffer memory 403 of the terminal device output unit 104 and the player 101 in FIG.
This can be realized by providing the memory circuit 701 of at least with a memory circuit that operates faster than a signal to be reproduced, a control circuit of the memory circuit, and data transfer means.

This embodiment will be described with reference to FIGS. 5 and 6. First, FIG. 5 shows a block configuration relating to high-speed transfer on the player 101 side. Photosensor 502, IV amplifier 503, serial / parallel conversion circuit 504, PL
L oscillator circuit 505, frequency divider circuit 506, multiplexer 5
07 and a mode switch 508 are added in the player. In the optical mode (the mode switch 508 is set to the light side), the B input side of the multiplexer 507 is selected and becomes the Y output, so external data supplied as a light pulse train (at the head of the unit write data train is “
The start bit indicating the state of "1" and the start bit indicating the state of "0" are added by 2 bits) to the memory circuit 701. That is, the light modulation pulse train is the photosensor 502.
Is converted into a current signal by the I-V amplifier 503, waveform-shaped as a voltage signal by the I-V amplifier 503, and input to a PLL oscillation circuit 505 for extracting a clock component from the pulse train after the shaping. Also input to the signal input terminal D. The PLL oscillation circuit 505
Clock signal extracted in (in this application, a frequency of 8 MHz)
Becomes the shift clock of the serial / parallel conversion circuit 504 and at the same time 1 / n (n is the number of quantization bits +
It becomes a count clock of the frequency dividing circuit 506, which is 2 bits and is 10 in the present application, and the output signal (800 kHz in the embodiment) of the frequency dividing circuit 506 becomes a write strobe signal to the memory circuit 701.

In addition, the electric mode (mode switch 508
Is set to the electrical side), A of the multiplexer 507
Since the input side is selected to be the Y output, the 16-bit parallel data is written from the input buffer 501 through the multiplexer 507 to the storage circuit 701.

FIG. 6 shows a block configuration showing a data transmission unit on the terminal device 100 side. For the 8-bit parallel data, the data output of the buffer memory 403 is output by the output buffer 601, and for the light modulation pulse, the data of the buffer memory 403 is parallel / serial converted.
02 as a serial signal, and a start bit adding circuit 603 adds 2 bits of a start bit indicating the state of “1” and the state of “0” to the head of the data string, and the VI amplifier 604.
The laser diode 605 is driven by and is output as a pulse train of light.

According to this embodiment, information such as a voice signal can be transferred at high speed wirelessly by optical coupling. For example,
In this embodiment, about 6 minutes of voice information (resolution 8 bits, sampling frequency 22.05 kHz, monaural) could be transferred in only 10 seconds. Also, in the example in which the frequency of the clock signal is set to 800 kHz for the purpose of reducing the power consumption during high-speed transfer, good results can be obtained although it takes some time.

The basic idea of this embodiment is that the operation speed of a digital memory such as a semiconductor memory is faster than that of an analog signal to be processed, and the content of the digital memory is directly transferred at a high speed by a digital signal. Needless to say, many applied operations are possible within the scope of this idea. For example, instead of the optical coupling method, the same result can be obtained by directly connecting the data transfer source with a connector or cable, and the action of application of radio waves or magnetism may be used. Further, in the method of transferring 8-bit parallel data, although the number of pins of the connecting connector is large, the circuit on the transmitting side or the receiving side is simplified, but the transfer speed is further shortened by about an order of magnitude. Only 1 minute for 6 minutes
Could be transferred in seconds.

In this embodiment, the terminal device 100 directly manages the memory circuit 701 of the player 101, but the transfer is started from the first address (zero address) of the memory circuit 701 and the address counter ( For example, FIG.
No. 703) of the storage circuit 703 overflows, or a method of high-speed transfer of data from any address to any address of the storage circuit 701 by adding ID information to the beginning part of the transfer data string. Also check,
Good results have been obtained.

Usually, considering the usability of the user, the necessary information can be selected from the abundant information accumulated in the terminal device 100, and the necessary information can be transferred to the player 101 at any place at any time. , Is required to be able to be repeatedly reproduced. Therefore, the storage capacity of the terminal device 100 is at least the same as or larger than the storage capacity of the player 101. That is, the storage capacity of the player 101 is M
p, where Ms is the storage capacity of the terminal device 100, Mp
≦ Ms. Note that this condition is not particularly limited depending on the application form. In FIG. 7, the player 1
A block diagram of one embodiment of 01 is shown.

The player 101 is roughly divided into a memory circuit 701 for storing digital signals, a large-scale integrated circuit 709 including a gate array, and a reproducing circuit. The storage circuit 701 is not particularly limited, but is about 8
It is composed of a pseudo static RAM having a storage capacity of MB. For example, as will be described later, 16 pseudo static RAMs (PSRAMs) each having about 4M bits are mounted,
The storage capacity of about 8 MB is realized. Large scale integrated circuit 7
Reference numeral 09 denotes a control circuit 704, an address counter 703, a multiplexer 702, and a parallel / serial conversion circuit 7.
05 is installed. The control circuit 704 has a storage circuit 701.
In addition to various control signals at the time of reading and reproducing the digital signal stored in, the control signal at the time of data input to the memory circuit 701 is also formed.

The address counter 703 is a memory circuit 70.
An address signal for reading the digital signal stored in 1 is generated. The multiplexer 702 performs address switching when the storage circuit 701 is accessed from the terminal device 100 and when the storage circuit 701 is internally accessed. That is, the writing of the digital signal to the memory circuit 701 is performed by the address from the terminal device 100 side, and the reading in the reproducing operation of the digital signal is performed by the address generated by the address counter 703.

A low-pass filter 706 is composed of a digital filter circuit and inputs only the band component necessary for reproduction to the digital / analog conversion circuit 707. In this embodiment, as will be described later, digital signals of a plurality of sampling rates are handled according to information and programs. The pass band of the digital filter is also switched according to these sampling rates. The digital / analog conversion circuit has a function of outputting left and right channel analog signals separated into left and right corresponding to a stereo signal input in a time division manner.
If the digital signal is a monaural signal,
The same analog signal is output from both channels. The player 101 uses headphones to output audio in order to reduce the size and weight. Reference numeral 711 is a headphone terminal therefor.

FIG. 8 shows a plan view of an embodiment of the mounting board which constitutes the player 101. Player 10
1 includes a control board 807 and a memory board 802. The control board 807 is provided with a power source section for inserting the button batteries 808a to 808d and a connector section separately at both ends in the longitudinal direction, and the large scale integrated circuit 709 and the amplifier circuit elements 805, 8 are provided on the board surface between them.
06, low-pass filter 706, and digital / analog conversion circuit 707. Electronic components such as semiconductor integrated circuit devices are mounted. Connector 804 is JEIDA
( J apan E lectronic I ndustry D evelopment A ssosiatio
n: Japan Electronic Industry Development Association) Standards (standards for memory cards, etc.) are used. The power supply unit consists of a button battery holder, such as an alkaline button battery (LR4
4) can be mounted four times. This control board 8
The size of 07 is not particularly limited, but the vertical length is 52 mm,
The width is 82 mm and it can be stored in the existing IC card case.

The memory board 802 corresponds to the size of the control board 807 excluding the relatively thick connector section and the section corresponding to the power supply section, and eight PSRAMs are mounted on each side. The memory board 802 and the control board 807 are flexible wiring boards 803.
Connected by. That is, the two substrates can be opened to facilitate inspection and repair.

FIG. 9 shows a side view of the mounting board housed in the case. The control board 8
Memory board 80 on the surface except the power supply part and connector part of 07
2 are folded back by the flexible wiring board 803 and are overlapped. As a result, it can be stored in the same case as an existing IC card (RAM card),
A small and thin player 101 can be realized. Also,
As described above, since the memory substrate 802 and the control substrate 807 can be kept open during repair, the IC or LS
It is easy to replace electronic components such as I.

FIG. 10 shows a plan view of another embodiment of the player 101.

In this embodiment, the main body of the player 101 and the storage circuit section 1001 can be attached and detached. That is, the main body of the player 101 is the same as the control board 80.
7, the large-scale integrated circuit 709 for control, the digital / analog converter circuit 707, the amplifier circuit 708, etc.
It is composed of C, a battery case, a JEIDA standard-compliant memory card connector 804, and the like. Then, as indicated by a dotted line in the figure, the memory circuit unit 100 in a thin card state is internally provided.
A space into which 1 (memory card) can be inserted and a storage circuit connector 1103 shown in FIG. 11 are provided. The memory circuit unit 1001 is configured, for example, in a thin card-shaped plastic case, in which the above-mentioned pseudo-static RAM and its backup battery are housed. By making the storage circuit unit 1001 detachable in this manner, a plurality of types of memory cards can be prepared. For example, as the RAM, static RAM or dynamic RAM
Alternatively, it is possible to prepare a memory having a plurality of storage capacities. In addition to the RAM as described above, a ROM card can also be used. As the ROM card, a mask type ROM may be used, or an EEPROM may be used to transfer digital signals. When such an EEPROM is used, a digital signal is transferred, in other words, the writing operation of the digital signal takes a little longer than when a RAM is used, but a backup battery becomes unnecessary, so that a memory card is used. Simplifies the manufacturing and handling of.

Further, the JEIDA standard (currently the guideline Ver.) Adopted in a general-purpose IC memory card such as the outer shape of the player 101, physical specifications such as connectors, electrical specifications such as signal characteristics and timing, and card attribute information.
Compatibility with existing IC memory cards can be ensured by adapting 4.0) as standard).
In the JEIDA standard, the external dimensions, connectors, pin arrangements, battery voltages, etc. are standardized, but in the present application, the external dimensions, signal pin arrangements, and signal characteristics are particularly extracted. FIG. 63 shows the outline of a type I card according to the JEIDA standard. External dimensions are 85.6 mm x 54.0 mm x
It is 3.3 mm. FIG. 64 shows the outline of a type II card according to the JEIDA standard. The external dimensions are 85.6 mm x 54.0 mm x 5.5 mm (however, the connector section is 3.3 mm). FIG. 65 shows the pin arrangement of signals, and the guideline is Ver4.0.
So, the number of pins is 68. FIG. 66 shows the signal characteristics.

FIG. 11 is a block diagram showing one embodiment of the main body of the player 101 and the storage circuit section 1001.

A memory card connector 804 conforming to the JEIDA standard, which is connected to the terminal device 100 as described above, is provided outside the main body of the player 101. And
A storage circuit connector 1103 is provided inside.
The card-shaped storage circuit unit 1001 as described above can be attached and detached via the storage circuit unit connectors 1002 and 1103.

The data input from the memory card connector 804 corresponding to the terminal device 100 is supplied to the data input terminal Di of the storage circuit section 1001 via the storage circuit section connectors 1002 and 1103. The address input from the memory card connector 804 corresponding to the terminal device 100 is supplied to one input A of the multiplexer 1105. The other input B of the multiplexer 1105 is supplied with the reproduction address generated by the address counter 1106 of the player 101 main body. Through this multiplexer 1105, a digital signal transfer address and a reproduction address are selectively supplied to the address terminal A of the memory circuit section 1001. And
Memory card connector 804 corresponding to the terminal device 100
The control signal input from A is supplied to one input A of the multiplexer 1104. This multiplexer 110
The other input B of 4 is supplied with a control signal for reproduction formed by the control circuit 1101 of the main body of the player 101. Through the multiplexer 1104, the control signal for passing the digital signal and the control signal for reproduction are selectively supplied to the control terminal C of the memory circuit unit 1001.

Multiplexers 1105, 1 as described above
104 is provided to perform switching of addresses and control signals, and the storage circuit unit 1001 is accessed from the terminal device 100 side to transfer digital signals and the player 101.
Reproduction of a digital signal that is accessed by the address counter 1106 of the main body or the control circuit 1101 is selectively executed. In the reproducing operation, the memory circuit unit 1
The digital signal output from the output terminal Do by the read operation of 001 is stored in the storage circuit connector 1002, 1
An audio signal is output via 103 through a reproduction circuit including a low-pass filter 706, a digital / analog conversion circuit 707, an amplification circuit 708, etc. of the main body of the player 101.

Control circuit 1101 of the player 101 main body
Controls the low-pass filter 706 and controls the digital / analog conversion circuit 707 according to the ID code of the reproduced digital signal.

The power supplied from the terminal device 100 is an operating voltage for high-speed writing of digital signals to the memory circuit section 1001 connected via the memory circuit section connectors 1002 and 1103, and the player 101. When the batteries 808a to 808d mounted on the main body are secondary batteries, they are also used to perform the quick charging operation.

FIG. 12 is a block diagram showing an embodiment of the power supply system of the player 101. Player 1
01 is divided into a memory circuit 701 as described above, a control circuit 704 composed of a digital circuit, a digital filter 706, a digital / analog conversion circuit 707, which will be described later, and an amplification circuit 708 which outputs an analog signal. These circuit blocks have different operating voltages. For example, the storage circuit 701 requires a relatively high operating voltage of about 4 V when using the pseudo static RAM as described above. On the contrary,
The digital circuit can operate at a relatively low voltage of about 3V by using a CMOS circuit gate array or the like. The operating voltage of the amplifier circuit 708 that drives the headphones is lower and may be about 1.5V. From this, the batteries 1203, 1204, and 1205 that match the operating voltages of the respective circuits are used. The voltage is supplied to the corresponding circuits via the power switches 1206 and 1207.

As described above, by directly supplying power to the corresponding circuit by using a plurality of types of batteries having different voltage values, the battery life can be extended. For example, if the internal power supply is set to the highest voltage of 4V, useless current flows in the digital circuit and the analog circuit, and the current consumption increases. Therefore, if the above-mentioned 4V is stepped down by the internal step-down circuit, the step-down circuit also consumes current, so that the battery life is shortened. On the other hand, in this embodiment, since the minimum required battery is selected for each circuit and power is supplied to it, useless current consumption is suppressed and the substantial battery life can be extended.

In order to write a digital signal to the memory circuit 701 and / or read a digital signal at high speed, the operating current of the memory circuit 701 becomes large. Therefore, the terminal device 100 is provided with a power supply connector to supply an operating voltage of about 5 V, which is higher than the internal voltage, from the connector. In this case, the player 101 side and the terminal device 10
In order to automatically switch the power supply on the 0 side, the connector 804 and the battery 1203 are respectively connected to the diode 12
The voltage is supplied to the power supply terminal of the memory circuit 701 through 01 and 1202. In this configuration, when the player 101 is connected to the terminal device 100, the operating voltage on the terminal device 100 side is about 5V and the battery 1203 is about 4V.
The diode 1201 is turned on because it is higher than that of the memory device, and the memory circuit 701 is operated by the operating voltage from the terminal device 100 side. At this time, the diode 1202 on the battery 1203 side is reverse-biased and turned off, and no reverse current flows from the connector of the terminal device 100 to the battery 1203. When the player 101 is removed from the terminal device 100, the connector is opened, so that the diode 1202 is turned on and the battery 120 is turned on.
The voltage of 3 is supplied to the memory circuit 701. By adopting such a power supply system, it is possible to extend the battery life of the player 101 while transferring data from the terminal device 100 side to the storage circuit 701 at high speed.

FIG. 13 shows a block diagram of an embodiment of a digital signal transferred from the terminal device 100 to the player 101.

Monophonic reproduction is sufficient as a source of a digital signal that requires a wide frequency band such as a music program, one that does not require a wide frequency band such as news, or one that requires stereo reproduction. There are some. As described above, in order to effectively use the limited storage capacity of the storage circuit 701 built into the player 101 according to the source, the sampling rate, bit length, and stereo / monaural selection are selected as the digital signal according to the source. to enable. In this case, it is necessary to set the reproduction condition corresponding to each source. In this case, if the selection is performed manually, the number of display means for instructing the selection increases, and if the user is not used to handling, the sound quality will be extremely deteriorated due to the mismatch of the reproduction conditions with the source, or the reproduction will be impossible.

In order to solve such a problem, FIG.
As shown in, the ID code 1308 for specifying the reproduction condition is inserted at the beginning of the digital signal. This ID code 1
Data consisting of a digital signal to be reproduced subsequent to 308 is provided. In this way, the digital signal and the ID code 1308 for instructing the reproduction condition thereof are delivered to the player 101 as an integrated signal. As a result, the ID code 1308 and the digital signal are integrally stored in the storage circuit 701 of the player 101.
For example, in the case of adopting a method in which the ID code 1308 is separated from the digital signal and transferred to the player 101, if the power of the player 101 is cut off, the ID code 13
It is necessary to devise so that 08 will not disappear,
Such a problem does not occur when the memory circuit 701 is integrally stored with the digital signal as in the above embodiment.

FIG. 14 shows a block diagram of an embodiment of the player 101 corresponding to the digital signal into which the ID code 1308 is inserted.

The digital signal first read from the memory circuit 701 is regarded as the ID code 1308 and is stored in the register 1401. Of the ID codes 1308 fetched in this register 1401, 1300 (D
0) and 1301 (D1) are input to the multiplexer 1404, and a clock pulse corresponding to the sampling rate is selected from the four types of clock pulses formed by the clock generation circuit 1403 and transmitted to the control circuit 704. The clock generation circuit 1403 receives the reference frequency signal formed by the oscillation circuit OSC and forms four types of clock pulses corresponding to the sampling rate.

Further, 1302 (D2) is input to the bit length conversion circuit 1405. The bit length conversion circuit 1405 has a parallel / serial conversion function, and outputs the digital signal output from the storage circuit 701 in units of up to 2 bytes.
It is input to the low-pass filter 706 according to the bit length designated by 302 (D2). Low pass filter 7
Reference numeral 06 denotes a digital filter circuit, which receives a clock pulse corresponding to the sampling rate from the control circuit 704 and cuts an excess or frequency band of the input digital signal. In addition, the digital / analog conversion circuit 70
7 receives a clock pulse corresponding to the sampling rate from the control circuit 704 and converts the input digital signal into an analog signal. The amplifier circuit 708 amplifies the converted analog signal and forms a drive signal for headphones or the like. Although not shown in the figure, a low-pass filter including a resistor and a capacitor is provided at the output section of the digital / analog conversion circuit 707.

The ID code 1308 is not particularly limited, but it is 8 bits (1 to 1300 to 1307 (D0 to D7)).
Byte), and for example, 1300 and 1301 (D0 and D1) specify four sampling frequencies. If 1300 and 1301 are 00, it is 5.5125k
If Hz, 1300, 1301 is 01, 11.025kH
If z, 1300, 1301 is 10, 22.05 kHz,
If 1300 and 1301 are 11, 44.1 kHz is designated. 1302 is used to specify the resolution and is 0
If 8 bits, if 1 and 16 bits are specified. Further, 1303 (D3) is used for mode designation, 0 is monaural and 1 is stereo. And the remaining 4
Bits 1304-1307 (D4-D7) are reserved for extended functionality.

Here, the memory capacity (total number of bits M) of the storage circuit 701, the bit length N as the resolution, the sampling rate fs and the mode S (stereo S = 2, monaural S = 1) and recording / reproducing time. The relationship with t is expressed by the following equation (1).

T = M / (N × fs × S) (1) The sampling rate is not particularly limited,
44.1 kHz is used to play a super HiFi music program equivalent to a compact disc player.
10. kHz is used for playing a HiFi music program, and 11.
024 kHz is used to reproduce information programs such as news, and 5.5125 kHz is used to reproduce answering machines. If the sampling frequency is set to be doubled as described above, the player 101 may have, for example, 44.1 kHz.
Can be easily formed by forming one reference frequency corresponding to and dividing it by 1/2. Therefore, the storage / reproduction time becomes long in inverse proportion to the above four sampling frequencies fs. In other words, when a constant recording / reproducing time is obtained, the storage capacity increases in proportion to the sampling rate fs.

When the bit length is 8 bits and 16 bits, the recording / reproducing time is doubled as is apparent from the above equation (1). When the bit length is increased, the storage capacity of the storage circuit 701 needs to be doubled accordingly. On the other hand, if the bit length is reduced to 8 bits, the storage / reproduction time is doubled for the same storage capacity. The stereo mode requires twice as much data as the monaural mode. That is, since the right signal and the left signal are alternately output from the storage circuit 701 in the stereo mode, the storage capacity twice as large as that in the monaural mode is required.

In this embodiment, three reproduction conditions such as the sampling rate, the bit length and the mode as described above are set in correspondence with the source of the digital signal, and the reproduction conditions can be arbitrarily combined to reproduce. The limited storage capacity of the storage circuit can be effectively utilized to the maximum extent.
Although various combinations can be made according to these reproduction conditions, the player 1
Since it can be automatically set to 01, it is possible to reproduce the information etc. that has been handed over to anyone, without the troublesome operation.

The type or frequency of the sampling rate can be arbitrary. In this case, the clock pulse may be generated according to each sampling rate. Then, the ID code 1308 may add a bit that can be designated by the operation of the terminal device. For example, the remaining bits can be used to automatically set the slow-listening mode or fast-listening mode, which will be described later, or to automatically specify the playback mode, such as playback in program units or continuous playback of all programs. It may be performed.

FIG. 15 shows a circuit diagram of an embodiment of the quantization noise elimination circuit.

When an analog signal is digitized, quantization noise (error component) is always generated. This quantization noise becomes particularly audible when there is no sound. In this embodiment, the input section of the digital / analog conversion circuit 707 is
The following quantization noise removal circuit is provided.

The digital signal read from the storage circuit 701 is input to the digital / analog conversion circuit 707, where it is converted into the analog signal Vout. Although not particularly limited, the quantization noise elimination circuit of this embodiment is intended for the case where the digital signal is composed of 2's complement code. The digital signal composed of D0 to Dn read from the storage circuit 701 is input to the corresponding input terminals D0 to Dn of the digital / analog conversion circuit 707 via the AND circuits 1510 to 151n. The digital signal read from the storage circuit 701 is the level determination circuit 150 as indicated by the broken line in FIG.
The level judgment which is considered to be silent is performed by 7. The output signal of the level determination circuit 1507, which is considered to be silent, is input to the timer circuit 1508 shown by the broken line in the figure, and time determination is performed. The level determination circuit 1507
When the level considered to be silent by the timer circuit 1508 and the timer circuit 1508 continues for a certain time, it is determined to be a silent period, the output signal passing through the logical NOT circuit 1505 becomes logical 0, and the gates of the logical product circuits 1510 to 151n are closed. Control. That is, the logical product circuits 151 to 151n are
Regardless of the digital signal read from the memory circuit 701, the logic 0 of the output signal of the logic negation circuit 1505 forces the input signals D0 to Dn input to the digital / analog conversion circuit 707 to logic 0.

The digital signals D0 to Dn are composed of 2's complement codes as described above. That is, D0
When Dn consists of 8 bits, the maximum positive value is 01111.
At 111, the maximum negative value is 10000000 and the 0 level is 00000000. In addition, +1 in the decimal system is 00000001 in the binary system, and -1 in the decimal system is 11111111 in the binary system. Therefore,
If it is determined to be the silent period as described above, the AND circuit 15
By fixing the outputs of 10 to 151n to 0, the quantization noise in the silent period can be completely cut.

The level determination circuit 1507 shown in the figure is capable of setting a positive maximum value + ΔL and a negative maximum value −ΔL which are regarded as silence. For example, if +1 is a positive maximum value + ΔL, 00000001 is input to the input B of the comparator 1501, and if -1 is a negative maximum value −ΔL, 11111111 is input to the input B of the comparator 1509.
The digital signal from the storage circuit 701 is input to the inputs A of the comparators 1501 and 1509. The comparator 1501 forms an output signal of 1 when A ≦ B, and the comparator 1509 forms an output signal of 1 when A ≧ B. These comparators 15
The output signals of 01 and 1509 are output via the AND circuit 1502. Therefore, the digital signal is
The output of the AND circuit 1502 outputs 1 for silence detection at 01, 00000000, 11111111.

The digital signal is 00000010.
When it is larger than + ΔL, the comparator 15
The output of 01 becomes 0, and the digital signal becomes 111111.
When it is smaller than −ΔL as in 10, the comparator 1
The output of 509 becomes 0. As a result, the AND circuit 15
From 02, an output signal of 1 is formed only when the digital signal is within the range of the level which is compared with the silence.

The timer circuit 1508 is the counter circuit 15
03 and a comparator 1504. The detection output of the level determination circuit 1507 is input to the reset input R of the counter circuit 1503. When the silence state is determined, the reset of the counter circuit 1503 is released, so the counter circuit 1503 starts the counting operation of the clock pulse CK. The count output of the counter circuit 1503 is supplied to the input A of the comparator 1504. To the input B of the comparator 1504, the set time t to be regarded as a silent period is input. This allows the comparator 1504
When the silent level continues and exceeds the set time t,
The output signal (A ≧ B) is set to 1. This output signal is inverted by the logical NOT circuit 1505 and the logical product circuit 151 is output.
Since it is input to 0 to 151n, the digital signal supplied to the input of the digital / analog conversion circuit 707 is set to 0000000 level of 0000000 regardless of the digital signal read from the storage circuit 701.

In the level judgment circuit 1507, when a level of the digital signal exceeding ± ΔL is input,
The comparator 1501 or 1509 detects this and sets the output to 0, and the counter circuit 150 of the timer circuit 1508
Reset 3 This allows the timer circuit 1508
Output signal of the comparator 1504 becomes 0, and the logical product circuits 1510 to 151n are passed through the logical negation circuit 1505.
Since the control input of 1 is set to 1, the digital signal read from the storage circuit 701 is input to the input of the digital / analog conversion circuit 707. In this way, the digital signal read from the storage circuit 701 is converted into an analog signal immediately after the silent period ends.

The set time t of the timer circuit 1508 is
According to the results of experiments conducted by the inventor of the present application, a time of about 0.5 ms to 20 ms is generally desirable, though it varies depending on the contents of a music program, a news program, or the like.
Of course, setting a time slightly beyond this range does not cause a big problem. Further, the level regarded as silence may be switchable according to the input source and its resolution. For example, generally speaking, in the case of a 16-bit digital signal, it is desirable to set the range larger than that in the case of an 8-bit digital signal. Further, it is not necessary to use a 2's complement code for the digital signal, and in the case of 8 bits, 01111111 or 10000000 may be set as the AC midpoint level. When such a digital signal is used, the input of the digital / analog conversion circuit 707 is 01111111 instead of the digital signal from the storage circuit 701 when a silent period is detected by a combination of a multiplexer and a gate circuit.
Alternatively, it may be switched to 10000000.

FIG. 16 is a waveform diagram for explaining the above operation. The waveform 1600a in the figure shows the case where the digital signal from the storage circuit 701 is input as it is to the digital / analog conversion circuit to form an analog signal. As shown in the figure, in the silent period, a signal change is made in correspondence with the quantization error amount, so that it becomes uncomfortable as noise. On the other hand, in the quantization noise elimination circuit of this embodiment,
As shown in 0b, the level considered as silence is t for a certain period of time.
After that, the logical product circuits 1510 to 151n are forced to digital-to-analog convert the digital signal corresponding to the 0 level, so that the next audio signal of the 0 level from which the noise has been removed is output until the arrival. . Since the constant time t is extremely short, about 0.5 ms to 20 ms as described above, the quantization noise output during that time does not become unpleasant.

Quantization noise elimination circuit 1500 of this embodiment
Are used in the player 101 as described above,
It can be widely used as various digital audio processing circuits such as those that handle digital audio signals such as digital audio tape recorders.

FIG. 17 is a circuit diagram of an embodiment of a security circuit used in the digital signal selling system according to the present invention.

When digitalized voice information or the like is sold as a product, it is important to prevent the product from being easily copied in order to increase the product value. Therefore, first, a function is added to allow only a specific person to perform a substantial digital signal reproducing operation. Second
When a digital signal sold in the digital signal selling system of the above embodiment is transferred to the player 101, the following signal conversion is performed inside the player 101 to add a function of preventing easy copying. .

In order to perform the reproducing operation only by the specific person, or in order to permit the copying by the specific person, the exclusive output controlled by the password judgment signal is applied to the read output section of the memory circuit 701. Sum circuit 170
0 to 170n are provided. This exclusive logic circuit 170
0 to 170n are provided corresponding to all the bits of the read signals D0 to Dn, and the exclusive OR circuits 1700 to 170n may be provided only for one or a plurality of bits including at least the upper 1 bit. Good.

The digital signal transferred from the terminal device 100 (server) is directly input to the input data terminal of the storage circuit 701. The storage circuit 70
When a semiconductor memory having a common input and output of 1 is used, the exclusive OR circuits 1700 to 170n are inserted in the read signal path with respect to the signal bus to which the data terminal of the memory circuit is connected. To be done. The memory circuit 701 is
The digital signal is read by the address signal generated by the address counter 702 which receives the address update pulse.

The password is preset in the player 101 by a switch, a ROM or the like. This password is notified to the purchaser when purchasing the player 101. Therefore, when the player 101 reproduces the digital signal, the password is set. When the password registered by the comparator (not shown) and the input password match, the password determination signal is set to 0. Therefore, the exclusive OR circuit outputs the coincidence signal of 0 when 0 which coincides with 0 is input. When 1 which does not match 0 is input, a mismatch signal of 1 is output. As described above, when the password determination signal is 0, the exclusive OR circuits 1700 to 170n allow the input digital signal to pass through and be output as it is.

On the other hand, when it is determined that the password registered by the comparator (not shown) and the input password do not match, the password determination signal is set to 1. Therefore, the exclusive OR circuit outputs a coincidence signal of 0 when 1 which coincides with 1 is input. When 0, which does not match 1 described above, is input, a 1 mismatch signal is output.
Thus, when the password judgment signal is 1, the exclusive OR circuits 1700 to 170n invert the input digital signal and output it. If exclusive OR circuits 1700 to 170n are provided for digital signals of all bits as described above, all the bits are reversed when the passwords do not match, and voices that do not make sense even if the reversed bits are converted to analog. It serves as a signal to keep information confidential. In addition, when performing copying, in other words, the storage circuit 70
Even if the data of No. 1 is output to the outside, the password is required, so that easy copying can be prevented.

For some things, such as news and traffic information, it is not so important to keep it confidential. In such a case, the ID code 1308 may be used to invalidate the password. In other words,
The confidentiality protection operation may be performed on the condition that the passwords match only when the confidentiality is required by the ID code 1308. In this way, the seller can specify what needs to be protected. Also, when you receive an answering machine, you may not want others to hear it. In such cases,
The security protection may be made possible by the ID code 1308 so that the terminal device 100 performs the security protection. In any case, the troublesome operation can be minimized by requiring the password input only when the ID code 1308 truly protects the confidentiality.

FIG. 18 is a circuit diagram showing another embodiment of the security circuit used in the digital signal sales system according to the present invention. In this embodiment, the password coincidence determination signal and the exclusive OR circuits 1800 to 180
A security circuit using n is provided on the data input terminal side of the memory circuit 701. Even in this case, when the passwords do not match, each bit or 1 or an arbitrary bit of the digital signal itself written in the storage circuit 701 is inverted and converted into a meaningless voice signal.
Security can be secured as described above. In this case, when a digital signal that requires security protection is transferred from the terminal device 100, only when the password is input by the touch key of the terminal device 100 and the passwords match, the substantially valid data is transferred. When the transfer is performed and the data do not match, the bits are inverted as described above to transfer a substantially meaningless digital signal. Instead of this, the transfer operation itself may be stopped.

FIG. 19 shows a circuit diagram of still another embodiment of the security circuit used in the digital signal selling system according to the present invention. In this embodiment, a password coincidence determination signal and exclusive OR circuits 1900 to 1
A security circuit using 90 m is provided on the address input terminal side of the memory circuit 701. In this case, when the passwords do not match, the address selection of the memory circuit 701 is different from that at the input, and by inverting one or more bits, continuous addresses at the time of input are skipped at the time of output. It will change to an address. As a result, the digital signal read out by such a discontinuous address becomes meaningless as voice information any more, and the security can be protected as described above.

The embodiment of FIG. 17 or FIG. 18 and the embodiment of FIG. 19 may be combined to provide a security protection circuit using one or a plurality of exclusive OR circuits for both data and address. Good. By doing so, it is possible to further enhance the security protection by combining the data and the address.

FIG. 20 shows a circuit diagram of still another embodiment of the security circuit used in the digital signal selling system according to the present invention. This embodiment is primarily directed to copy protection of digital signals. Individual passwords are registered in the player 101 by an EPROM or the like. This password is an encryption code that is not known to the purchaser of the player 101.

Each bit of these encryption codes is supplied to one input of the exclusive OR circuits 2000 to 200n and 2010 to 201n provided at the input and output of the storage circuit 701, respectively. In the figure, an exclusive OR circuit is provided for all bits of data input and data output of the memory circuit 701, but an exclusive OR circuit is provided only for any one or a plurality of bits. 2000-2
00n and 2010-201n may be provided. However, the corresponding inputs and outputs form a pair as the exclusive OR circuits 2000 to 200n, 2010 to 201.
n is provided for each.

Exclusive OR circuit 2 with the password
The data input bits for which the inputs of 000 to 200n and 2010 to 201n are set to 0 are directly written through and the exclusive OR circuits 2000 to 20 are written by the password.
The data input bits whose inputs 0n and 2010 to 201n are set to 1 are inverted and written.

The digital signals read from the storage circuit 701 are exclusive OR circuits 2000 to 200n and 2010 to 201n controlled by the same password as described above.
By passing through, the bit of the through becomes the through as it is as described above, and the inverted bit is returned because it is inverted again. As a result, since the same digital signal as the input digital signal is transmitted to the digital / analog conversion circuit 707, voice reproduction can be performed without any problem.

On the other hand, for the connector side of the player 101, the reading of the memory circuit 701 is output as it is. In other words, the write circuit outputs the digital signal bit-converted by the password. As a result, the copied digital signal is meaningless unlike the original digital signal, so that substantial copy protection is possible. The password can be decrypted relatively easily by anyone who has knowledge of digital circuits. However, given the news, stock market prices, and selling prices of music programs, etc., the effort to destroy the above-mentioned confidentiality would be costly and would be meaningless. In other words, the security of the digital signal sales system of the present application is sufficient if easy copying and easy wiretapping can be prevented.

FIG. 21 is a circuit diagram showing still another embodiment of the security circuit used in the digital signal selling system according to the present invention. In this embodiment, a rearrangement circuit 2101 is used in place of the bit through / inversion by the exclusive OR circuit as described above. For example, the rearrangement circuit 2101 has two signal paths, one for outputting the input signal as it is, and the other one for the input side bits D0 to Dn with respect to the output side bits D0 to Dn.
A device that spatially interchanges Dn, specifically, outputs the least significant bit D0 as the most significant bit Dn,
D1 is output as D2. If the password judgment signals do not match, the above-mentioned rearrangement is performed so that the digital signal is destroyed into a meaningless one and outputted. This rearrangement circuit 2101 may be provided in the input side data instead of the exclusive OR circuit of FIG. 18, or may be provided in the address input side instead of the exclusive OR circuit of FIG.

FIG. 22 shows a concrete circuit diagram of an embodiment of the rearrangement circuit 2101 used in the security circuit.

In the same drawing, a 1-bit rearrangement circuit is illustrated as a representative for a digital signal composed of a plurality of bits.

One of a plurality of input digital signals D0 to Dn is selected by the switching circuit 2201 and output from the output terminal as the least significant bit D0. The switching circuit 2201 selects and outputs one of D0 to Dn according to the selection signal formed by the decoder 2202.

When the digital signals D0 to Dn are 8 bits, the random number circuit 2204 generates a 3-bit random number (0 to 7 in decimal) and supplies it to the input terminal B of the multiplexer 902. A 3-bit binary signal (000) designating decimal 0 corresponding to the output bit D0 is input to the other input terminal A of the multiplexer 923. Then, the password determination signal is input to the selection terminal S of the multiplexer 902. The password judgment signal becomes logical 0 when the passwords match, and the signal of the input A of the multiplexer 902 is transmitted from the output Y.

When the passwords match as described above, since decimal 0 corresponding to the output bit D0 is input to the decoder 2202 through the multiplexer 902, the decoder 2202 sends the selection signal of the input bit D0 to the switching circuit 2201. Form and supply. As a result, the switching circuit 2201 changes the input signal D0 from the output signal D0.
Is output as is. On the other hand, when the passwords do not match, the 3-bit signal generated by the random number circuit 2204 is selected and input to the decoder 2202. Accordingly, the decoder 2202 decodes the 3-bit signal and forms one selection signal from the 8-bit input signals D0 to Dn. The probability that the input signal D0 is selected is 1/8. Since a circuit similar to the above is provided for the remaining 7-bit output signals, the probability that the input signals D0 to Dn are output as they are is 1 / (8 × 8 × 8 × 8 × 8 × 8 ×) even if the passwords do not match. 8 × 8) = 1/1
It becomes extremely low like 6777216, and security protection becomes possible. The characteristic of this circuit is that the random number circuit 2204 changes the combination of changing the bit each time, so that it is possible to substantially disable the decoding of the true data from the output bit string.

Next, an embodiment of a function of preventing copying of digital signals, that is, a function of preventing the digital signals stored in the storage circuit 701 of the player 101 from being correctly read from the outside will be described. Normally, the data terminal (D in FIG. 4) of the player 101 has both an input and an output. Then, an output enable signal for putting the data terminal into an output state is given. That is, although the logic level is not particularly limited, the player 101 outputs the data terminal only when the output enable signal is valid (logic 1 in the present application). Therefore, the copy protection circuit is inserted in a portion related to the data read path, although not particularly limited thereto.

FIG. 23 is a circuit diagram of an embodiment of a security circuit suitable for copy protection used in the digital signal sales system according to the present invention. In order to permit copying by a specific person, a logical product circuit 2301 that controls the output enable signal OE by a password determination signal and a buffer circuit 23000 whose output is controlled by the output enable signal OE are provided in the read output portion of the memory circuit 701. ~ 2300n are provided. The buffer circuits 23000 to 2300n maintain the outputs in the high impedance state unless the control input becomes the logic 1. Usually, the buffer circuits 23000 to 2300n are provided corresponding to all the bits of the read signals D0 to Dn.

The digital signal transferred from the terminal device 100 is directly input to the input data terminal of the storage circuit 701. When a semiconductor memory in which the input and output of the memory circuit 701 are common is used,
The buffer sum circuit 23000 is provided in the read signal path for the signal bus to which the data terminal of the memory circuit is connected.
~ 2300n is inserted. The memory circuit 701 reads a digital signal by the address signal generated by the address counter 703 (not shown). The output enable signal OE is input to the AND circuit 2301 together with the password determination signal, and is controlled by a signal obtained by inverting the password determination signal in the logical NOT circuit 2302.

The password is preset in the player 101 by a switch, a ROM or the like. This password is notified to the purchaser when purchasing the player 101. Therefore, when reading the digital signal stored by the player 101, the password is set. When the password registered by the comparator (not shown) and the input password match, the password determination signal is set to logic 0, and the logic negation circuit 230
After being inverted by 2, it is input to the AND circuit 2301. Therefore, the AND circuit 2301 outputs the output enable signal OE.
Is a logic 0, a logic 0 is output and the output enable signal OE
Is a logic 1, a logic 1 is output. Thus, when the password determination signal is logic 0, the output enable signal O
E makes it possible to control the buffer circuits 23000 to 2300n.

On the other hand, when it is determined that the registered password and the input password do not match with each other by a comparator (not shown), the password determination signal is set to logic 1 and inverted by the logical NOT circuit 2302, and then the logical product is performed. It is input to the circuit 2301. Therefore, the AND circuit 2301
Is a logic 1 even if the output enable signal OE is a logic 0.
, A logical 0 is output. Thus, when the password determination signal is logic 1, the output enable signal OE
Irrespective of the above, the outputs of the buffer circuits 23000 to 2300n are set to the high impedance state. Therefore, when the data in the storage circuit 701 is output to the outside, a password is required, so that easy copying can be prevented.

FIG. 24 is a circuit diagram of another embodiment of a security circuit suitable for copy protection used in the digital signal selling system according to the present invention. In this example, in the read output section of the storage circuit 701, AND circuits 24010 to 2401n that control the output of the storage circuit 701 by a password determination signal and a buffer circuit 24000 whose output is controlled by the output enable signal OE.
~ 2400n are provided. Even in this case, the password discrepancy determination signal can prevent copying in the same manner as described above. From this embodiment, it can be easily inferred that, in this case, one bit or any bit of the data is targeted, and an OR circuit or an exclusive OR circuit can be used in place of the AND circuit.

FIG. 25 is a circuit diagram of still another embodiment of a security circuit suitable for copy protection used in the digital signal selling system according to the present invention. In this embodiment, the coincidence determination signal of the password and the logical product circuit 2
A security circuit using 5000 to 2500 m is provided on the address input terminal side of the memory circuit 701. In this case, when the passwords do not match, the address selection of the storage circuit 701 is different from the case of the input, and one or a plurality of bits are fixed to logic 0, so that the continuous addresses at the time of the input are output. Sometimes it changes to a random address. As a result, the digital signal read out by such a discontinuous address becomes meaningless as correct information any more, and the security can be protected as described above. It should be noted that, similarly to the embodiment shown in FIG. 24, this embodiment also deals with 1 bit or any bit of the address input, and it is possible to use an OR circuit or an exclusive OR circuit in place of the AND circuit. It can be easily analogized.

FIG. 26 is a circuit diagram showing still another embodiment of the security circuit suitable for copy protection used in the digital signal selling system according to the present invention. In this embodiment, a rearrangement circuit 2101 is used as in the embodiment of FIG. 21 in place of the bit control by the AND circuit as described above. For example, the sorting circuit 210
One has two signal paths, one outputs an input signal as it is, and the other one has input side bits D0 to Dn.
The output bits D0 to Dn are spatially interchanged with each other, specifically, the least significant bit D0 is output as the most significant bit Dn, or D1 is output as D2. If the password judgment signals do not match, the above-mentioned rearrangement is performed so that the digital signal is destroyed into a meaningless one and outputted.

FIG. 27 shows a concrete circuit diagram of an embodiment of the rearrangement circuit 2101 used in the security circuit as in FIG.

In the same figure, a 1-bit rearrangement circuit is representatively shown for a digital signal consisting of a plurality of bits.

One of a plurality of bits of input digital signals D0 to Dn is selected by the switching circuit 2201 and output from the output terminal as the least significant bit D0. The switching circuit 2201 selects and outputs one of D0 to Dn according to the selection signal formed by the decoder 2202.

When the digital signals D0 to Dn are 8 bits, the random number circuit 2204 generates a 3-bit random number (0 to 7 in decimal) and supplies it to the input terminal B of the multiplexer 902. A 3-bit binary signal (000) designating decimal 0 corresponding to the output bit D0 is input to the other input terminal A of the multiplexer 923. Then, the password determination signal is input to the selection terminal S of the multiplexer 902. The password judgment signal becomes logical 0 when the passwords match, and the signal of the input A of the multiplexer 902 is transmitted from the output Y.

When the passwords match as described above, since decimal 0 corresponding to the output bit D0 is input to the decoder 2202 through the multiplexer 902, the decoder 2202 instructs the switching circuit 2201 to select the input bit D0. To form and supply. As a result, the switching circuit 2201 changes the input signal D0 from the output signal D0.
Is output as is. On the other hand, when the passwords do not match, the 3-bit signal generated by the random number circuit 2204 is selected and input to the decoder 2202. Accordingly, the decoder 2202 decodes the 3-bit signal and forms one selection signal from the 8-bit input signals D0 to Dn. The probability that the input signal D0 is selected is 1/8. Since a circuit similar to the above is provided for the remaining 7-bit output signals, the probability that the input signals D0 to Dn are output as they are is 1 / (8 × 8 × 8 × 8 × 8 × 8 ×) even if the passwords do not match. 8 × 8) = 1/1
It becomes extremely low like 6777216, and security protection becomes possible. The characteristic of this circuit is that the random number circuit 2204 changes the combination of changing the bit each time, so that it is possible to substantially disable the decoding of the true data from the output bit string.

FIG. 28 is a circuit diagram showing still another embodiment of the security circuit suitable for copy protection used in the digital signal selling system according to the present invention. This embodiment is similar to the embodiment of FIG.
01 is used for address input. Also in FIG.
27 shows a concrete circuit diagram of an embodiment of the rearrangement circuit 2801 similar to FIG. 27 used in the security circuit. Compared to the embodiments of FIGS. 26 and 27, the present embodiment has exactly the same concept except that the bit lengths of data and addresses are different.

FIG. 30 is a block diagram of an embodiment of a digital audio signal processing circuit which realizes fast-listening and slow-listening reproduction with high sound quality.

In the digital signal sales system as described above, the information such as news and various market conditions can be heard quickly in order to listen in a short time. Also,
When the user of the player is an old person or the like, it is effective to add the slow-listening function because not only the hearing loss but also it takes time to understand the words themselves.

In an analog type recording apparatus such as a conventional cassette tape recorder, slow or fast listening can be performed by changing the tape speed from the recording time to the reproduction time. However, when the tape speed is changed in this way, the pitch (frequency) is also changed.
Also changes and loses fidelity to the original sound, making it very difficult to hear.

Therefore, it is conceivable to change the reproduction speed without changing the pitch by using a signal processing technique using a digital signal processor or the like. But,
In this case, the configuration becomes complicated and the power consumption increases, so that the portable player cannot be mounted on the portable player as described above and the price becomes expensive. Furthermore, it is effective only for voice, making it difficult to reproduce a music program.

In this embodiment, the silent period included in the voice information is utilized, the silent period is shortened or substantially deleted during the fast-listening reproduction, and the silent period is expanded or extended during the slow-listening reproduction. It is intended to be reproduced. By adopting such a method, even in fast-listening or slow-listening reproduction, since the pitch of the original sound does not change, high sound quality can be maintained. The configuration can be configured by a combination of relatively simple logic circuits as described later, and it is not necessary to use an expensive and complicated device such as a digital signal processor, and the cost can be reduced and the size can be reduced. .

The embodiment shown in FIG. 30 is an example installed in the player 101 of the digital signal selling system.

The digital audio signal read from the storage circuit 701 is input to the digital / analog conversion circuit 707 and also to the silent period detection circuit 3002. This silence period detection circuit 3002 is the same as that shown in FIG.
A circuit similar to that used for the quantization noise elimination circuit 1500 of the embodiment of FIG. 5 can be used. When the quantizing noise removing circuit 1500 is also installed, it may be shared with the quantizing noise removing circuit 1500 to use the silent period detecting circuit 3002. The output signal of the silent period detection circuit 3002 is input to the fast listening / slow listening circuit 3003. Fast-listening / slow-listening circuit 300
3 receives the control signals of the mode 1 and the mode 2, and designates fast listening or slow listening. The fast-listening / slow-listening circuit 3003 has the storage circuit 70 for the mode signal.
The operation control of the address counter 703 that forms the read address signal of 1 is performed. For example, if fast listening is designated by mode 1, when the silent period is detected, the frequency of the clock is set higher than usual and the memory circuit 70 in the silent period is set.
By speeding up the reading of 1, the silent period is substantially shortened, and fast listening reproduction is performed.

On the contrary, if the slow listening is designated by the mode 2, when the silent period is detected, the frequency of the clock is slower than usual or stopped for a fixed period and the memory circuit 7 in the silent period is stopped.
The slow-playing is performed by extending or extending the reading time of 01. The output signal of the address counter 703 is sent to the storage circuit 70 via the multiplexer 702.
Input to 1. The multiplexer 702 includes the storage circuit 7
When a digital signal is written to 01, an external address signal is input to the memory circuit 701, and when the digital signal stored in the memory circuit is read, in other words, in the reproducing operation of the digital signal, the address counter 703 generates the signal. The generated address signal is input to the memory circuit 701.

FIG. 31 is a block diagram showing a concrete example of the fast listening circuit.

In this embodiment, the silent period detection circuit 300
On the one hand, the output signal of 2 is inputted to the AND circuit 3103 via the logical NOT circuit 3102. The AND circuit 3103 is a gate circuit for inputting the digital signal from the storage circuit 701 to the digital / analog conversion circuit 707, and has the same configuration as the quantization noise removal circuit 1500. That is, this embodiment is intended to remove the quantization noise during the fast listening in the silent period at the same time.

The output signal of the silent period detection circuit 3002 is input to the control terminal S of the multiplexer 3101. The multiplexer 3101 selectively inputs the two clock pulses CK1 and CK2 to the address counter 703 according to the output signal of the silent period detection circuit 3002 input to the control terminal S. For example, clock pulse CK1
Is a clock pulse corresponding to normal reproduction, and has a frequency corresponding to the sampling rate of the digital signal. On the other hand, the clock pulse C
K2 is used for fast listening and is the clock pulse CK1.
The frequency is set to about 10 times higher.

When the fast-listening mode is designated, if the silent period detection circuit 3002 determines that there is no sound, the output signal becomes high level (logic 1). In response to this, the output signal of the logical NOT circuit 3102 is at low level (logical 0).
Therefore, since the gate of the AND circuit 3103 is closed, in the case of the digital signal of the 2's complement code as described above, the digital signal input to the digital / analog conversion circuit 707 is forced during the silent period. It corresponds to 0 level. In addition, the multiplexer 3101 changes to the clock CK1 instead of the clock CK1 due to the high level of the output signal of the silent period detection circuit 3002.
2 is input to the address counter 703. This allows
The address counter 703 performs the address update operation at a speed about 10 times that of the normal reproduction operation. As a result, the silent period is shortened to about 1/10, and fast listening reproduction is equivalently performed.

According to the experiments conducted by the inventor of the present application, the silent period accounts for about 30% to 50%, which is relatively long, with respect to the total reproduction time of various conversations and lectures from a news program of reading a manuscript. . By substantially eliminating this silent period, the reproduction time can be shortened to about 2/3 to 1/2.

When the silent period ends, the normal reproduction is immediately resumed, so that the sound quality becomes the same as the original sound, and the listening becomes very easy. In the circuit of this embodiment, when the fast listening function is stopped, for example, the output signal of the silent period detection circuit 3002 is passed through a newly added logical product circuit or the like to the control terminal S of the multiplexer 3101.
To enter. If 0 is input to the input of the AND circuit when the fast listening is not performed, the control terminal S of the multiplexer 3101 is always set to the low level. Therefore, the clock CK1 is set to the address counter 7 even in the silent period.
03, and the silence level is output for the time corresponding to the silence period. At this time, the AND circuit 3103 acts as the quantization noise removing circuit as described above to prevent the generation of quantization noise during that period.

FIG. 32 is a block diagram showing a concrete example of the delay listening circuit.

In this embodiment, a silent period which is expanded in proportion to the true silent period is produced for slow-listening reproduction. Silent period detection circuit 30 as described above
The output signal of 02 is supplied to the set input S of the flip-flop circuit 3201 on the one hand and to one input of the AND circuit 3210 on the other hand. The clock pulse CK3 for measuring the silent period is input to the other input of the AND circuit 3210. AND circuit 3
The output signal of 210 is input to the silent period counter 3202. The silent period counter 3202 counts the clock pulse CK3 while the silent period detecting circuit 3002 determines that there is no sound, thereby performing a counting operation corresponding to the silent period. The counter 3205 is an AND circuit 3
The counting operation of the clock pulse CK3 input via 211 is performed. The silent period counter 3202 performs the information holding operation together with the time measurement of the silent period, and the same clock pulse C as the silent period information.
The operation of reproducing the silent time is performed by the counter 3205 that counts K3. That is, the outputs of the silent period counter 3202 and the counter 3205 are the comparator 32.
03, and the coincidence output A = B is input to the N counter 32.
Counted by 04.

The N counter 3204 is for designating the silent period to be N times and is not particularly limited, but the N value is variable. The N counter 3204 is a programmable counter, and outputs a coincidence signal Q = N when the count value Q coincides with N to output the flip-flop circuit 320.
Reset 1 The N counter 3204 can also be realized by using a down counter circuit. The borrow output when the count value becomes 0 after the down count operation from the initial value N becomes
01 may be reset.

On the one hand, the output signal Q of the flip-flop circuit 3201 is inverted by the logical NOT circuit 3209, and the AND circuit 3208 having the quantization noise removing function is provided.
It is used as a control signal. On the other hand, the output signal Q of the flip-flop circuit 3201 is used as a control signal of the AND circuit 3211 for supplying the clock pulse CK3 to the counter 3205 or a control signal of the AND circuit 3206 via the logical NOT circuit 3207. It The logical product circuit 3206 functions as a gate circuit that selectively supplies the clock pulse CK1 to the address counter 703.

The operation of this embodiment circuit is as follows. When the silent period detection circuit 3002 detects a silent period, the AND circuit 3210 opens the gate and inputs the clock pulse CK3 to the silent period counter 3202. As a result, while the silent period detection circuit 3002 determines the silent state, the silent period counter 32
02 counts the clock pulse CK3. When the silent period detection circuit 3002 determines that the audio digital signal is input, the flip-flop circuit 3 is synchronized with the change of the detection signal from the high level to the low level.
201 is set. As a result, the output signal Q becomes high level, and instead of the digital signal from the storage circuit 701, the digital signal corresponding to the no signal level is supplied to the digital / analog conversion circuit 707.

In response to the change of the output signal Q of the flip-flop circuit 3201 to logic 1, the logic negation circuit 3207.
Output signal becomes a logic 0, closing the gate of the AND circuit 3206. As a result, the address counter 70
Since the clock pulse CK1 is not supplied to 3, the address counter 703 is left holding the previous address. In other words, the read operation of the memory circuit 701 is stopped. The flip-flop circuit 320
When the output signal Q of 1 changes to logic 1, the AND circuit 3
Since 211 opens the gate, the counter 3205 starts the counting operation of the clock pulse CK3. When this count value becomes equal to the count value of the silent period counter 3202,
The comparator 3203 outputs the coincidence signal A = B, and N
While operating the counter 3204, the counter 320
Reset 5. When the N counter 3204 counts the N value by repeating the above operation, the flip-flop circuit 3201 is reset. That is, when the silent period measured by the silent period counter 3202 is multiplied by N, the flip-flop circuit 3201 is reset. By resetting the flip-flop circuit 3201, the AND circuit 3206 opens the gate again and inputs the clock pulse CK1 to the address counter 703.
As a result, the reading of the substantial digital signal from the memory circuit 701 is restarted, and the AND circuit 32
Since 08 opens the gate and supplies the read digital signal to the digital / analog conversion circuit 707, the audio signal is output again. In this configuration, the expansion of the silent period is proportional to the original silent period. Therefore, the interval between the conversation and the lecture is expanded according to each, and it becomes easy to hear.

When counting the silent periods, the above quantization noise is output. In order to remove the quantization noise at the time of counting the silent period, for example, the output signal of the silent period detecting circuit 3002 may be inverted via the logical NOT circuit to control the AND circuit 3208. In this case, the AND circuit 3208 is 3
An input AND circuit is used, and at the time of counting the silent period, quantization noise is removed by the output signal of the added silent period detecting circuit 3002, and the silent period thereafter is expanded as described above. Flip-flop circuit 32
Quantization noise is removed by the output signal Q of 01.

FIG. 33 shows an operation waveform diagram corresponding to the fast listening circuit of FIG. The silent periods 3303 (Tm1) and 3304 (Tm2) of the original signal 3301 can be substantially deleted by switching the clock pulse supplied to the address counter 703 during that period.
In other words, without changing the pitch (frequency) of the audio signal, in other words, it is possible to listen quickly without degrading the sound quality of the audio signal.

FIG. 34 shows an operation waveform diagram corresponding to the delay listening circuit of FIG. The silent periods 3303 (Tm1) and 3304 (Tm2) of the original signal 3301 are expanded by n times as much as the operation of the address counter 703 between them is stopped by the counter 3205 and the N counter 3204. In other words, it is possible to listen slowly without degrading the sound quality of the audio signal.

FIG. 35 is a block diagram showing another embodiment of the fast listening circuit according to the present invention.

In this embodiment, the address generating operation itself is switched by using the adder circuit 3501 in the address counter 3503 for fast listening reproduction. That is, the address counter 3503 includes a register 350 that receives the adder circuit 3501 and its addition output A + B.
The output signal Q of the register 3502 is fed back to the addition input A and is also input to the multiplexer 702 as a read address of the memory circuit 701.

To the other input B of the adder circuit 3501, 1 and a positive integer M are selectively input via the multiplexer 3504. The output signal of the silent period detection circuit 3002 is supplied to the control terminal S of the multiplexer 3504. The output signal of the silent period detection circuit 3002 is also supplied to the AND circuit 3505 for removing the quantization noise through the logical NOT circuit 3209 as in the above embodiment.

When the silent period detecting circuit 3002 determines that the period is the silent period, the multiplexer 3504 selects M instead of 1 and sends it to the adding circuit 3501. Therefore,
Before entering the silent period, the adder circuit 3501 performs a +1 count operation of adding +1 to the address signal formed by the register 3502 to generate the next address signal. On the other hand, when the silent period is entered as described above, the multiplexer 3504 inputs M to the adder circuit 3501. As a result, the adder circuit 3501
+ To the address signal generated by the register 3502
M is added to generate an address signal skipped by M addresses. As a result, the address updating operation in the silent period becomes equivalently fast, and the silent period is substantially deleted as described above.

FIG. 36 is a block diagram showing another specific embodiment of the delay listening circuit according to the present invention.

In this embodiment, a slow-listening clock pulse CK4 is prepared for slow-listening reproduction. That is,
Contrary to the fast listening circuit shown in FIG. 31, a slow clock pulse CK4 is prepared for slow listening, and when the silent period starts, the multiplexer 3601 is switched to switch from the normal clock pulse CK1 to the slow listening clock pulse CK4. Switch to. When the frequency of the clock pulse CK4 is lowered to 1 / N of the clock pulse CK1, the operation of the address counter 703 is delayed N times, and the silent period can be equivalently expanded N times.

In this embodiment, since a circuit similar to that shown in FIG. 31 can be used, a clock pulse CK is applied to the input B of the multiplexer 3601 through a similar multiplexer or an appropriate switching circuit in the fast listening mode.
In the slow-listening mode, when the clock pulse CK4 is selectively supplied, fast-playing and slow-listening playback can be performed.

FIG. 37 is a block diagram showing another specific embodiment of the delay listening circuit according to the present invention.

The slow-listening mode is convenient for listening when the user is an old person or the like as described above. Therefore, even if a relatively long silent period is expanded or extended, it becomes rather difficult to hear. Therefore, in this embodiment, a function of providing a certain limit to the expansion or extension of the silent period in the slow listening mode is added.

In this embodiment, the following circuit is added based on the delay listening circuit shown in FIG. The output signal Q of the silent period counter 3202 is the multiplication circuit 370.
3 and is multiplied by N. The multiplication output multiplied by N is supplied to one input A of the multiplexer 3705 and one input A of the comparator 3706. The output signal Q of the silent period counter 3202 is supplied to one input A of the comparator 3707. The multiplexer 3705 and the two comparators 3706 and 370.
The maximum extension time K of the silent period is input to the other input of 7. The N value for multiplying the silent period by N times and the maximum extension time K are not particularly limited, but can be arbitrarily set by the user of the player within a certain range. Although not particularly limited, the maximum extension time K can be adjusted within the range of 1 to 5 seconds. According to the result of the delayed listening test by the inventors of the present application, it was determined that about 3 seconds is appropriate.

The output signal Q of the extension counter 3702 is supplied to one input A of the comparator 3704, and the output signal Y of the multiplexer 3705 is supplied to the other input B.
Is supplied. The output signal of the comparator 3706 is supplied to the control terminal S of the multiplexer 3705.
The output signals of the comparators 3704 and 3707 are passed through the logical sum circuit G4 and the flip-flop circuit 37.
14 are supplied to the reset terminal R, the reset terminal R of the silent period counter 3202, and the reset terminal R of the extension counter 3702. The flip-flop circuit 3714
Is set at the falling edge of the silent period detection circuit 3002, in other words, at the end timing of the silent period of the original signal 3301. The output signal Q of the flip-flop circuit 3714 is controlled by the logical AND circuit 3713 via the logical NOT circuit 3713 and the logical product circuit 37 for controlling the counting operation of the extension counter 3702.
11 and the logical negation circuit 3709, and is supplied to the AND circuit 3708 which controls the counting operation of the address counter 703.

FIG. 38 shows an operation conceptual diagram for explaining an example of the operation of FIG. Original signal 3 before processing
801 and Tmax corresponds to the maximum extension time K.
Thus, the silent period Td of the original signal 3801 before processing is
If it is larger than the maximum extension time K, the comparator 3
Silence period counter 3202 supplied to input A of 707
When the output signal Q of the comparator 3707 becomes larger than the maximum extension time K supplied to the input B of the comparator 3707, the comparison output A ≧ B of the comparator 3707 becomes logical 1. As a result, the flip-flop circuit 3714, the silent period counter 3202, and the extension counter 3702 are reset through the OR circuit 3701, so that the delayed listening mode is equivalently disabled. As a result, the processing becomes the same before and after the slow listening operation processing. Thus, the original signal 3801
In the case where the silent period is longer than the purpose of listening late, the extension operation of the silent period is substantially invalidated.

FIG. 39 shows an operation conceptual diagram for explaining another example of the operation of FIG. In the same figure, the original signal 3901 before processing is similar to the above, and Tma
x corresponds to the maximum extension time K. As described above, when the silent period Td of the original signal 3901 before processing is shorter than the maximum extension time K but becomes longer than the maximum extension time K when it is multiplied by N, it is calculated by the multiplication circuit 3703. The comparator 3706 detects that the silent time Td × N becomes longer than the maximum extension time K, and the comparison output A
Make ≧ B a logical one. In response to the logic 1 of the comparison output signal, the multiplexer 3705 outputs the multiplication output Td × of the input A.
Instead of N, the maximum extension time K of the input B is calculated by the comparator 37.
Tell 04. As a result, when the output signal Q of the extension counter 3702 exceeds the maximum extension delay time, the comparison output A ≧ B of the comparator 3704 becomes logical 1, and the flip-flop circuit 3714 through the logical sum circuit 3701,
Silence period counter 3202 and extension counter 3702
To reset. In this way, the processed signal 390
In No. 2, the extension time of the silent period is limited so as not to exceed the maximum extension time.

FIG. 40 shows an operation conceptual diagram for explaining still another example of the operation of FIG. Also in the figure, the original signal 4001 before processing is similar to the above, and T
max corresponds to the maximum extension time K. Thus, the silent period Td of the original signal 4001 before processing is the maximum extension time K
If it is shorter and N times that is shorter than the maximum extension time K, the comparator 3706 detects that the silent time Td × N obtained by the multiplication circuit 3703 is smaller than the maximum extension time K. Then, the comparison output A ≧ B is set to logic 0. Logic 0 of this comparison output signal
In response, the multiplexer 3705 transmits the multiplication output Td × N of the input A to the comparator 3704. As a result, when the output signal Q of the extension counter 3702 exceeds the expanded silent period Td × N, the comparator 3704.
Of the comparison output A ≧ B becomes logic 1 and the OR circuit 3701
The flip-flop circuit 3714, the silent period counter 3202, and the extension counter 3702 are reset through. In this way, the silence period of the processed signal 4002 is expanded N times.

FIG. 41 is a waveform diagram for explaining another embodiment of the fast listening and slow listening operations.

In this embodiment, a data compression function is performed in addition to fast listening and slow listening. Conversely, the silent periods 3303 and 3304 of the original signal 3301 are replaced with the silent signal 4102 (MK) like the processed signal 4101. It should be noted that the silent signal 4102 in FIG.
(MK) indicates the insertion position, and the portion where the silent signal 4102 (MK) is inserted is put into a silent state when the analog conversion is actually performed. By inserting such a silent signal 4102 (MK),
Since the silent periods 3303 and 3304 are replaced with information such as several bytes, the silent periods 3303 and 3304 included in the digital signal before analog conversion can be substantially eliminated. As a result, the storage capacity necessary for storing the digital signal can be reduced to about 1/2 to 2/3 as described above by the ratio of the silent period to the whole. When such a data compression method is adopted, the silent signal 4102 (MK) is used to selectively expand or reduce the silent signal 4102 to perform a slow-listening or fast-listening operation. be able to. For such data compression, basically the above-mentioned fast-listening circuit can be used. In the fast listening circuit, the 0 level is output in order to remove the quantization noise in the silent period, but instead of this, the silent signal 410 is output.
2 (MK) may be inserted.

FIG. 42 shows a bit pattern diagram of an embodiment of the silent signal 4102 (MK).

The silent signal 4102 (MK) is composed of a silent mark 4203 and silent period information 4204. For the silent mark 4203, a combination of bit patterns that cannot be a normal audio digital signal is selected. In this embodiment, when the digital signal is composed of a two's complement code, a combination of the maximum positive value 4201 (01111111) and the maximum negative value 4202 (1000000) is used. This combination is used as a silent mark because it does not change from a positive maximum value to a negative maximum value as a normal audio signal. As the silent mark 4203, a combination opposite to the above case, 2 bytes, or 3
It may be configured by combining bytes or 4 bytes.

The silent period information 4204 is prepared for 2 bytes, although not particularly limited thereto. In order to correspond to a silent period longer than this, 3 bytes or 4 bytes may be used as the silent period information 4204.

FIG. 43 shows a block diagram of an embodiment of a digital signal reproducing circuit including a fast-listening / slow-listening mode for a digital signal subjected to data compression as described above.

The address counter 703 receives the address counter clock ADCK via the AND circuit 4311.
Is supplied. As described above, when the silence signal 4102 (MK) is composed of the silence mark 4203 of 2 bytes and the silence time of 2 bytes, the read signal of the memory circuit 701 is:
Correspondingly, four-stage shift registers 4301a-43
It is output through 01d. These shift registers 4
The data shift clock DSCK is supplied to the 301a to 4301d via the AND circuit 4312. The outputs A and B of the shift registers 4301d and 4301c are input to the mark detection circuit 4303. Mark detection circuit 4
303 indicates that the bit patterns of the signals A and B are the maximum positive value 4201 (01111111) and the maximum negative value 42.
02 (1000000) is compared to determine whether or not it matches.
The detection signal of the mark detection circuit 4303 is used as the set signal of the flip-flops 4308 and 4309.
Outputs C and D of shift registers 4301b and 4301a
Is supplied to one input A of the comparator 4304. The output signal of the silence counter 4305 is supplied to the other input B of the comparator 4304. The output signal of the comparator 4304 is input through the logical sum circuit 4315 to the reset terminal R of the silence counter 4305 and the input CK of the repeat counter 4306 used for extending the silence period.
Is supplied to. The output Q of the repeat counter 4306 is compared with the extension magnification N by the comparator 4307.

Output Q of flip-flop circuit 4309
Through the logical NOT circuit 4314.
15 and the AND circuits 4311 and 4312. As a result, when the silent mark 4203 is detected, the operation of the address counter 703 and the shift register 430 are performed.
The shift operation of 1a to 4301d is stopped, and the silent signal 4102 (MK) is transferred to the shift registers 4301a to 430.
It is held at 1d. At this time, the memory circuit 701 is also brought into a read-out stopped state as the operation of the address counter 703 stops. The output signal of the comparator 4307 is supplied to the repeat counter 4306 and the reset terminal R of the flip-flop circuit 4309.

Output Q of flip-flop circuit 4308
Is a silence flag FLG and is used as a control signal for the AND circuit 4310 via the logical NOT circuit 4313. When the silence mark 4203 is detected in this way, the logical product circuit 4310 is immediately closed, and the positive maximum value 4201, the negative maximum value 4202, and the time information 4204 to be subsequently output are erroneously output as a voice signal. Prevent it from falling. In particular, as shown above, the maximum of positive and negative values is the silence mark 4.
When it is used as 203, if it is output as it is, large pulse noise is generated.

The silence flag of the flip-flop circuit 4308 is the four-stage D-type flip-flops 4302a to 4302a-4.
It is fed back as a reset signal of the flip-flop circuit 4308 through 302d. These flip-flop circuits 4302a to 4302d perform a silent flag transmission operation by the same data shift clock as the shift registers 4301a to 4301d, as will be described below, and when the silent period ends, the shift registers 4301a to 4301a.
The above-mentioned silence mark 4 held in 4301d
Silence signal 4102 composed of 203 and time information 4204
The period during which (MK) is swept is detected. If the flip-flop circuits 4302a to 4302d determine that the silent signal period has ended, the flip-flop circuit 4308 is reset.

When the flip-flop circuit 4309 is set by detecting the silence mark 4203, the reset state of the silence counter 4305 is released via the logical NOT circuit 4314. The silence counter 4305 starts counting operation of the silence clock SCLK in response to the release of the reset state.

In the normal reproduction mode, the N value supplied to the comparator 4307 is set to 1. As a result, the count value of the silence counter 4305 and the silence signal 410
When the silent time 4204 included in 2 (MK) matches, the repeat counter 4306 counts +1 for the match signal output by the comparator 4304, so that the count value becomes 1. As a result, the comparator 4307 also forms a coincidence output at the same time, so that the repeat counter 4306 and the flip-flop circuit 4309 are reset. By resetting the flip-flop circuit 4309, the AND circuits 4311 and 4312 open the gates, the reading of the memory circuit 701 through the address counter 703, and the shift operation of the shift registers 4301a to 4301d are restarted. The flip-flop circuits 4302a to 4302 are synchronized with the operations of the shift registers 4301a to 4301d.
d also sequentially transmits the silent flag FLG. That is, the flip-flop circuit 4308 is kept in the set state until the silent signal 4102 (MK) held in the shift registers 4301a to 4301d is swept out.
It is prohibited from being transmitted by the digital / analog conversion circuit 707 and output as voice noise. The flip-flop circuit 4308 is reset in synchronization with the sweep of the silent signal 4102 (MK). As a result, the digital voice signal output from the shift register 4301d at the final stage after the substantial silence period ends is input to the digital / analog conversion circuit 707 through the AND circuit 4310, and the voice signal is reproduced.

In the slow listening mode, the comparator 4
The N value supplied to 307 is set to a suitable integer value of 1 or greater. For example, when set to 2, the silence counter 430
When the count value of 5 and the silence period included in the silence signal 4102 (MK) rotate twice, the comparator 4307 forms a coincident output to end the doubled silence period. If N is set to 3, the silent period can be expanded and extended to three times the original silent period.

In the fast listening mode, the operation of flip-flop circuit 4309 is invalidated. Specifically, it is sufficient to prohibit the set input S of the flip-flop circuit 4309 from being supplied with the output signal of the mark detection circuit 4303 via the AND circuit or the like. In this case,
Address counter 703 and shift registers 4301a to
Since the clock is continuously supplied to 4301d, the reading operation of the memory circuit 701 is continuously performed. However, since the flip-flop circuit 4308 is set by the detection output of the mark detection circuit 4303, the silence signal 4102 (MK) is input to the digital / analog conversion circuit 707 as an audio signal by the logical NOT circuit 4313 and the logical product circuit 4310. Is prohibited. That is, the silent period is only a very short period during which the audio information is output, and the silent period can be substantially eliminated. As a result, the same fast listening as described above can be performed.

The digital signal processing circuit for realizing the above-mentioned fast-listening and / or slow-listening mode is used for a player in the digital signal delivery system as described above, and a digital audio tape (DAT).
It can be widely used for various reproducing apparatuses including a digital signal processing circuit for reproducing analog audio signals of digital audio signals.

In digital audio and the like, code compression is performed in order to lengthen the recording time. And
A known compression method that can be adopted in the digital signal delivery system presented in the present application is an adaptive P as described below.
There are CM, adaptive difference PCM, adaptive ΔM, and the like. Among them, the adaptive differential PCM system is adopted as a voice compression system such as CD-I and CD-ROM and is standardized as a standard. For data compression, various compression methods including the above-mentioned three methods and data compression and decompression methods according to the present invention described later, which are suitable for the purpose and configuration of the system, may be adopted and standardized. Is desirable.

The amplitude and frequency distribution of the acoustic signal are relatively gentle but change significantly with time. Therefore, there is adaptive PCM (APCM) as the encoding that changes the quantization step width according to the property of the nearby signal. In this adaptive PCM, the quantization step width is changed according to the amplitude of the quantized value of the immediately preceding sample. Also, the adaptive difference PCM
Is a method in which an adaptive step width is introduced into the difference PCM, and the difference from the predicted value is applied and quantized instead of the direct quantization of the signal. And ΔM is a coding method for quantizing a signal with 1 bit. This method causes large distortion when the signal changes abruptly. On the other hand, the adaptive ΔM increases the quantization step width when the same sign continues and decreases it when it inverts.

On the other hand, the adaptive PCM and adaptive difference P
Both the CM and the adaptive ΔM require a multiplication circuit for changing the step width, which requires a complicated circuit such as a microcomputer or a digital signal processor, which has a drawback of increasing the circuit scale. Further, ΔM has a drawback that quantization distortion is large and fidelity is lacking.

FIGS. 44, 45 and 46 are block diagrams showing embodiments of a data compression and expansion method according to the present invention, which has a simple structure and is suitable for downsizing and is advantageous in terms of electric power.

The object of the present embodiment is to provide a data conversion system and a data conversion circuit which can obtain high fidelity with a simple structure for data compression and expansion.

FIG. 44 is a block diagram showing an embodiment of a data conversion circuit constructed by the data conversion system according to the present invention.

Although not particularly limited, the data conversion circuit of this embodiment is directed to a circuit for converting an analog signal into 16-bit digital data and compressing it into 8-bit digital data for output. There is.

The analog signal Vin is input to the analog / digital conversion circuit 4401, where it is converted into digital data of n bits (for example, 16 bits as described above). In this embodiment, the digitally converted 16-bit data is converted into m (for example, 8 bits).
The following circuit is used for compressing the data.

The digitally converted 16-bit data D1 is input to one input of the subtractor 4402. The other input of the subtractor 4402 has a register 4406.
The 16-bit data D2 stored in is input. 16-bit data D stored in this register 4406
2 is the previous sampling data as described later. The subtractor 4402 stores the 1 stored in the register 4406 from the digitally converted input data D1.
The previous sampling data D2 is subtracted, and the difference data (D1-D2) data D3 is output. The difference data D3 is supplied to one input B of the comparator 4403. The other input A of the comparator 4403 is supplied with the data D4 corresponding to the maximum value of the compressed 8-bit data. This data D4 consists of 16 bits of 0000000011111111 as shown in the figure, and the lower 8 bits (m) are all 1s (255 in decimal).

The comparator 4403 has input terminals A and B.
Compare the magnitude of the data D3 and D4 supplied to
When A (D3> D4), a high level output signal is formed, and when A> B, a low level output signal is formed. The output signal of the comparator 4403 is used as a selector selection signal.

One input A of the selector 4404 has the maximum value data d4 (11
111111) is input, and the lower 8 bits of the data d3 of the difference data D3 are input to the input B. If the output signal of the comparator 4403 is high level, in other words, if the subtraction data D3 is larger than D4, the selector 4404 selects and outputs the maximum value data d4 of the input A, and the output signal of the comparator 4403. Is low level,
In other words, when the subtraction data D3 is smaller than D4, the lower 8-bit data d3 of the subtraction output supplied to the input B is output.

The output signal d5 of the selector 4404 is
Although not particularly limited, the data is temporarily stored in the memory circuit 4408, read out, and output as compressed 8-bit digital data Dout. The output signal d5 of the selector 4404 is supplied to one input of the adder 4405. The output data D2 of the register 4406 is supplied to the other input of the adder 4405. As a result, the adder 4405 adds the previous sampling data D2 stored in the register 4406 to the compressed data d5 output from the above-mentioned select, and adds 1 to the next input data D1. The updated sampling data D2 ′ which is immediately before is formed and stored in the register 4406. Thus, register 440
By generating the next sampling data by 6 and the adder 4405, the cumulative error can be prevented.

Thereafter, by repeating the same as above, the 16-bit (n-bit) input data D1 is converted into 8-bit (m-bit) compressed data d5.

FIG. 45 is a waveform diagram for explaining the analog / digital conversion operation accompanied by the above data compression operation.

At the start of data compression, the data in register 4406 is cleared (0000000000000000)
Has been done. Therefore, when the analog signal rises sharply as shown in the figure, it is not possible to follow the input digital signal by the progressive addition operation of the maximum value of the lower 8 bits.
Once the difference between the input digital signal and the previous sampling data becomes less than the maximum value of the compressed data,
It is possible to obtain compressed data that faithfully corresponds to changes in the input signal. In the case of an acoustic signal, its amplitude and frequency distribution are relatively gentle over time, which enables data compression with a fidelity that poses no practical problems.

FIG. 46 is a block diagram of another embodiment of the data conversion circuit according to the data conversion system of the present invention. This embodiment is directed to a circuit for expanding data compressed to m bits (for example, 8 bits) into n bits (16 bits) data corresponding to the above embodiments and converting the data into an analog signal for output. Has been.

The data Din compressed by the data compression circuit as shown in FIG. 44 is not particularly limited, but once the storage circuit 4408 of FIG. 44 to the storage circuit 4 of FIG.
It is transferred to 601 and stored. In some cases, FIG.
The memory circuit 4408 and the memory circuit 4601 in FIG. 46 are commonly used. The data d5 read from the storage circuit 4601 is supplied to one input of the adder 4602. The other input of the adder 4602 is connected to the register 460.
The n-bit data D6 stored in 3 is supplied. The adder 4602 forms the data D7 by adding the data d5 and the data D6. The data D7 is input data of the register 4603, although not particularly limited. The data D6 output from the register 4603 is digitally / decompressed as decompressed data.
It is input to the analog conversion circuit 4604 to form a demodulated analog signal Vout.

The operation of the data expansion circuit is as follows. At the start of the data expansion operation, the register 4603 is cleared as described above. The compressed data d5 read from the memory circuit 4601 is added to the data D6 of the register 4603 consisting of the preceding n bits each time it is read, and stored in the register 4603 as decompressed data.
Therefore, it is possible to restore the decompressed data that changes stepwise according to the amount of change due to the compressed data d5 as shown in FIG.

The operational effects obtained from the above embodiment are as follows.
It is as follows. That is, (1) The difference between the previous sampling data and the input data is obtained, and if the difference is larger than the maximum value of the code to be compressed, the maximum value is output, and if it is smaller, the subtraction result is output. Then, the compressed data is output to perform data compression. With this method,
For data such as an acoustic signal whose amplitude and frequency distribution are relatively gentle over time, an effect that high fidelity data compression can be performed with a simple configuration such as subtraction or addition can be obtained.

(2) According to the above (1), the data compression and decompression circuit can be realized by a simple circuit such as a subtractor, an adder, a register and a comparator, and the power consumption thereof can be suppressed small.

(3) By using the above-described data conversion system and circuit, it is possible to achieve the effect of reducing the size and weight of the player that reproduces the audio signal stored in the storage circuit.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
4, in place of the configuration in which the subtraction output data D3 and the maximum value D4 of the compressed data are compared by a comparator, any one of the higher bits of the subtraction output data D3 is 1 by using a logical sum circuit or the like. Therefore, the magnitude comparison output with the maximum value may be equivalently formed. The difference data may be obtained by subtracting the input data D1 from the register data D2.

The data-compressed input signal uses the output signal of the analog / digital conversion circuit as in the embodiment of FIG. 44, or the digitally converted data is stored in a storage circuit, a magnetic tape or a compact disk. It goes without saying that it may be a thing. The compressed data may be converted into serial data and output via a communication line or the like.

INDUSTRIAL APPLICABILITY The data conversion system and data conversion circuit according to the present invention can be widely used in circuits and devices that handle digital data that changes with the passage of time.

FIG. 47 shows a digital / digital converter according to the present invention.
A block diagram of one embodiment of an analog conversion circuit is shown. Although not particularly limited, the digital / analog conversion circuit shown in the figure is mounted on the player 101 used in the digital signal delivery system.

As a known technique of the digital / analog conversion circuit, there is the above-mentioned publication (Japanese Patent Laid-Open No. 61-236222). In this digital / analog converter circuit, pulses of a predetermined frequency are repeatedly counted by a counter, the output signal of this counter is digitally compared with the input digital signal to be converted, and the width corresponding to the value of the input digital signal is obtained. Is output, and a high-frequency component is removed from the pulse output by a filter circuit to form an analog signal.

In the above digital / analog conversion circuit, since an output signal converted into one pulse width with respect to the input digital signal is formed, when it is smoothed by the filter circuit, a ripple component occurs. There is a problem that an analog signal with good sound quality cannot be obtained. That is, it is necessary to reduce the time constant of the low-pass filter in order to improve the responsiveness (high-frequency characteristic) of the analog signal, but in this case, the ripple component increases.
If the time constant of the filter circuit is increased in order to reduce this ripple component, the responsiveness to changes in the input signal deteriorates and the high frequency characteristics deteriorate. Further, since the counter and the comparator are required, the circuit configuration becomes complicated.

The digital / analog conversion circuit of FIG. 47 is directed to the improvement of the output characteristics.

The digital / analog conversion circuit of this embodiment is constructed by the following circuit in order to remove the ripple component contained in the output signal. The input digital signal Din is taken into the register 4701. The input digital signal D fetched by this register 4701
in is supplied to one input A of the comparator 4702. The counter 4703 performs an operation of repeatedly counting the pulses as the reference time signal. This counter 4703
The carry output CAR of is supplied to the repeat counter 4704. The repeat counter 4704 outputs a carry output CAR when counting the designated repeat count value J. This carry output CAR is controlled by the control circuit 4705.
And the conversion end signal EOC is output.

When the control circuit 4705 receives the strobe synchronized with the input digital signal Din, it receives the register 470.
The set signal S is supplied to 1 to instruct the acquisition of the input digital signal Din. Also, although not particularly limited, 10
Upon receiving the reference time pulse CK of MHz, the above register 4
When the input digital signal Din to 701 is taken in,
It is supplied to the counter 4703 to start the counting operation.

The comparator 4702 has a register 470.
When the input digital signal Din taken in 1 is larger than the count value Q in the counter 4703 (A> B),
Form a high level output signal. When the count output Q of the counter 4703 becomes larger than the data line input digital signal Din (A <B), a low level output signal is formed. In this embodiment, the repeat counter 47
No. 04 is provided, the repeat counter 4704 does not immediately form an output pulse corresponding to the next input digital signal as in the conventional case, but a pulse having a pulse width corresponding to the one input digital signal Din. The conversion operation is ended by repeating the designated J times.

FIG. 48 is a waveform diagram showing an example of the operation of the digital / analog conversion circuit.

For example, when the digital input signal Din consists of 8 bits, the cycle of the clock pulse CK of 10 MHz becomes 0.1 μs as described above, and counting by using the counter composed of 8 bits makes one cycle. Becomes 25.6 μs. Therefore, when the input digital signal is the decimal system 1, a high level pulse is output only during the first 0.1 μs and a low level pulse is output during the remaining 25.5 μs. When the input digital signal is a decimal number 10, a high-level pulse is output only during the first 1 μs and a low-level pulse during the remaining 24.6 μs. Similarly, the input digital signal is decimal 1
When it is 00, a high level pulse is output only during the first 10 μs, and a low level pulse is output during the remaining 15.6 μs. When the input digital signal has a maximum value of 255 in the decimal system, a high level pulse is output for the first 25.5 μs, and a low level pulse is output only for the remaining 0.1 μs.

In the figure, the case where the number of repetitions J is 4 is shown. When the output signal converted into the pulse width as described above is repeatedly output four times, the converted output signal EOC corresponding to one input digital signal Din is output. When the repeat is performed four times as described above, the conversion is performed to form the pulse width modulation output of the above four times within one sampling period, in the period for fetching the data read from the memory circuit 701 in the player 101. The time is 25.6 × 4 = 102.4 μs, which enables a conversion frequency of about 10 KHz. This is ideal for playing news programs, conversations and lectures. In reproducing a high-quality music program, if the frequency of the clock pulse CK is set to 20 MHz, a high frequency up to about 20 kHz can be reproduced under the same four repeat times. In addition, the clock pulse CK is 10 MHz
If you keep it as it is and reduce the number of repeats to 2
High frequency up to 0 kHz can be reproduced. in this way,
The frequency of the clock pulse CK and the number of repeats may be combined to match the sampling cycle of the input digital signal.

When the conversion output signal EOC is received and the digital signal is input again in synchronization with the strobe STB, the analog / digital conversion operation corresponding to the digital signal is similarly performed.

The pulse width modulation signal output from the above comparator 4702 is the resistor 4706 and the capacitor 47.
An analog signal Dout is output after being smoothed by a low pass filter 4708 composed of 07. In this example,
A plurality of pulses pulse-width modulated as described above are output. Therefore, in order to improve the sound quality of the output signal, the resistor 4
Even if the response is enhanced by setting the time constant of 706 and the capacitor 4707 small, the ripple component can be prevented to the minimum.

In the circuit shown in this embodiment, since the entire circuit can be constructed by a digital circuit, the process is simpler than that in the case where the digital circuit and the analog circuit are mixed, and the circuit is formed by a low power consumption CMOS circuit integrated circuit or the like. can do.

FIG. 49 shows a digital / digital converter according to the present invention.
A block diagram of another embodiment of the analog conversion circuit is shown. The digital / analog conversion circuit of this embodiment is directed to simplification of the circuit.

In this embodiment, the comparator 4 of FIG.
702 is omitted, and the down counter 4901 and the flip-flop circuit 4902 form a pulse width modulation signal corresponding to a digital signal. That is, the down counter 4901 is set with the input digital signal Din in synchronization with the strobe. The strobe sets the flip-flop circuit 4902. As a result, the output signal Q of the flip-flop circuit 4902 changes to the high level, and the strobe causes the down counter 4901 to start the clock counting operation. The down counter 4901 outputs a borrow signal BO when the count value becomes 0, and the flip-flop circuit 49
02 is reset. This borrow signal BO is sent to the input side as a conversion end signal.

The flip-flop circuit 4902 is set when the counting of the digital signal is started, and is reset when the clock corresponding to the digital signal is counted. As a result, the output signal Q of the flip-flop circuit 4902 becomes a pulse width modulation signal corresponding to the input digital signal.

The signal source provided on the input side of the digital / analog conversion circuit of this embodiment is the storage circuit 701.
The digital signal and the strobe are output corresponding to the constant sampling period as shown in. Therefore, the signal source side does not immediately send the next digital signal when the conversion end signal EOC has been sent, but on the condition that this is one condition, the digital signal and strobe are synchronized with the fixed sampling period. Is sent. As a result, a pulse width modulation signal corresponding to an input digital signal of a constant cycle can be obtained by the set operation synchronized with the strobe of the flip-flop circuit 4902 and the reset operation synchronized with the borrow output BO of the down counter 4901.

For example, when the digital input signal Din consists of 8 bits, the cycle becomes 0.1 μs when the clock pulse CK of 10 MHz is used as described above, and it is counted using the down counter 4901 consisting of 8 bits. By doing so, the maximum count value becomes 25.5 μs.
Therefore, when the input digital signal is 1 in the decimal system, the down counter 4901 counts only 1, so the level is high only for the first 0.1 μs, and for the remaining 25.5 μs until the next strobe is input. A low level pulse is output. In addition, when the input digital signal is a decimal number 10, a pulse having a high level only during the first 1 μs while counting 10 and a low level pulse during the remaining 24.6 μs until the next strobe is input. Is output. Similarly, when the input digital signal is decimal 100, 10 is counted during counting 100.
A high level pulse is output only for μs, and a low level pulse is output for the remaining 15.6 μs until the next strobe is input. When the input digital signal has a maximum value of 255 in the decimal system, a high-level pulse is output for the remaining 0.1 μs during 25.5 μs corresponding to the maximum count value.

Such a pulse width modulation signal is smoothed by the low pass filter 4905 such as the resistor 4903 and the capacitor 4904 as described above, and the analog signal Vou.
t is formed.

When a plurality of pulse width modulation signals are formed with respect to one input signal Din as in the embodiment shown in FIG. 47, one input signal Din of the above-mentioned cycle is input on the input side. Strobes may be generated multiple times.

FIG. 50 shows a digital / digital converter according to the present invention.
A block diagram of yet another embodiment of an analog conversion circuit is shown.

In the digital / analog conversion circuit shown in FIG. 49, it is necessary to form a strobe with a digital signal at a constant cycle on the input side, and its application is limited. In this embodiment, the up counter 500
2 is provided to define the cycle of the pulse width modulation signal output. That is, 0 is supplied to the input D of the up counter 5002 and is cleared by the counter load pulse LD synchronized with the strobe, and the down counter 5001 takes in the input digital signal Din by the counter load pulse LD.

The same clock CK is supplied to the down counter 5001 and the up counter 5002. The borrow output BO of the down counter 5001 is supplied to one input of the AND circuit 5006 via the input K of the flip-flop circuit 5003 and the logical NOT circuit 5005.
The clock pulse is supplied to the clock terminal CK of the flip-flop circuit 5003, and the output signal of the AND circuit 5006 is supplied to the input J of the flip-flop circuit 5003. The set signal generated from the control circuit 5004 is supplied to the other input of the AND circuit 5006. The carry output CAR of the counter
Are supplied to the control circuit 5004.

The control circuit 5004 controls the digital signal Din
When receiving the strobe ST input in synchronism with the above, it is activated and outputs the counter load signal LD of the down counter 5001 and the up counter 5002 and the set signal FR of the flip-flop circuit 5003. Also,
The control circuit 5004 sends a clock pulse to the down counter 5001 and the up counter 5002 when the strobe is input in response to the clock CLK, and sends a conversion end signal EOC when it receives the carrier output CAR from the up counter 5002. It will be in a standby state.

The flip-flop circuit 5003 operates in synchronization with the rising edge of the clock pulse. If the inputs J and K are 00 (low level, low level) at that time, the flip-flop circuit 5003 is in the holding state, and the inputs J and K are 01 (low level). If the input J and K are 10 (high level, low level), it will be in the set state and the input J will be in the set state.
If K is 11 (high level, high level), the inversion operation is performed.

Next, the digital / analog conversion operation will be described in detail.

In the initial state, all counters and flip-flop circuits 5003 are in a reset state. When the conversion start signal is input to the strobe input terminal ST of the control circuit 5004, in response thereto, the control circuit 5004 sets the output signal from the conversion end signal terminal EOC to logic 1 and declares that the conversion is in progress.

The control circuit 5004 outputs the count load signal LD to load the down counter 5001 with the input digital signal and load the up counter 5002 with 0 in synchronization with the rising edge of the clock CK. Down counter 5001 and up counter 500
2 starts the clock counting operation at the end of the load.

The control circuit 5004 outputs the set signal FR of the flip-flop circuit 5003 with a delay of 1/2 cycle of the counter clock from the counter load signal LD. Since the borrow output BO of the down counter 5001 is logical 0, the input J becomes 1 and the input K becomes 0, and the flip-flop circuit 5003 is set in synchronization with the rising edge of the clock.

The down counter 5001 outputs a borrow signal BO when the count value becomes 0 by performing the down counting operation (-1) at each arrival of the clock. As a result, due to the change of the borrow signal BO to logic 1, the flip-flop circuit 5
Input J of 003 changes to 0 and input K changes to 1. As a result, the flip-flop circuit 5003 is reset in synchronization with the rising edge of the clock pulse.

When the input digital signal Din is 0 in the decimal system, the borrow output B of the down counter 5001
O and the set signal FR of the control circuit 5004 are output at the same timing. In this embodiment, a logical product circuit 5006 is provided in order to give priority to the borrow output BO of the down counter 5001, and the logical product circuit 5006 inhibits the set signal FR of the flip-flop circuit 5003 from the control circuit 5004. . Thus, when the digital signal Din is 0 in the decimal system, no pulse is output from the flip-flop circuit 5003. When the digital signal Din is 1 or more, the output Q of the flip-flop circuit 5003 outputs a pulse having a corresponding pulse width. The output signal thus pulse width modulated is supplied to the low pass filter 500.
An analog signal Vout is formed by smoothing by 7.

The up counter 5002 outputs the carry signal CAR when the counting operation is continued and reaches the maximum value.
Upon receiving the carry signal CAR, the control circuit 5004 changes the conversion end signal EOC to logic 0 and ends the series of conversion operations. After the completion of this conversion operation, the next digital signal is input. That is, when the up counter 5002 as described above is provided, it is possible to generate an address signal and read the next input digital signal by the conversion end signal EOC according to the digital / analog conversion operation.

When the input digital signal Din and the strobe are input as described above, the above operation is repeated to form the analog signal Vout corresponding to the input digital signal Din. The control circuit 5004 sets the conversion end signal EOC to a high level during the conversion operation to notify it to the outside, and does not respond to the strobe ignoring this, and continues the conversion operation.

In order to reduce the ripple component contained in the analog conversion output Vout, a repeat counter or the like is provided for the conversion start signal such as one strobe to perform the above digital / analog conversion operation. It only has to be repeated a specified number of times. If the input of the digital signal Din is not guaranteed during this repeat, a register may be provided to take in the input digital signal as described above.

The embodiment described with reference to FIGS. 47 to 50 can be widely used as a signal conversion circuit for converting a digital signal into a pulse width modulation signal in addition to the digital / analog conversion circuit.

FIG. 51 shows a basic block diagram of an embodiment of the switch input circuit of the player 101 used in the digital signal delivery system.

As described above, the player 101 is made small and thin so as to be compatible with an IC memory card or the like.
Therefore, it is important to reduce the switches that indicate the operation mode. Therefore, in this embodiment, the operation state control circuit 2 which receives the ON / OFF signal of one key switch 5101 forms the signals 5103-1 to 51013-n designating the operation states 1 to n. . By doing so, the operation switch can be mounted on the limited space of the small and thin player 101 as described above.

FIG. 52 is a block diagram for explaining an example of a specific structure of the operation state control circuit.

In this embodiment, the operating state control circuit 5102 determines the ON time T of the switch 5101.
The operation state control circuit 5102 unconditionally generates the signal 5201-1 for setting the state A to the ON time T of the switch 5101 if the switch is simply turned on. The operating state control circuit 5102 forms a signal 5201-2 for setting the state B when it is determined that the ON time T of the switch 5101 is predetermined and less than the constant time M (M> T). Then, the operation state control circuit 5102 includes the switch 5
When it is determined that the ON time T of 101 is longer than a predetermined fixed time M (M ≦ T), a signal 510 for setting the state C
Form 1-3. The following reproduction control operation can be realized by combining the signals 5101-1 to 5101-3 indicating the three states A to C as described above.

FIG. 53 is a conceptual diagram for explaining the operation mode.

[0232] The player 101 is brought into the stopped state 5302 immediately after the power is turned on. In this state 5302, when the switch 5101 is turned on, a signal 5301a indicating the unconditional state A is formed for the on time T, and the player 101 enters the reproduction state 5303. In this playback state 5303, two kinds of selections are required, either changing to the pause state 5305 or returning to the original stop state 5302. Therefore, when the switch 5101 is turned on again, the signal 530 indicating the state A as described above is displayed.
1b is formed and the time determination 5304 is entered, and the determination of the time T that is turned on at that time is performed. If this determination result is the signal 5301c indicating the state B, the player 101 is put in the pause state 5305. Alternatively, if the determination result is the signal 5301e indicating the state C, the player 101 returns to the original stopped state 5302. In the paused state 5305, it has only meaning to return to the reproduction state 5303 again. Therefore, only by turning on the switch 5101, the signal 53 indicating the state A as described above.
The playback state 5303 is restored by 01d.

When a plurality of kinds of operations are instructed by one switch, there is a drawback that the operation method becomes complicated. Therefore, in this embodiment, in order to facilitate the learning of the operation method, a light emitting diode or the like or a liquid crystal display element is provided corresponding to the stopped state 5302, the reproduction state 5303 and the paused state 5305 shown in FIG. , It is turned on in accordance with the current state, and by combining it with an arrow as shown in the figure, it is displayed what state can be changed by the input of the states A to C. When a light emitting diode is used as a display device, this display operation may be performed only for a certain period of time when a switch operation is performed in order to reduce power consumption.

FIG. 54 shows a block diagram of another embodiment for explaining the specific structure of the operation state control circuit.

In this embodiment, the switch 5 as described above is used.
Instead of the ON time T of 101, the number of times the switch 5101 is turned ON is determined by the operation state control circuit 5102. The operation state control circuit 5102 forms a signal 5401-1 that counts the number of times the switch 5101 is turned on and sets the state A when the number is one. The operating state control circuit 5102 includes a switch 510.
A signal 5401-2 for setting the state B when the number of ON times of 1 is 2
To form. Signal 5 indicating two such states A and B
The following reproduction control operation can be realized by combining 401-1 and 5401-2.

FIG. 55 is a conceptual diagram for explaining the operation mode.

Immediately after the power is turned on, the player 101 is brought into the stopped state 5302 in the same manner as described above. In this state 5302, if the switch 5101 is turned on only once,
The signal 5501a indicating the state A is formed and the player 10
1 becomes the reproduction state 5303. In this playback state 5303, two kinds of selections are required, either changing to the pause state 5305 or returning to the original stop state 5302. Therefore, when the switch 5101 is turned on only once again, the signal 5501b indicating the state A as described above is formed, and the player 101 is set to the pause state 5305. Alternatively, when the switch 5101 is turned on twice, a signal 5501e indicating the state B is formed and the player 101 returns to the original stopped state 5302. In this embodiment, in addition to returning from the pause state 5305 to the reproduction state 5303 again, the original stop state 5302 is selectively changed. Therefore, when the switch 5101 is turned on only once in the pause state 5305, the signal 5501c indicating the state A is formed and the player 101 changes to the reproduction state 5303. When the switch 5101 is turned on twice in the suspension state 5305, the signal 5501d indicating the state B is displayed.
Is formed and the player 101 changes to the stopped state 5302. Also in this embodiment, similarly to the above, by drawing the display element and the arrow corresponding to FIG. 53, the learning of the operation is facilitated.

In FIG. 56, when there are a plurality of contents to be stored, the storage circuit is divided into blocks of arbitrary size (recorded) and recorded, and at the time of reproduction, the block to be read is designated in advance by an operation switch or the like. FIG. 3 is a block diagram showing a concept of an embodiment for enabling selective reproduction, that is, so-called cueing. In addition to the data storage circuit 5610 and the data address counter 5611, a block address storage circuit 5601 for setting a block address in the data address counter 5611 that determines the storage address of the data storage circuit 5610,
A block address address counter 5602 for designating an address of the block address storage circuit, a decoder circuit 5603 for decoding the contents of the block address address counter 5602, a display 5604 for displaying the decoded contents, and a block for selecting a block. The operation switch 5607 includes a chatter killer circuit for removing the chatter. A PLAY signal (width 100n) indicating that storage / reproduction has started is sent to the circuit section.
s pulse) and a RECSTOP signal (pulse having a width of 100 ns) indicating storage stop are input.

The operation of the circuit will be described below. Here, for the sake of clarity, it is assumed that the block address address counter 5602 is zero. When the memory mode is entered in this state, data is sequentially stored from address 0 of the data memory circuit 5610. When the memory stop instruction is given at an arbitrary timing,
First, the block address address counter 5602 is incremented (the content becomes 1) at the leading edge of the RECSTOP signal, and further, the content of the data address counter 5611 is stored at address 1 of the block address storage circuit 5601 via the 100 ns delay circuit 5608. (Becomes the start address of the second data). Next, in order to store another data, when the PLAY signal is output in the storage mode, the contents of the first address of the block address storage circuit 5601 stored previously are loaded as they are to the data address counter 5611 as the leading address ( Is set) and the second data is sequentially stored. Hereinafter, every time storage stop is instructed, the contents of the data address counter 5611 are changed to the block address storage circuit 5.
It is sequentially written in 601. On the other hand, the procedure for reproduction is as follows. When you want to play the target block first, for example, the second data, use the operation switch 5
Each time 607 is pressed, the block address counter 5602
Is incremented, and the content is incremented by the decoder circuit 560.
A numeral display 5604 (which may be a simple LED display) is displayed through 3. The operation switch 5607 is continuously pressed until the target address 1 (the second address is stored at address 1) is displayed, and when the address 1 appears, the pressing is stopped. Next, when the reproduction is instructed, the PLAY signal is output and the contents of the first address, that is, the start address where the second data is stored, is the data address counter 56.
The data is loaded (set) to 11, and the reading progresses. Note that when it is desired to reproduce (same in storage) the first data, the increment operation of the block address address counter 5602 is stopped at the time when the display unit 5604 displays zero, so that the all-ZERO output of the decoder circuit 5603 becomes low. PLA to reach the level
The Y signal passes through the OR circuit 5606 to clear the data address counter. As a result, the data storage circuit 56
10 will perform the reproduction (or storage) operation from the address 0, and the first data will be reproduced (or stored).

As described above, according to this embodiment, a block to be read can be arbitrarily selected by a simple operation, and an extremely convenient device can be provided. Also,
Another feature of this embodiment is that the block length is completely arbitrary, and the data storage circuit 5610 can be used efficiently without waste. This is an example showing the effectiveness of the device of the present application, paying attention to the characteristics of the semiconductor memory and making full use of its performance. Although the memory circuit is described here as being divided into the data memory circuit 5610 and the block address memory circuit 5601, they may be arranged in the same memory.

FIG. 57 shows the memory circuit 7 of the player 101.
A conceptual diagram of an example of the storage area management system of No. 01 is shown.

Storage circuit 70 mounted on player 101
In order to efficiently use one storage capacity for a plurality of types of information, the storage circuit 701 is divided into a table of contents area and a data area. Although not particularly limited, the table of contents area has four tables of contents 5701a to 5704a, and block addresses BA0 to BA3 can be stored in each of them. The contents 5701a to 5704a are selected by the program select signals PSL1, PSL2, etc., and the block addresses BA0, BA1 etc. can be written and read.

For example, in the digital signal passing system as described above, the player 101 uses the terminal device 10
When the terminal device 100 is connected to 0, the terminal device 100 accesses the table of contents area and reads the valid block address. As a result, the terminal device 100 can know the free area of the storage circuit 701 in the player 101.
When a new digital signal to be delivered is designated, the block address is stored in the empty table of contents and the digital signal is stored in the empty area. If,
If the table of contents is insufficient, or if there is not enough free storage capacity for the digital signal to be passed, that fact is displayed and a stored digital signal that can be erased is selected. Enter. At this time, the stored digital signal stored in the player 101 is also read, and address allocation is performed again so that there is no free storage capacity in accordance with the storage capacity of the new digital signal.

In the figure, the table of contents 5701a is accessed by the program select signal PSL1, the block address BA0 stored therein is read and set in the address counter 703. For example, if the block address BA0 set in the address counter 703 is the data block 5701d at the head address of the data area as indicated by the solid line in FIG. Start. Although not particularly limited, the end mark 5701e is stored at the final address of the data, and the reading is terminated when the end mark 5701e is detected. With this configuration, the address information can be reduced because only the top address needs to be stored in the table of contents.

Also, the table of contents 5702 is accessed by the program select signal PSL2, the block address BA2 stored therein is read out, and set in the address counter 703. For example, if the block address set in the address counter 703 is an intermediate block as indicated by the dotted line in the figure, reading is started sequentially from the address where the ID code 5702i at the head of the block is stored. Then, similarly to the above, the end mark 5702e is stored at the final address of the data 5702d, and the reading is ended by the detection of the end mark 5702e.

For example, when a digital signal corresponding to the table of contents 5701a is erased or the like, there is a space between the data blocks in which the two types of programs are stored as described above.
The terminal device 100 has the block address B of the table of contents 5702a.
The block address BA2 is changed to the address of the end mark 5701e of the data area corresponding to the table of contents 5701a, and the digital signal corresponding thereto is written. By doing so, the digital signal corresponding to the newly delivered program can be continuously used in the remaining empty area.

When the player 101 is connected to the terminal device 100, the table of contents area and the data area may be cleared and a new digital signal may be stored in principle. In this case, the program to be left is player 1
01 erasure prohibition is specified, or the terminal device 100
The erase-prohibited program may be designated during the operation of exchanging the digital signal with the side.

FIG. 58 shows the memory circuit 7 of the player 101.
A conceptual diagram of another embodiment of the storage area management system 01 is shown.

In this embodiment, the table of contents storage circuit 5801 and the data storage circuit 5802 perform storage management of digital signals. Table of contents storage circuit 580
Reference numeral 1 enables storage of up to four types of digital signals (programs) such as the contents 1 to 4. The table-of-contents storage circuit 5801 stores not only the start address as in the above embodiment, but also the table of contents information in addition to the end address and the ID code. The table of contents information is not particularly limited, but is composed of character information, and a liquid crystal display device is provided in the player 101 so that the contents of the program can be displayed in characters.

Each table of contents of the table storage circuit 5801 and the data area of the data storage circuit 5802 can be arbitrarily set as data 2, data 1, data 4 and data 3 from the head address side of the data storage circuit 5802 depending on the storage order. Done. That is, the data storage circuit 5
A digital signal is stored for 802.

FIG. 59 is a block diagram showing the main part of an embodiment of the player 101 when the above-mentioned table of contents function is added.

The control circuit 5906 is provided with a switch 5907 for designating a table of contents (program designation) in addition to the switch 5908 for controlling the operation as described above. Although not particularly limited, when the switch 5907 is turned on, a +1 pulse is supplied to the table of contents address counter 5901 to access the table of contents storage circuit 5801.
The table-of-contents information read from the table-of-contents storage circuit 5801 is stored in the table-of-contents register 5909, and characters such as a title are displayed on the liquid crystal display 5910.

The head address read from the table-of-contents storage circuit 5801 is set in the address counter 5902 of the data storage circuit 5802, and the end address and ID code are loaded into the registers 5903 and 5904, respectively. The ID code is transmitted to the control circuit 5906, and is decoded to automatically set the sampling frequency, data length, stereo / monaural reproduction and the like.

The address signal output from the address counter 5902 is used for accessing the data storage circuit 5802 and also supplied to the comparator 5905. The final address loaded in the register 5903 is transmitted to the other input of the comparator 5905. As a result, when the reading of the digital signal (data) corresponding to the specified table of contents is completed, the comparator 5905 detects this and the control circuit 5
Since the end signal is input to 906, the read operation of a series of digital signals ends.

In the above-mentioned table of contents function, the number of tables of contents is not limited to four, but if it is set to the Nth power of 2, the binary address counter can be used as it is, so selection becomes easy. Further, when the table-of-contents storage circuit 5801 is provided separately from the data storage circuit 5802, each of them can be independently accessed in parallel, so that the control of the address counter is simplified. Needless to say, the table-of-contents storage circuit 5801 may be configured by utilizing a fixed storage area of the data storage circuit 5802 as in the embodiment of FIG.

FIG. 60, like FIG. 7, shows an embodiment of the player 101 according to the present invention. In this embodiment, a portion within a dashed-dotted line frame, that is, a multiplexer 702 excluding the memory circuit 701 of the player 101, an address counter 703, a control circuit 704, a parallel / serial conversion circuit 705, a low-pass filter 706, a digital / analog conversion circuit 707, A one-chip integrated circuit 6001 in which the amplifier circuit 708 is integrated into an IC or a hybrid IC is shown. This one-chip integrated circuit has a signal and a terminal for realizing data transfer of the digital signal delivery system, a signal and a terminal for controlling the storage circuit, a signal and a terminal for outputting an analog audio signal, and a one-chip integrated circuit. On the other hand, a signal and terminal for supporting the operation, a signal and terminal indicating the state of the one-chip integrated circuit, and a signal and terminal for supplying electric power to the one-chip integrated circuit are provided. The configuration of the one-chip integrated circuit does not have to include all the functions described above, and is not particularly limited.

According to the present embodiment, the main body circuit including the battery can be mounted in the ear portion of the headphone with a micro book used by a telephone operator, etc., and the power consumption can be reduced in standby mode. It measures 50 microwatts and about 20 milliwatts during playback, and it is possible to realize a compact device with extremely low power consumption. This means that even if a small-capacity (180 mAh) button-type lithium battery is used as the power supply, it is possible to reproduce for 30 consecutive hours or more, or to reproduce after 450 days even if the stored data is left as it is. It suggests. Further, these values can be significantly improved by the technological advances of batteries, and it is possible to keep a record for several years, or to realize a reproducing operation for several hundred hours or more, or a small and lightweight device.

When the control circuit is stored in a one-chip integrated circuit, there is a problem that the storage capacity of the storage circuit that can be controlled as it is is limited. to solve this problem,
As shown in FIG. 61, the storage capacity of the memory circuit can be expanded by providing an extension signal and a terminal as options to the control signal and the terminal of the memory circuit. For example, as shown in FIG. 60, when the address generated by the address counter 703 stored in the one-chip integrated circuit is 23 bits (data is 8 bits), the maximum storage capacity of the storage circuit is 8,388,608 bytes. Become. If the storage capacity is to be doubled to 16,777,216, as shown in FIG. 61, an extension address counter 6101 which operates in conjunction with the internal address counter 703 and an extension which performs the same operation as the internal multiplexer 702. An address expansion circuit composed of the multiplexer 6102 may be provided outside the one-chip integrated circuit to expand the address given to the memory circuit to 24 bits.

FIG. 62 shows a block diagram of a self-diagnosis circuit for automatically discriminating defective bits in the memory circuit and skipping defective bits in the player 101.

In the player shown in FIG. 7, the storage circuit 7
A self-diagnosis circuit is added to 01. Data input to the memory circuit 701 and 2 for memory circuit test
A multiplexer 6202 for selecting the data patterns “AA” and “55” of a kind, a ternary counter 6201 for giving a selection signal to the multiplexer 6202,
It comprises a buffer circuit 6204 for connecting the output of the multiplexer 6202 to a storage circuit, a delay circuit 6206, an address counter 703, a comparator 6203, a first-in first-out memory 6207 and the like. Input / output signals to / from the circuit unit are terminal devices 100.
Input data from the memory circuit and output data from the memory circuit, and a write strobe signal (W
E) and RUN signal (RUN) indicating storage / reproduction and two types of storage circuit test pattern data “AA”, “
55 "is input. The skip address output and the reproduction clock input are signals for skipping and reading a defective portion (defective address) of the memory circuit during the reproducing operation. Immediately after the memory data is changed, the write strobe is input. A signal (WE) is input with a pulse width of 100 ns (repetition frequency is 8 kHz), the ternary counter 6201 is cleared via the OR circuit 6213, and the OR circuit 6214 is used.
Further, it passes through a negative logical sum circuit 6205 and passes through the buffer circuit 6
It is connected to the control terminal of 204 and the WE (write enable) of the memory circuit. The buffer circuit 6204 is an element that is in a high impedance state when the control terminal is at a high level, and the input is reflected to the output terminal only when the control terminal becomes a low level. (DIO) outputs the contents of the designated address when the WE terminal is at the high level, and when the WE terminal goes to the low level, the DIO terminal switches to a state in which data can be input, and the data input at the DIO terminal is It will be written to the specified address. Therefore, if the data on the input side and the data on the output side of the buffer circuit 6204 match immediately after the WE pulse signal returns to the high level (correctly, after 50 ns of the access time of the memory circuit), the memory circuit is normal. It means that the data has been written into the memory, and if the data do not match each other, it means that the data has not been normally written into the memory circuit. In order to make such a judgment, the comparator 6
203 is provided, and the Y output of the comparator 6203 has a non-coincidence output logical configuration that becomes high level when the contents of the A input terminal and the B input terminal do not match,
The Y output of the comparator is used as one input of the AND circuit 6210. Here, the output of the NOR circuit 6205 is also input to the pulse delay circuit 6206 with a logical NOT function, and the delay circuit 6206 outputs about 200n.
It becomes the WE 'pulse sent to the s and becomes the other input of the AND circuit 6210. At this time, if the mismatch output is at the low level, that is, if the data is normally written in the memory circuit 701, nothing is output to the output of the AND circuit 6210. Here, the ternary counter 6201 is reset when the WE pulse is input (the pulse is also input to the clock input CP at the same time, but the clear operation is prioritized). Both the QA output and the QB output of the ternary counter 6201 It is at the low level, and the multiplexer 6202 has the pattern "AA" (1
Hexadecimal notation 101 in order from the 7th bit of 2 in binary notation
01010) is selected, the data normally written in the memory circuit 701 is the first test pattern. Therefore, the ternary counter 620
Since the QB output of 1 (1st bit of 2) is low level, the output becomes high level in the logic undefined circuit 6216,
The logical product circuit 6211 passes through the above WE ′, and counts up the ternary counter 6201 via the logical sum circuit 6214, whereby the multiplexer 6202 causes the test pattern “55” (hexadecimal notation 2 to 7). 01010101) in sequence from the raised bit side, and at the same time, the output of the OR circuit 6214 is the negative OR circuit 6
It becomes an input of 205 and acts as a write pulse to the memory circuit. After that, when the test pattern "55" and any stored data (stored circuit input data) are normally written, the AND circuit 6211 is prohibited (because the QB output of the ternary counter 6201 becomes high level). The loop circuit as described above is opened, the WE 'pulse passes through the AND circuit 6212 instead, the address counter 703 is counted up, and the next write pulse (WE) input from the control circuit is waited. .
The Y output of the comparator 6203 (mismatch output)
Is at a high level, that is, when data is not normally written in the memory circuit 701, the WE ′ pulse passes through the AND circuit 6210 and the contents of the address counter 703 at that time are transferred to the first-in / first-out memory 6207. Since the write operation is simultaneously input to the negative OR circuit 6205 and the OR circuit 6213, the same operation as when the WE pulse is input is repeated once again. Note that this repetitive operation is continued until data is normally written in the memory circuit 701 (the time required for this repetitive operation is about 300 ns.
Further, since the WE input period is about 125 μs, the actually allowable number of repetitions is about 400 times in the case of repeating the first pattern check, that is, the error occurrence at the time of writing the “AA” pattern, and the second time. Pattern check, that is, about 200 times in the case of repeating the error occurrence at the time of writing the "55" pattern).

According to this embodiment, a semiconductor memory chip which is discarded in the inspection because the memory cell of only a few bits out of the large capacity memory cell of the megabit class such as 4 megabit or 16 megabit is defective. Since it can be used, a very inexpensive device can be provided as a result. The basic idea of the idea described here is to inspect before writing and utilize the defective bit to make use of the result, and it goes without saying that various modifications and applications are possible using this concept. Absent. For example,
There is also a method in which when a defective bit whose test result is fixed to "1" is detected when writing "1", it is directly used as "1".

It should be noted that the multiplexer 62 in FIG.
02 operation is fixed (GA output is fixed at low level and QB output is fixed at high level by using ternary counter 6201), and simple self-diagnosis by the method of checking while writing to the memory circuit using only write data. A circuit can be constructed.

The present embodiment is particularly effective when a recording function (in the case of voice, other images, medical information, etc.) is added to the player.

FIG. 67 shows the appearance of a specific embodiment of the digital signal delivery system according to the present invention. In the figure, the same parts as those in FIG. 1, FIG. 3, FIG. 7, FIG. 10 or FIG.

Reference numeral 1001 denotes a small-sized memory circuit section mainly composed of a memory card or an IC card mainly composed of a semiconductor memory. In this embodiment, a parent for adding a further function to the player 101 or for memory expansion,
It shows a digital signal delivery system of child and grandchild type. The terminal device 100 shown in the figure has a first clock which is a sampling frequency of an analog / digital conversion circuit at the time of recording an external input signal, and a high-speed first signal for transferring a digital audio signal from the terminal device 100 to the player 101. It has two clocks. Further, the player 101 has a third clock which is the sampling frequency of the digital / analog conversion circuit during reproduction.

The player 101 also has a high-speed fourth clock for transferring a digital signal from the player 101 to the storage circuit section. The terminal device 100 and the player 101
Is used in the connected state, the fourth clock may use the second clock. In at least that case, the fourth clock can be omitted. Of these clocks, the first and third clocks for recording or reproduction can be changed respectively. In music, the sampling frequency of the voice can be made high, and a higher quality playback sound can be expected. In conversation, the sampling frequency can be reduced to save memory usage.

[0267] For example, in the usage pattern shown in the figure, a high speed is set at the second clock for selecting an arbitrary audio file from the parent terminal device 100 and transferring the information to the child player 101, which is about the size of an electronic notebook. It is possible to write the data, transfer it to a small memory card or an IC card, which becomes a grandchild in the storage circuit unit, at a high-speed fourth clock and record it, and share the recorded content with another player 101 or an electronic notebook.

It is also conceivable that the manufacturing and software development maker side provides voice information, processing programs, etc. in the form of a memory card or IC card. Furthermore, it is possible to add an optional function to the player 101, such as converting a voice signal into a sentence, to store the sentence in the storage circuit unit. Note that the grandchild's card is not limited to a card using a semiconductor memory, and in the future, media such as various ultra-small optical and magnetic disks may be used.

Although the player of this embodiment has a detachable storage circuit section shown in FIG. 10, the player is not limited to this. Information from the terminal device 100 to the player 1
In the case of transferring to 01, the player with the storage circuit section mounted is mounted in the player insertion slot 6701 of the terminal device 100, and the selected information is transferred to the player at high speed. At this time, the information to be transferred is selected from the information stored in the storage unit 303 by operating the operation switch group 6702 of the terminal device 100. At the time of reproduction, the player is pulled out from the terminal device 100 and reproduced independently. Further, the present embodiment shows a relatively large-sized embodiment intended to be installed in a store in a town or a shop in a station.

FIG. 68 shows the appearance of another specific embodiment of the digital signal delivery system according to the present invention.
1, FIG. 3, FIG. 4, FIG. 7, FIG.
Alternatively, the same parts as those in FIG. 67 are denoted by the same reference numerals and detailed description thereof will be omitted.

Reference numeral 406 denotes a speaker, 6702 denotes an operation unit for recording / reproducing, and the terminal device 100 itself also denotes a device having a recording / reproducing function. For example, the terminal device 100 is FM,
A multifunctional voice recording / reproducing apparatus having at least the functions of radio such as AM and TV, optical disc, magnetic disc, digital audio tape, timer reserved recording, and the like. It can promote and expand mediaization.

Needless to say, the shape of the terminal device 100 may be stationary or general, and may be changed depending on the environment. Also, by introducing the digital signal delivery system of the present invention into a telephone or the like, a large amount of information can be obtained by an answering machine recording function.

It should be noted that this embodiment shows a comparatively small embodiment for home use.

FIG. 69 shows the appearance of the most characteristic specific embodiment of the digital signal delivery system according to the present invention. 1, FIG. 3, FIG. 4, FIG. 7 or FIG.
The same parts as 0 are denoted by the same reference numerals and detailed description thereof will be omitted. The present embodiment has the following features in order to realize that it can be easily operated by anyone. Although not particularly shown in the present embodiment, if a touch panel is adopted for the liquid crystal display device 303 and the operation explanation and the function of the operation switch are displayed on the same screen, the operation switch is eliminated as much as possible due to the hierarchical operation screen (to be described later). Confirmation switch only). This greatly improves the usability for the user. Further, mechanical processing is performed so as to prevent the terminal device 100 from being inserted backward when inserted into the player. Further, a confirmation switch 6901 is provided in order to prevent erroneous selection of user information. After confirming the selected information using the audition function above, confirm switch 690
Information is instantly transferred to the player 101 by depressing 1. In addition to the normal operation screen, the terminal device 100 displays the battery 7 in the player 101 on the display panel 303.
The result of checking the state of 10 and a player insertion confirmation message are also displayed.

Further, the terminal device 100 and the player 101 are connected by the JEIDA standard or a connector conforming to the JEIDA standard.

The player 101 of the present embodiment gives a switch for turning on / off the power source, a switch for designating the slow / quick listening mode, a switch for designating the loudness mode, and a play / stop / pause operation. One push button switch is provided.

Further, the liquid crystal display device 303 of the terminal device 100 of the present embodiment displays characters and graphic screens in monochrome, but the present invention is not affected by this, and still images and moving images are displayed in color. But there is no problem. The operational effects obtained from the above-described examples are as follows. That is, (1) in the delivery of digital signals, a player as a terminal device is directly connected in one-to-one correspondence with a digital signal supply source, receives the specified digital signal as it is, stores it in a storage circuit, and stores it in the player alone. The reproduced digital signal is reproduced. With this configuration, the player receives the digital signal and reproduces it by itself, so that the value of the delivered digital signal can be exerted as it is.

(2) According to the above (1), it is possible to obtain an effect that processing, manufacturing, and construction of a sales system can be easily performed on the digital signal delivered as a product or the like.

(3) According to the above (1), since the player has a simplified function of recognizing the value of the delivered digital signal itself as a product or the like and simply reproducing it, Since the player has a simple structure and is easy to operate, it can be used by anyone.

(4) A terminal device for receiving and storing a digital signal from a supplier of the digital signal via a communication line or an appropriate storage medium as necessary is provided, and is connected to the player through a connector to be specified. By delivering the digital signal, it is possible to obtain the effect that the digital signal sales system as a product or the like can be performed at high speed and rationally.

(5) As a terminal device, a magnetic disk memory device having a relatively large storage capacity is used as a backup memory, and a digital signal having a large transfer amount or a digital signal updated over time can be accessed at high speed. By storing the digital signal in the buffer memory including the memory, it is possible to efficiently transfer the digital signal.

(6) As a terminal device, a microcomputer function is provided to manage the magnetic disk memory and the buffer memory, exchange digital signals with a supply source via a communication line, and store in the player. By also managing the memory area of the circuit, it is possible to simplify the player and effectively utilize the memory circuit.

(7) As a terminal device, by adding a function capable of monitoring a part of a digital signal for a fixed period of time, it is possible to prevent a mistake in selecting a desired digital signal or to select a desired digital signal. The effect that it can be easily obtained is obtained.

(8) By limiting the digital signal to be passed as a digital audio signal to audio information, the function of the player can be simplified like storage and reproduction.

(9) The transferred digital signal is I
By automatically specifying the reproduction condition in the player by adding the D code, various digital signals corresponding to the information program can be transferred and the usability thereof can be improved.

(10) By making the card-shaped storage circuit unit removable from the player main body, various RAMs, EEPROMs or ROMs can be used as the storage circuit,
The effect of diversifying functions can be obtained.

(11) The effect that the player's external shape and connector are made compatible with the existing memory card and the internal memory circuit can be used in the same manner as the existing memory card can be obtained.

(12) By virtue of the above (10) and (11), it is possible to obtain the effect of making the player multifunctional and expanding the application.

(13) A digital signal to be passed to the player because an easy copyer, wiretapping, etc. can be prevented by adding a security function to the input and / or output operation of the memory circuit according to the password or the password coincidence detection signal. The effect that the commercial value of can be increased can be obtained.

(14) By making a thin card-shaped storage device detachable as a part of the storage circuit section of the player, the storage capacity can be expanded and the program constituted by various ROMs can be played back if necessary. Therefore, the effect that various functions can be realized is obtained.

(15) As the security system, the data input and / or the data output of the storage circuit of the digital signal, or the digital signal of at least one bit of the address input section is inverted or replaced with another bit. By adopting, it is possible to obtain the effect that the security can be protected with a simple configuration.

(16) By providing the player with a storage area or table storage circuit for storing table of contents information including storage addresses corresponding to a plurality of digital signals, and a data area or data storage circuit accessed by the storage address The effect that the digital signal as a plurality of types of information can be efficiently stored in the storage circuit is obtained.

(17) For the player operation control, a player can be made smaller and thinner by designating an operation mode consisting of a plurality of types by combining the ON time or the number of times of ON of one key switch. The effect is obtained.

(18) The silent period of the digitized voice signal is detected, and the digital signal input to the digital / analog conversion circuit is forcibly replaced with a signal corresponding to an AC 0 level in the silent period. As a result, it is possible to remove the unpleasant quantization noise in the silent period.

(19) Outputs of a pair of comparators that compare the magnitude of a digital signal to be reproduced with a digital signal corresponding to the level of being regarded as silence of both positive and negative polarities, which can adjust the detection of the silent period. By forming based on the signal, the effect that the silent period can be accurately detected according to the content of the program of the digital signal is obtained.

(20) By detecting the silent period of the digitized audio signal and expanding and extending the interval, the effect of enabling delayed listening while maintaining high sound quality can be obtained.

(21) The effect that the delayed listening can be realized while maintaining the high sound quality by the simple structure that the address updating operation of the memory circuit storing the digital signal is substantially delayed as compared with the normal operation. Is obtained.

(22) By detecting the silent period of the digitized voice signal and shortening the period, the effect of enabling fast listening while maintaining high sound quality can be obtained.

(23) With the simple structure in which the address updating operation of the memory circuit in which the digital signal is stored is made faster than the normal operation, it is possible to obtain the effect that the fast listening can be realized while maintaining the high sound quality. .

(24) Data compression becomes possible by replacing the silent period of the digital signal with the silent code information and the silent time information, and the silent time corresponding to the time information is produced. By adding the above-mentioned time information to lengthen the silent time and playing it back or by ignoring it and playing back, it is possible to perform slow listening or fast listening.

(25) The effect that the digital voice signal and the silent code can be easily distinguished by combining at least two continuous digital signals corresponding to the substantially positive maximum value and the substantially negative maximum value as the silent code. Is obtained.

(26) By providing a function of setting the maximum silent time and restricting the silent period expanded with the slow listening operation so as not to exceed the maximum silent time, it is wasteful to play in the slow listening mode. The effect is that time can be lost.

(27) The difference between the immediately preceding sampling data and the input data is obtained, and if the difference is larger than the maximum value of the code to be compressed, the maximum value is output. Data is compressed by outputting the compressed data. With this method, it is possible to obtain high-fidelity data compression with a simple configuration such as subtraction or addition for data whose amplitude and frequency distribution are relatively gentle over time such as an acoustic signal.

(28) According to the above (27), the data compression and expansion circuit can be realized by a simple circuit such as a subtractor, an adder, a register and a comparator, and the power consumption thereof can be suppressed small.

(29) By using the above-described data conversion system and circuit, it is possible to achieve the effect of reducing the size and weight of the player that reproduces the audio signal stored in the storage circuit.

(30) The digital input signal is stored in the storage circuit, and the output of the counter circuit which receives the reference time pulse and performs the counting operation corresponding to the maximum value of the digital input signal is compared with the stored digital signal by the comparator. By repeating the operation of forming the pulse width modulated signal by the repeat counter a plurality of times, it is possible to obtain an effect that an analog signal with high sound quality can be obtained.

(31) A simple circuit for inputting a digital signal supplied at a constant cycle corresponding to the maximum value of the digital signal to a down counter to form a reference time pulse, a pulse corresponding to the digital signal is generated. The effect that a width modulation signal can be obtained is obtained.

(32) With a simple structure, the constant period corresponding to the maximum value of the digital signal is formed by the up-counter circuit which receives the reference time pulse and performs the counting operation corresponding to the digital input signal. The effect that a digital signal corresponding to the address conversion operation can be input is obtained.

(33) Among the functions constituting the memory card with the reproducing mechanism, the digital / analog conversion circuit excluding the storage circuit, the low-pass filter, the amplification circuit, the control circuit, and the like are integrated into a one-chip integrated circuit, which makes it extremely small. Thus, it is possible to provide a device with extremely low power consumption. or,
Mass production will be easier and cost will be reduced. (34) In the above memory card with a reproducing function, by providing a function of self-diagnosing a memory circuit and skipping a defective bit, a defective memory chip thrown away in the conventional inspection can be used, and an extremely inexpensive device. Can be provided.

(35) By adapting the player to the JEIDA standard, compatibility with the existing memory card can be secured.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in a digital signal passing system, one digital signal
Besides being sold as one product, it may be provided free of charge to a specific person instructing the player as one of services of a securities company, a financial insurance company, or the like. Alternatively, the entire digital signal may be used for exchanging necessary information on a regular basis or arbitrarily according to a collective contract. Further, the digital signal may be any signal as long as it can be transmitted by a voice signal, such as data necessary for memorization for language learning or various examinations.

Furthermore, by the digital signal delivery system as described above, instead of the conventional newspapers and weekly magazines using print characters, digital audio signals are used to provide various information and entertainment in a timely manner. It is also possible to build a highly efficient futuristic media.

The player may be provided with a connector to which an expansion ROM card or RAM card can be connected. In this case, in order to prevent the thickness of the player itself from increasing, it is preferable that the ROM card or the RAM card is composed of a thin plastic card having a built-in memory chip. The ROM card is convenient for music programs and language learning. The RAM card is an effective means for expanding the storage circuit capacity. For example, the RAM card is effective when receiving a music program or the like having a long playing time.

Various configurations can be adopted for the configuration and functions of the terminal device and player used in the digital signal delivery system. The memory circuit incorporated in the player uses a static RAM in addition to the pseudo static RAM, and a dynamic R
A memory composed of an AM and an automatic refresh circuit, and a flash memory (E
EPROM), various ROMs, or the like, or a rewritable small and thin optical disk memory may be used.

The digital signal may be a combination of character information, image information, or a voice signal and characters or image information in addition to the voice signal as described above. Thus, a display device is required to reproduce the character information and the voice information. The display device is not particularly limited, but a thin liquid crystal display device that can be made smaller and lighter may be used.

[0316]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in the delivery of a digital signal, the digital signal supply source is directly connected to the player as a terminal device, the specified digital signal is received and stored in the storage circuit, and the digital signal stored in the player alone is reproduced. In this system,
Since the player receives the digital signal in the form of the digital signal and reproduces it by itself, the value of the delivered digital signal can be exhibited as it is. Further, since the delivery can be in the form of a digital signal, the processing, manufacturing, and construction of a sales system can be easily performed, and the configuration of the player is simple and the operation is easy, and can be handled by anyone. In addition, by detecting the silent period of the digitized audio signal and expanding or shortening the silent period, it is possible to realize slow-listening playback or fast-listening playback while maintaining high sound quality. For data such as an acoustic signal whose amplitude and frequency distribution are relatively gentle over time, high-fidelity data compression and decompression processing can be realized by a simple circuit such as a subtractor, an adder, a register, and a comparator. Moreover, by performing a signal having a pulse width corresponding to the digital input signal a plurality of times in one signal conversion period, ripples when smoothed can be significantly reduced, and a high-quality analog signal can be obtained. be able to. Further, by integrating the player into a one-chip integrated circuit, an extremely small-sized device with extremely low power consumption is realized, mass production is facilitated, cost is reduced, and a defective memory chip can be used by a self-diagnosis function. An extremely inexpensive device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of a digital signal delivery system according to the present invention.

FIG. 2 is a block diagram of an input unit of the terminal device of FIG.

FIG. 3 is a block diagram of a storage unit of the terminal device of FIG.

FIG. 4 is a block diagram of an output unit of the terminal device of FIG.

FIG. 5 is a block diagram of a main part of a data input unit of the player.

6 is a principal block diagram of a data output unit of the terminal device of FIG.

FIG. 7 is a block diagram showing an embodiment of a player used in the digital signal delivery system according to the present invention.

FIG. 8 is a plan view showing an embodiment of a mounting board which constitutes the player.

FIG. 9 is a side view showing an embodiment of a mounting board in a state of being controlled by a case.

FIG. 10 is a plan view showing another embodiment of the player.

11 is a block diagram showing an embodiment of a player main body and a storage circuit section of FIG.

FIG. 12 is a block diagram showing an embodiment of a power supply system for a player.

FIG. 13 is a configuration diagram showing an embodiment of a digital signal transferred from a terminal device to a player.

14 is a block diagram showing an embodiment of a player corresponding to a digital signal into which the ID code of FIG. 13 is inserted.

FIG. 15 is a circuit diagram showing an embodiment of a quantization noise elimination circuit according to the present invention.

16 is a waveform diagram for explaining an example of the operation of the quantization noise removal circuit in FIG.

FIG. 17 is a circuit diagram showing an embodiment of a security circuit used in the digital signal sales system according to the present invention.

FIG. 18 is a circuit diagram showing another embodiment of the security protection circuit used in the digital signal sales system according to the present invention.

FIG. 19 is a circuit diagram showing another embodiment of the security protection circuit used in the digital signal sales system according to the present invention.

FIG. 20 is a circuit diagram showing another embodiment of the security circuit used in the digital signal sales system according to the present invention.

FIG. 21 is a circuit diagram showing still another embodiment of the security circuit used in the digital signal sales system according to the present invention.

22 is a specific circuit diagram showing an embodiment of a rearrangement circuit used in the security circuit of FIG.

FIG. 23 is a circuit diagram showing an embodiment of a security circuit suitable for copy protection used in the digital signal sales system according to the present invention.

FIG. 24 is a circuit diagram showing another embodiment of a security circuit suitable for copy protection used in the digital signal sales system according to the present invention.

FIG. 25 is a circuit diagram showing still another embodiment of the security protection circuit suitable for copy protection used in the digital signal sales system according to the present invention.

FIG. 26 is a circuit diagram showing still another embodiment of a security circuit suitable for copy protection used in the digital signal sales system according to the present invention.

27 is a specific circuit diagram showing an embodiment of a rearrangement circuit used in the security circuit of FIG.

FIG. 28 is a circuit diagram showing still another embodiment of the security circuit suitable for copy protection used in the digital signal sales system according to the present invention.

29 is a specific circuit diagram showing an embodiment of a rearrangement circuit used in the security circuit of FIG. 28. FIG.

FIG. 30 is a block diagram showing an embodiment of a digital audio signal processing circuit that realizes fast-listening and slow-listening reproduction according to the present invention.

FIG. 31 is a block diagram showing a specific example of the fast listening circuit according to the present invention.

FIG. 32 is a block diagram showing a specific example of the delay listening circuit according to the present invention.

FIG. 33 is an operation waveform diagram corresponding to the fast listening circuit of FIG. 31.

34 is an operation waveform diagram corresponding to the slow-listening circuit of FIG. 32.

FIG. 35 is a block diagram showing another embodiment of the fast listening circuit according to the present invention.

FIG. 36 is a block diagram showing another embodiment of the delay listening circuit according to the present invention.

FIG. 37 is a block diagram showing another specific example of the delayed listening circuit according to the present invention.

38 is an operation conceptual diagram for explaining an example of the operation of the slow-listening circuit shown in FIG. 37. FIG.

39 is an operation conceptual diagram for explaining another example of the operation of the slow listening circuit shown in FIG. 37. FIG.

FIG. 40 is an operation conceptual diagram for explaining still another example of the operation of the slow listening circuit shown in FIG. 37.

FIG. 41 is a waveform chart for explaining another embodiment of the fast listening and slow listening operations according to the present invention.

42 is a bit pattern diagram showing an example of the silent signal MK of FIG. 41. FIG.

FIG. 43 is a block diagram showing an embodiment of a digital signal reproducing circuit including a fast-listening / slow-listening mode for a data-compressed digital signal.

FIG. 44 is a block diagram showing an embodiment of a data conversion circuit configured by the data conversion system according to the present invention.

45 is a waveform chart for explaining an example of an analog / digital conversion operation accompanied by the data compression operation of FIG. 44.

FIG. 46 is a block diagram showing another embodiment of the data conversion circuit configured by the data conversion system according to the present invention.

FIG. 47 is a block diagram showing one embodiment of a digital / analog conversion circuit according to the present invention.

48 is a waveform chart showing an example of the operation of the digital / analog conversion circuit in FIG. 47.

FIG. 49 is a block diagram showing another embodiment of the digital / analog conversion circuit according to the present invention.

FIG. 50 is a block diagram showing still another embodiment of the digital / analog conversion circuit according to the present invention.

FIG. 51 is a basic block diagram showing one embodiment of a switch input circuit of a player used in a digital signal delivery system.

FIG. 52 is a block diagram showing an example of a specific configuration of the operation state control circuit.

53 is a conceptual diagram for explaining operation modes of the embodiment of FIG. 52.

FIG. 54 is a block diagram showing another example of the specific configuration of the operation state control circuit.

FIG. 55 is a conceptual diagram for explaining an operation mode of the embodiment of FIG. 54.

FIG. 56 is a block diagram showing an example of a storage area management system of a storage circuit mounted on the player.

FIG. 57 is a conceptual diagram of an embodiment of a storage area management system of a storage circuit built in a player.

FIG. 58 is a conceptual diagram of another embodiment of the storage area management system of the storage circuit built in the player.

59 is a principal block diagram showing an embodiment of the player when the table-of-contents function of FIG. 58 is added.

FIG. 60 is a block diagram showing an embodiment of a player similar to that of FIG.

FIG. 61 is a block diagram showing an example in which the memory circuit is expanded in the example of FIG. 60.

FIG. 62 is a block diagram of a main part showing an embodiment of a self-diagnosis circuit.

Fig. 63 Type of memory card according to JEIDA standard
It is an outline drawing of I

FIG. 64: Memory card type according to JEIDA standard
It is an outline drawing of II

FIG. 65 is a table showing pin arrangement of a memory card according to JEIDA standard.

FIG. 66 is a table showing signal characteristics of a memory card according to JEIDA standard.

FIG. 67 is a diagram showing an appearance of a specific example of the digital signal delivery system according to the present invention.

FIG. 68 is a diagram showing an appearance of another specific embodiment of the digital signal delivery system according to the present invention.

FIG. 69 is a diagram showing an appearance of still another specific example of the digital signal delivery system according to the present invention.

[Explanation of symbols]

100 ... Terminal device, 101 ... Memory card (player) with playback function, 102 ... Input unit, 103 ... Storage unit, 10
4 ... Output unit, 105 ... VME bus, 201 ... B-ISD
N compatible network interface, 202a, 202
b ... Low-pass filter, 203 ... Multiplexer, 20
4 ... Sample hold circuit, 205 ... Analog / digital conversion circuit, 206 ... Input control circuit, 207 ... Digital input interface, 301 ... Hard disk,
302 ... Hard disk control circuit, 303 ... Liquid crystal display device, 304 ... LCD control circuit, 305 ... VME interface, 306 ... Microprocessor, 307 ... Read only memory (ROM), 308 ... Random access memory (RAM), 309 ... internal bus, 401 ...
Output interface, 402 ... Memory card control circuit with playback function, 403 ... Buffer memory, 404 ... Monitor control circuit, 405 ... Monitor, 406 ... Speaker, 407
... power supply circuit, 501 ... input buffer, 502 ... photo sensor, 503 ... IV amplifier, 504 ... serial / parallel conversion circuit, 505 ... PLL oscillation circuit, 506 ... frequency divider circuit, 507 ... multiplexer, 508 ... mode switch, 601 ... Output buffer, 602 ... Parallel / serial conversion circuit, 603 ... Start bit addition circuit, 604
... VI amplifier, 605 ... Laser diode, 701 ...
Storage circuit, 702 ... Multiplexer, 703 ... Address counter, 704 ... Control circuit, 705 ... Parallel / serial conversion circuit, 706 ... Low pass filter, 707 ... Digital / analog conversion circuit, 708 ... Amplification circuit, 70
9 ... Large-scale integrated circuit (gate array), 710 ... Power supply circuit, 711 ... Earphone jack, 801a to 801h ...
4 Mb pseudo SRAM (static random access memory), 802 ... Memory board, 803 ... Flexible wiring board, 804 ... Connector, 805 ... Amplification circuit element, 806 ... Amplification circuit element, 807 ... Control board, 808a to 808d ... Button Battery, 1001 ... Storage circuit section, 1002 ... Storage circuit section connector, 1101 ... Control circuit, 1102 ... Storage circuit, 1103 ... Storage circuit section connector, 1104 ... Multiplexer, 1105 ... Multiplexer, 1106 ... Address counter, 1201 ... Diode, 1202 ... diode, 1203 ... battery, 1
204 ... Battery, 1205 ... Battery, 1206 ... Switch,
1207 ... Switch, 1300 ... Bit 0 (D0), 1
301 ... bit 1 (D1), 1302 ... bit 2 (D
2) 1303 ... bit 3 (D3), 1304 ... bit 4 (D4), 1305 ... bit 5 (D5), 1306 ...
Bit 6 (D6), 1307 ... Bit 7 (D7), 13
08 ... ID code, 1309 ... Data, 1401 ... Register, 1402 ... Oscillation circuit, 1403 ... Clock pulse generation circuit, 1404 ... Multiplexer, 1405 ... Bit length conversion circuit, 1500 ... Quantization noise removal circuit, 150
1 ... Comparator, 1502 ... AND circuit, 1503 ...
Counter, 1504 ... Comparator, 1505 ... Logical NOT circuit, 1507 ... Level determination circuit, 1508 ... Timer circuit, 1509 ... Comparator, 1510, 1511 ...
151n ... AND circuit, 1600a ... Signal before processing, 1
600b ... Processed signal, 1700, 1701-170
n ... Exclusive OR circuit 1800, 1801 to 180n
... Exclusive OR circuit, 1900, 1901-190 m ...
Exclusive OR circuit, 2000-200n ... Exclusive OR circuit, 2010-201n ... Exclusive OR circuit, 210
1 ... Reordering circuit, 2201 ... Switching circuit, 2202 ... Decoder, 2203 ... Multiplexer, 2204 ... Random number circuit, 23000, 2301-2300n ... Buffer circuit, 2301 ... Logical product circuit, 2302 ... Logical NOT circuit,
24000, 24001 to 2400n ... Buffer circuit,
24010, 24011 to 2401n ... AND circuit, 2
402 ... Logical NOT circuit, 2500-2500 m ... AND circuit, 2501 ... Logical NOT circuit, 2801 ... Rearrangement circuit, 2901 ... Switching circuit, 2902 ... Decoder, 29
03 ... Multiplexer, 2904 ... Random number circuit, 3001
... Headphones, 3002 ... Silent period detection circuit, 3003
… Fast listening / slow listening circuit, 3101… Multiplexer, 3
102 ... Logical NOT circuit, 3103 ... Logical product circuit, 320
1 ... Flip-flop circuit, 3202 ... Silent period counter, 3203 ... Comparator, 3204 ... N counter,
3205 ... Counter, 3206 ... AND circuit, 3207
... logical NOT circuit, 3208 ... logical product circuit, 3209 ... logical NOT circuit, 3210 ... logical product circuit, 3211 ... logical product circuit, 3301 ... original signal, 3302 ... processed signal, 330
3 ... Silent period, 3304 ... Silent period, 3401 ... Processed signal, 3402 ... Silent period, 3403 ... Silent period, 350
1 ... Adder circuit, 3502 ... Register, 3503 ... Address counter, 3504 ... Multiplexer, 3505 ... Logical product circuit, 3506 ... Logical NOT circuit, 3601 ... Multiplexer, 3602 ... Logical product circuit, 3603 ... Logical NOT circuit, 3701 ... Logical OR Circuit, 3702 ... Extension counter, 3703 ... Multiplier circuit, 3704 ... Comparator, 3
705 ... Multiplexer, 3706 ... Comparator, 3
707 ... Comparator, 3708 ... AND circuit, 370
9 ... Logical NOT circuit, 3710 ... AND circuit, 3711 ...
AND circuit, 3712 ... AND circuit, 3713 ... Logical NOT circuit, 3714 ... Flip-flop circuit, 3801 ...
Signal before processing, 3802 ... signal after processing, 3901 ... signal before processing, 3902 ... signal after processing, 4001 ... signal before processing, 4002 ... signal after processing, 4101 ... processing signal, 4102 ... silence signal, 4201 ... Maximum value of 8-bit two's complement code, 4202 ... Minimum value of 8-bit two's complement code, 4203 ... Silent mark, 4204 ... Silent period information, 4301a-4301d ... Shift register, 430
2a-4302d ... D-type flip-flop circuit, 430
3 ... Mark detection circuit, 4304 ... Comparator, 430
5: silence counter, 4306 ... repeat counter, 430
7 ... Comparator, 4308, 4309 ... Flip-flop circuit, 4310-4320 ... AND circuit, 431
3, 4314 ... Logical NOT circuit, 4315 ... Logical sum circuit,
4401 ... Analog / digital conversion circuit, 4402 ...
Subtraction circuit, 4403 ... Comparator, 4404 ... Selector, 4405 ... Addition circuit, 4406 ... Register, 440
7 ... Reference data, 4408 ... Storage circuit, 4501 ... Analog signal, 4502 ... Compressed digital signal, 460
1 ... Storage circuit, 4602 ... Addition circuit, 4603 ... Register, 4604 ... Digital / analog conversion circuit, 470
1 ... Register, 4702 ... Comparator, 4703 ... Counter, 4704 ... Repeat counter, 4705 ... Control circuit, 4706 ... Resistor, 4707 ... Capacitor, 470
8 ... Low-pass filter, 4901 ... Down counter, 4
902 ... Flip-flop circuit, 4903 ... Resistor, 49
04 ... Capacitor, 4905 ... Low-pass filter, 50
01 ... Down counter, 5002 ... Up counter, 5
003 ... Flip-flop circuit, 5004 ... Control circuit,
5005 ... Logical NOT circuit, 5006 ... AND circuit, 50
07 ... Low-pass filter, 5101 ... Switch, 510
2 ... Operating state control circuit, 5103-1 to 5103-n ...
Operating states 1 to n, 5201-1 ... State A, 5201-2
... state B, 5201-3 ... state C, 5301a ... state A, 5301b ... state A, 5301c ... state B, 530
1d ... State A, 5301e ... State C, 5302 ... Stop state, 5303 ... Playback state, 5304 ... Time determination state, 5
305 ... Suspended state, 5401-1 ... State A, 540
1-2 ... State B, 5501a ... State A, 5501b ... State A, 5501c ... State A, 5501d ... State B, 55
01e ... State B, 5601 ... Block address storage circuit, 5602 ... Block address address counter,
5603 ... Decoder circuit, 5604 ... Display, 5605
... Chatter killer circuit, 5606 ... OR circuit, 560
7 ... Switch, 5608 ... Delay circuit, 5609 ... OR circuit, 5610 ... Data storage circuit, 5611 ... Data address counter, 5612 ... Logical NOT circuit, 5701
a ... Table of contents 1, 5701d ... Data 1, 5701e ... End mark 1, 5701i ... ID code 1, 5702a ...
Table of contents 2,5702d ... Data 2,5702e ... End mark 2,5702i ... ID code 2,5703a ... Table of contents 3,5703d ... Data 3,5703e ... End mark 3,5703i ... ID code 3,5704a ... Table of contents 4,
5704d ... Data 4, 5704e ... End mark 4,
5704i ... ID code 4, 5801 ... Contents storage circuit,
5802 ... Data storage circuit, 5901 ... Table of contents address counter, 5902 ... Data address counter, 5903
... register, 5904 ... register, 5905 ... comparator, 5906 ... control circuit, 5907 ... switch, 59
08 ... switch, 5909 ... table of contents register, 5910 ...
Liquid crystal display, 6001 ... 1-chip integrated circuit, 6101 ...
Extended address counter, 6102 ... Extended multiplexer, 6103 ... Address extended circuit, 6104 ... Extended storage circuit, 6201 ... Counter, 6202 ... Multiplexer, 6203 ... Comparator, 6204 ... Buffer circuit, 6205 ... Negative OR circuit, 6206 ... Delay circuit , 6207 ... First-in first-out memory, 6210 ... AND circuit, 6211 ... AND circuit,
6212 ... AND circuit, 6213 ... OR circuit, 621
4 ... Logical sum circuit, 6215 ... Logical sum circuit, 6216 ... Logical negation circuit, 6701 ... Player insertion slot, 6701 ... Operation switch group, 6901 ... Confirmation switch.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical display location // G11B 20/10 D 7923-5D (72) Inventor Katsutaka Kimura 1-chome, Higashi Koikeku, Kokubunji City 280 In the Central Research Laboratory of Hitachi, Ltd. (72) Inventor Toshio Sasaki 1-280 Higashi Koikekubo, Kokubunji City, Tokyo 280 In the Central Research Laboratory of Hitachi, Ltd. (72) 1-280 Higashi Koikeku Ku, Kokubunji City, Tokyo 280 Hitachi, Ltd. Central Research Laboratory (72) Inventor Isamu Oda 1-280 Higashi Koikeku, Kokubunji, Tokyo Metropolitan Institute of Hitachi, Ltd. (72) Katsuro Sasaki 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Co., Ltd. In-house (72) Inventor Naoki Ozawa 1-280, Higashi Koigokubo, Kokubunji, Tokyo Local Hitachi, Ltd. Central Research Laboratory (72) Inventor Kazuhiro Kondo 1-280, Higashi Koikeku, Kokubunji, Tokyo Metropolitan Institute Central Research Institute (72) Inventor Toshiaki Masuhara 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. (72) Inventor Tadashi Onishi 1-280, Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Hidehito Obayashi 1-280, Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Central Research Center, Hitachi, Ltd. (72) Inventor Kiyoshi Aiki 1-280, Higashi Koigokubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Yasushi Horikoshi 1-280, Higashi Koigokubo, Kokubunji, Tokyo, Hitachi Research Center, Ltd.

Claims (41)

[Claims] 1. A digital signal supply source and a digital signal which is connected to the digital signal supply source when the digital signal is transferred, receives the specified digital signal, stores it in a storage circuit, and reproduces the stored digital signal independently. A digital signal delivery system comprising a memory card with a reproducing function. 2. The digital signal transfer system, wherein the digital signal is transferred between the digital signal supply source and the memory card with a reproducing function at a speed higher than at least a signal to be processed. Item 1. A digital signal passing system. 3. The digital signal supply source is connected to the digital signal supply source in the delivery of the digital signal, and is received by the specified digital signal and stored in a storage circuit to reproduce the stored digital signal by itself. In the digital signal delivery system including a memory card with a reproducing function, the digital signal supply source supplies a digital signal from the supply source and a digital signal from the supply source via a communication line or an appropriate storage medium as needed. 2. The digital signal delivery system according to claim 1, further comprising: a terminal device which receives and stores the digital signal and which is connected to the memory card having the reproducing function and which is connected via a connector to deliver the specified digital signal. . 4. The digital signal delivery system according to claim 3, wherein the storage capacity of the terminal device is the same as or larger than the storage capacity of the storage circuit on the memory card with a reproducing function. . 5. The terminal device uses a magnetic disk memory device having a relatively large storage capacity as a backup memory, and is updated with a large amount of digital signals transferred to and from a memory card with a reproducing function or with the passage of time. 4. The digital signal delivery system according to claim 3, wherein the digital signal is stored in a buffer memory composed of a semiconductor memory which can be accessed at high speed. 6. The terminal device has a microcomputer function, manages the magnetic disk memory and the buffer memory, transmits and receives a digital signal to and from a supplier through a communication line, and in a connected state. 6. The digital signal delivery system according to claim 3, wherein the storage area for a storage circuit in the memory card with a reproducing function is also managed. 7. The digital signal delivery system according to claim 3, wherein said terminal device has a function of reproducing and outputting a part of the designated digital signal only for a fixed time. 8. A digital signal supply source and a digital signal supply source are connected to the digital signal supply source for receiving and storing the specified digital signal in a storage circuit and reproducing the stored digital signal independently. In a digital signal transfer system including a memory card with a reproducing function, the memory card with a reproducing function has a built-in secondary battery, and when connected to the terminal device, the secondary battery is supplied to the secondary battery by a power source of the terminal device side. A memory card with a playback function that is also charged. 9. The reproduction card according to claim 8, wherein the memory card with a reproduction function comprises a reproduction output circuit for converting a digital audio signal read from the storage circuit into an analog audio signal and outputting the analog audio signal. Memory card with functions. 10. The memory card with a reproducing function according to claim 9, wherein the memory card with a reproducing function is separated from or attached to a thin card-shaped storage medium. 11. The memory card with a reproducing function according to claim 9, wherein the memory card with a reproducing function has an ID code and a reproducing condition is automatically designated according to the content of the ID code. 12. The memory card with a reproducing function according to claim 11, wherein the reproduction condition includes at least one of stereo / monaural reproduction, 8-bit and 16-bit resolution, and sampling frequency. 13. A digital signal source and a digital signal source connected to the digital signal source for the delivery of the digital signal, and receives the specified digital signal and stores it in a memory circuit, and reproduces the stored digital signal independently. In a digital signal delivery system including a memory card with a playback function, the memory card with a playback function has a storage circuit for storing and controlling the digital signal, a connector for delivering and receiving a signal from the outside, and an operation unit for controlling playback. A memory card with a playback function that is characterized. 14. The delivery connector is JEIDA.
The memory card with a reproducing function according to claim 13, which is a connector conforming to the standard or the JEIDA standard. 15. A digital signal supply source and a digital signal which is connected to the digital signal supply source when the digital signal is transferred, receives the specified digital signal and stores it in a storage circuit, and reproduces the stored digital signal independently. In a digital signal delivery system including a memory card with a reproducing function, the storage circuit inverts at least one bit digital signal of an input and / or output unit of the storage circuit according to a password or a password match detection signal, or A memory circuit having a security function that replaces other bits and does not reproduce a correct digital signal for the user. 16. The storage circuit inverts a digital signal of at least one bit of an address input section of the storage circuit in accordance with a password or a password coincidence detection signal, or replaces it with another bit to correct a digital signal for a user. 16. The storage circuit according to claim 15, which has a security function of not reproducing a signal. 17. The memory card with a reproducing function, wherein the memory circuit invalidates or replaces at least one bit digital signal of the output part of the memory circuit in accordance with a password or a password match detection signal. 16. The memory circuit according to claim 15, which has a security function for preventing a correct digital signal from being read from the outside. 18. A memory with a reproducing function, wherein said memory circuit invalidates or replaces at least one bit digital signal of an address input section of said memory circuit in accordance with a password or a password match detection signal. 16. The memory circuit according to claim 15, which has a security function for preventing the correct digital signal from being read out from the card. 19. The storage circuit is divided into arbitrary storage capacities to store a plurality of different information, and a user can select arbitrary information from the stored information during reproduction. The memory circuit according to claim 15. 20. The storage circuit comprises a storage area or a table storage circuit for storing table of contents information including storage addresses corresponding to a plurality of digital signals, and a data area or a data storage circuit accessed by the storage address. 16. The memory circuit according to claim 15, wherein the memory circuit comprises: 21. The memory card with a reproducing function according to claim 13, wherein the operation section is capable of designating a plurality of types of operation modes according to the ON time or the number of times of ON of one key switch. . 22. A digital signal supply source is connected to the digital signal supply source in the delivery of the digital signal, and the specified digital signal is received and stored in a storage circuit, and the stored digital signal is reproduced independently. In a digital signal transfer system including a memory card with a reproducing function, a trowel provided with means for compressing or expanding the information amount with respect to the original information amount of the digital signal and noise removing means for removing noise. Characteristic digital signal delivery system. 23. The noise eliminating means detects the silent period of the digitized voice signal and the digital signal inputted to the digital / analog conversion circuit in the silent period is forcibly set to an AC 0 level. 23. Means for replacing with a corresponding signal.
Digital signal delivery system. 24. The noise removing means comprises means for comparing, when the silent period is within a predetermined level based on the comparison result, with a comparing means for comparing a predetermined level, which is regarded as silence of both positive and negative polarities, with a digital signal. 23. The digital signal delivery system according to claim 22, wherein the system is in a silent state for a predetermined period. 25. The decompressing means detects a silent period of a digitized audio signal, and means for expanding the silent period carries out slow listening reproduction.
2. Digital signal delivery system. 26. The means for expanding the silent period is performed by substantially delaying an address updating operation of a memory circuit storing a digital signal as compared with a normal operation. 25 digital signal delivery system. 27. A digital signal delivery system according to claim 22, wherein said compressing means detects a silent period of the digitized audio signal, and shortens the silent period for fast listening reproduction. 28. The digital signal processing method according to claim 27, wherein the means for shortening the silent period is performed by accelerating an address updating operation of a memory circuit storing a digital signal as compared with a normal operation. Signal passing system. 29. The means for compressing obtains the difference between the sampling data immediately before the digital signal and the input data, and if the result is larger than the maximum value of the code to be compressed, it is compressed. 23. The digital signal delivery system according to claim 22, comprising means for outputting a maximum value of data and means for outputting a subtraction result by the compressed data when the data is small. 30. The digital signal according to claim 22, wherein said decompression means decompresses the data of said digital signal into the original data by adding it to the previous sampling data. Signal passing system. 31. Data compression is performed by replacing the silent period of a digital signal with silent code information and silent time information, and when the silent code information is detected during normal operation, a memory circuit is provided for a time corresponding to the silent time information. Address updating operation is stopped and a signal corresponding to AC 0 level is output instead of it, and when the silent code information is detected during the slow listening reproduction operation, the memory circuit is expanded over the silent time information. The address update operation is stopped and a signal corresponding to an AC level of 0 is output instead of the address update operation. During the fast listening operation, the silent code information and the silent time information are substantially ignored and a digital signal is output. A digital signal processing circuit characterized by the following. 32. The silent code information is constituted by a combination of at least two continuous digital signals corresponding to a substantially positive maximum value and a substantially negative maximum value. Digital signal processing circuit. 33. A digital signal processing circuit as set forth in claim 31, further comprising a function of setting a maximum silence period and limiting a silence period expanded due to a slow listening operation so as not to exceed the maximum silence period. . 34. A storage circuit for receiving a digital input signal, a counter circuit for receiving a reference time pulse and performing a counting operation corresponding to the maximum value of the digital input signal, an output signal of the storage circuit and an output signal of the counter circuit. A comparator for comparison, a repeat counter for counting the repeated counting operation of the counter circuit, an instruction to receive an input digital signal to the memory circuit in response to a strobe signal, and to start the counting operation of the counter circuit to start the repeat operation. A signal conversion circuit including a control circuit for transmitting a conversion end signal according to an output signal from a counter, and obtaining a pulse width modulation signal corresponding to a digital input signal from the output of the comparator. 35. A down counter circuit for receiving a digital input signal supplied at a constant cycle corresponding to the maximum value of a digital signal and counting a reference time pulse, and forming a pulse corresponding to an operation period of the down counter circuit. And a digital circuit for obtaining a pulse width modulated signal corresponding to the digital input signal. 36. The constant period corresponding to the maximum value of the digital signal is formed by an up counter circuit which receives the reference time pulse and performs a counting operation corresponding to the digital input signal. Claim 3
5 signal conversion circuit. 37. The pulse width modulated signal is input to a low pass filter composed of a resistor and a capacitor and converted into an analog signal.
Signal conversion circuit. 38. A digital voice signal is stored in a memory circuit, the digital voice signal is read out from the memory circuit independently, the digital voice signal is converted into an analog voice signal by a digital / analog conversion circuit, and the signal is passed through a low-pass filter. In a digital audio signal reproducing circuit having a reproducing circuit for amplifying and outputting by an amplifier circuit, a one-chip integrated circuit consisting of a digital / analog conversion circuit excluding the memory circuit, a low-pass filter, an amplifier circuit, a control circuit and an interface section. One-chip integrated circuit characterized by being stored in. 39. The digital audio signal reproducing circuit has a function of easily expanding the memory circuit control function outside the one-chip integrated circuit when the memory capacity becomes larger than the controllable memory capacity. 39. The one-chip integrated circuit according to claim 38. 40. A signal terminal for allowing the interface section of the one-chip integrated circuit to realize data transfer of a digital signal passing system, a signal terminal for controlling the storage capacity, a signal terminal for outputting an analog audio signal, and the digital signal. The audio signal reproducing circuit is provided with a signal terminal for supporting an operation, a signal terminal for indicating a state of the digital audio signal reproducing circuit, and a signal terminal for supplying electric power to the one-chip integrated circuit. The one-chip integrated circuit of claim 38. 41. In the digital audio signal reproducing circuit, when writing information in the memory circuit, a step of self-diagnosing a defective portion of the memory circuit and skipping an address of the defective portion is included. 38. A digital audio reproduction circuit according to claim 39 or claim 40.