DE19803665A1 - Transistor for analog circuit functions - Google Patents

Description

The present invention relates to a transistor, in particular a PMOS transistor, for analog or mixed ana log / digital circuit functions.

To maintain or increase international competition ability to work it is necessary to reduce the costs to reali a certain electronic function are constantly lowering and thus productivity continues to increase. The guarantee for productivity increases CMOS techno has been in the past few years logic. The CMOS technology owes its outstanding position especially the small space requirement of the MOS transistors itself as well as the ability to use the MOS transistors in one integrated circuit with the highest packing density nen. Add to that the low power consumption and, with progressive reduction in structure, also a high one Switching speed.

As a rule, other technologies come, for example that Bipolar technology or EEPROM technology, only then used when the specific, by the CMOS techno logic not or only insufficiently covered properties the respective other technology are in demand. examples for those that are not or only insufficiently from CMOS technology covered properties are the non-volatile spoke tion, the ability to drive predetermined currents, highest Speed or very good analog properties.

However, CMOS technology has cost advantages over it the other technologies so large that it is the goal of many ent is to improve CMOS technology so that  it can cover an increasing number of properties. In particular, it is the goal of many developments, the analo to improve the properties of CMOS technology.

To improve the analog properties of CMOS technology On the one hand, it is necessary to set the parameters of the components elements according to the desired electronic function optimize. Second, it is necessary to have an adequate Stability of these parameters over the life of the Eauele to ensure. Unfortunately there are a number of Degra dation mechanisms that negatively affect the electrical Pa parameters of a MOS transistor.

The best studied degradation mechanism is the so-called "HE degradation" (ME = hot electron). When loading Driven by a MOS transistor occurs on the drain side channel edge a field strength peak, which the channel electrons to na can accelerate to their limit speed. Some these so-called "hot electrons" can have the potential overcome barrier at the gate oxide interface and into that Gate oxide. There these electrons can among other things Si-H bonds break and thus he interface states testify.

In the case of an n-channel MOS transistor, the "hot elec tron effects "especially in a degradation of the drain current. In the case of a p-channel MOS transistor, the "hot elec tron effects "especially in shortening the effective Channel length. As an effective countermeasure against these effects So-called "LDD doping" (LDD = "Lightly Doped Drain") of the source / drain areas applied. It has also been proposed to use small amounts of fluorine or Introduce chlorine into the gate oxide to reduce the HE degradation reduce (Yasushiro Nishioka et al. IEEE Electron Device Let ters, vol. 10, no. 4, 141 (1989); Chii-Wen Chen et al. Jpn J.  Appl. Phys., Vol. 35, 2590 (1996) or P. Singer, Semiconduc Tor International, April 1997, p. 38). The Minde achieved in this way However, HE degradation is usually not sufficient appropriate to justify the additional effort that a Einbrin fluorine or chlorine in the gate oxide. Accordingly, this method is not used in mass production used.

In addition to the degradation of the transistor parameters by "hot Electrons "play the degradation of the transistor parameters due to long-term investing a gate voltage at elevated temperatures ("Bias Tempera ture stress ", BTS) especially for analog or mixed analog / digital circuit functions play an important role.

With analog or mixed analog / digital circuit radio ion some of the MOS transistors are often in one ar operating point, which is very sensitive to changes the threshold voltage of the transistor reacts. This ar The operating point is characterized by a gate voltage, the is only slightly above the threshold voltage of the MOS transistor. Accordingly, even small fluctuations in the lead Set voltage of the MOS transistor to relatively large fluctuations conditions in the current flowing through the MOS transi at the operating point stor flows. Since typical applications in analog circuit functions a well-defined flow through the Such MOS transistor can need such swan kungen in the threshold voltage of the MOS transistor in the Re gel are not accepted.

Unfortunately, the degradation leads to the "bias temperature Stress "(ETS) just changes the operational tension with the mentioned negative effects on the analog Circuit functions. To solve the problem caused by the "Bias Tem perature stress "caused drift in analog circuits  solve, were previously purely circuitry Action taken. These circuitry measures are intended to prevent a Voltage is applied to the gate of a MOS transistor.

Complicate the circuitry measures mentioned however design the circuit and also cost additional Chip area, which is therefore not for other electronic scarf functions can be used. It is therefore the task of the present invention to provide a transistor that avoids the mentioned disadvantages of the prior art or diminishes. In particular, it is a task of the present the invention to provide a transistor in which the Problem caused by the "Bias Temperature Stress" Technically drifts in analog circuits without Additional circuitry measures solved or essential Lich can be reduced.

This object is achieved by the transistor according to claim 1 solved. Further advantageous embodiments, Ausgestaltun conditions and aspects of the present invention result from the subclaims of the description and the enclosed Drawings.

According to the invention, a transistor for analog circuit functions with at least one source area, at least one Drain area, one between the source area and the drain area arranged channel area, one above the channel area richly arranged gate dielectric and one above the gate dielectric gate electrode provided. Of the Transistor according to the invention is characterized in that the width of the channel area is greater than twice the mi nominal structure size of the for the manufacture of the transistor manufacturing process used and in the gateielek  trical foreign atoms from the group of halogens are.

Any integrated circuit manufacturing process is the smallest structure size that can be manufactured is usually denoted by F ("Feature Size"). Should with such a manufacturing process, technology for short called, MOS transistors are made, so these Transistors, designed so that the width of the Kanalbe reichs ("effective channel width") equal to the smallest adjustable structure size is. In this way one can ensure the highest possible integration of the MOS transistors most. Unfortunately, such MOS transistors have only inadequate analog properties, so that they are only for digital scarf tion functions can be used.

The transistor according to the invention, however, is designed that the width of the channel area is greater than twice that minimum structure size for the manufacture of the transi manufacturing process used. This has to Consequence that when the transistor ei ne results in a sufficiently flat output characteristic, d. H. with too increasing voltage between source and drain, the current remains almost constant between source and drain.

In addition, the transistor according to the invention is thereby characterized in that foreign atoms in the gate dielectric the group of halogens are provided. By bringing in of foreign atoms from the group of halogens into the gatedi the negative effect of "bias Temperature Stress "(ETS) significantly reduced Consequence that the threshold voltage of the Transi invention only slightly during the life of the transistor Is subject to fluctuations. Accordingly, in the Re  gel on additional circuitry measures to the sub pressing the "bias temperature stress" can be dispensed with.

The transistor according to the invention thus has a one characteristic curve optimized with regard to anolog properties whose sufficient stability this characteristic curve over the Life of the transistor.

Fluorine and / or chlorine are preferred in the gate dielectric intended.

Furthermore, it is preferred if the width of the channel area larger than three to six times the minimum structure size of the used for the production of the transistor Technology is.

It is also preferred if the source region and the Drain area in the vicinity of the channel area have lower conductivity.

According to another embodiment of the present invention is the number of foreign atoms in the gate dielectric chosen that the capacitance of the from the gate electrode, the Ga tedielectric and the channel region formed capacitor by at least 2%, preferably at least 5%, compared to the value is reduced without foreign atoms. The change in capacity however, should not exceed 20%.

It is further preferred if the foreign atoms are replaced by an Im plantation in the gate electrode and then a diffu sion are introduced into the gate dielectric.

The invention is based on the figures of the drawing shown in more detail. Show it:  

Fig. 1-3 is a schematic representation of a method for the production of the transistor arrangement according to the invention,

Fig. 4 is a schematic representation of a transistor according to the invention, and

Fig. 5 is a measurement curve to illustrate the improvement in ETS degradation obtained by the inventive transistor arrangement.

Figs. 1 to 3 show a schematic representation of egg nes method for producing the inventive Transistor storanordnung, an n-type silicon substrate 1. Fig. 1 shows a section of a silicon wafer with and arranged above the silicon substrate 1 oxide layer 2 , which forms the Ga tedielectric of the later p-channel MOS transistor. Over the oxide layer 2 , a polysilicon layer 3 is brought up, which forms the gate electrode of the later p-channel MOS transistor. The state shown in FIG. 1 of a silicon wafer corresponds, for example, to the state that a silicon wafer assumes in a standard CMOS process after the wells of the CMOS transistors and the insulation (not shown) of the individual transistors have already been produced.

Fluorine atoms are then introduced into the polysilicon layer 3 by an implantation. The implantation takes place, for example, at an energy of 40 keV and a dose of 5 10 ¹⁵ to 1 10 ¹⁶ cm ^-2 . The resulting situation is shown in Fig. 2.

A phosphor glass layer 4 (PSG = Phosphorous Silicate Glass) is produced on the polysilicon layer 3 . Due to the temperature treatment required when producing the phosphor glass layer 4 or through a specially carried out temperature treatment, the polysilicon layer is doped with phosphorus atoms and the fluorine diffuses into the oxide layer 2 . The resulting situation is shown in Fig. 3.

Due to the diffusion of the fluorine into the oxide layer 2 , the capacitance of the capacitor formed from the polysilicon layer 3 , the oxide layer 2 and the Ka substrate 1 is reduced by 6% compared to the value without fluorine.

The process of making the p-channel MOS transistor can then continue according to a standard CMOS process, to create the full p-channel MOS transistor. The These steps are known per se, so do not continue on them must be received.

Fig. 4 shows a schematic representation of a transistor according to the Invention. The p⁺-doped source region 5 and the p⁺-doped drain region 6 are produced in the n-doped silicon substrate 1 by implantation. Both the source area 5 and the drain area 6 each have an area 5 a, 6 a of lower conductivity (LDD = "lightly doped drain"). Between the source region 5 and the drain region 6 , the channel region 7 is arranged below the gate dielectric 2 . The width of the channel area 7 between the areas 5 a; 6 a lower conductivity is five times the minimum structure size of the manufacturing method used for manufacturing the transistor.

Spacers 8 are arranged on the side of the gate electrode 3 and are used to produce the regions 5 a, 6 a.

Fig. 5 shows a measurement curve to illustrate the improvement obtained by the transistor according to the invention with regard to ETS degradation. A gate voltage of -8.5 V was applied to the PMOS transistor shown in FIG. 4 at a temperature of 210 ° C. for 1000 seconds. The measurement curve shows the degradation of the drain current (Y axis in percent) at different gate voltages (X axis in volts). The square symbols represent measured values of a transistor which has identical dimensions as a transistor according to the invention, but without the introduction of fluorine atoms into the gate dielectric. The round symbols represent measured values of a transistor according to the invention, in which fluorine atoms are provided in the gate dielectric.

The improvement in the degradation behavior is from the measurement curve at least clearly visible, especially with small gate voltages bar.

Claims (6)

1. transistor for analog circuit functions with at least one source region (5), at least a drain region (6), arranged between the source region (5) and the drain region (6) channel region (7), arranged over the channel region (7) gate dielectric ( 2 ) and a gate electrode ( 3 ) arranged above the gate dielectric ( 2 ), characterized in that the width of the channel region ( 7 ) is greater than twice the minimum structure size of the production method used for the production of the transistor and in the gate dielectric ( 2 ) Foreign atoms from the group of halogens are seen before. 2. Transistor according to claim 1, characterized in that fluorine and / or chlorine are provided in the gate dielectric ( 2 ). 3. Transistor according to claim 1 or 2, characterized in that the width of the channel region ( 7 ) is larger than three to six times the minimum structure size of the technology used for the production of the transistor. 4. Transistor according to one of the preceding claims, characterized in that the source region ( 5 ) and the drain region ( 6 ) each in the vicinity of the channel region ( 7 ) have an area ( 5 a, 6 a) of lower conductivity. 5. Transistor according to one of the preceding claims, characterized in that the number of foreign atoms in the gate dielectric ( 2 ) is selected such that the capacitance of the gate electrode ( 3 ), the gate dielectric ( 2 ) and the channel region ( 7 ) formed capacitor by at least 2%, preferably at least 5%, compared to the value without foreign atoms is reduced. 6. Transistor according to one of the preceding claims, characterized in that the foreign atoms are brought by an implantation in the gate electrode ( 3 ) and a subsequent diffusion in the gate dielectric ( 2 ).