DE19749378B4 - MOS transistor and method for its production - Google Patents

Abstract

MOS transistor,
With source, a gate electrode, drain and a channel,
Wherein the source and the drain are formed by doped regions of a semiconductor material,
Wherein the semiconductor material is located on a substrate which contains a planar disk of a single crystal at least in the region of a main surface,
- wherein below the source and / or the drain, a layer stack of a plurality of superimposed layers (70, 80) of insulating materials is arranged, wherein the layer stack of several superimposed layers (70, 80) extends to the channel and at most below one Part of the area between the source and the drain is arranged, and
- Wherein the top layer (80) of the layer stack of a plurality of superimposed layers (70, 80) nitrogen or a nitrogen compound.

Description

The The invention relates to a MOS transistor, with source, a gate electrode, Drain and a channel, wherein the source and the drain through doped regions a semiconductor material are formed, and wherein the semiconductor material is located on a substrate which at least in the region of a main surface of a flat disc of a single crystal contains, as well as a method to its production.

One Such MOS transistor can be used, for example, in a CMOS logic circuit be used as an n-channel transistor or as a p-channel transistor. It exists a high demand, the switching speed of such a transistor to increase and to reduce the power turnover. Since it is known that a large capacity between the active region of the MOS transistor and the substrate to a low switching speed and high power consumption of the Transistor leads, will the capacity between the active region of the transistor and the substrate as possible kept small.

to Achieving a high switching speed is known (J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Boston / Dordrecht / London, 1991, pp. 107-117), a MOS transistor based on an SOI (SILICON ON INSULATOR) substrate build. The use of such an SOI substrate is two Benefits connected. The lateral and vertical isolation through The isolator prevents the so-called latch-up effect. In which Latch-up effect is the occurrence of an ignition current the polarity of an emitter-base pn junction in the direction of flow. The high ignition current can cause local destruction lead the integrated circuit, for example, by melting the metallization. By avoiding the latch-up effect, it is possible to n-channel and p-channel MOS transistors so close together as the resolution of the lithographic process allowed. Another advantage of using SOI substrates is in that it almost no parasitic pn capacity There are, which must be reloaded at the occurring switching operations. One such on a SOI substrate constructed MOS transistor draws thus characterized by a high switching speed.

This Structure of the transistor, however, has several disadvantages. On the one hand, there is a heating of the transistor during operation, on the other hand, the SOI material due to its manufacturing process, a higher defect density in the upper one Silicon layer on as a massive silicon substrate. hereby it can cause failures and thus come to yield problems in mass production.

It is also known, a method for producing a MOS transistor perform so that the isolation areas generated at a distance of at least 0.3 microns from the gate electrode become. The source and drain grow epitaxially, wherein a connection between the source and the drain with the channel (K. Imai et al Symposium on VLSI Technology Digest of Technical Papers, IEEE 1996, pp. 172-173). It is also located below the channel a δ-doped layer. Under δ-doping It is understood here that it is around a thin, highly doped layer is. Such a layer points in lateral Direction a good conductivity on. In the vertical direction, the interfaces between the δ-doped However, layer and the semiconductor regions adjacent to it one Isolation property on. This occurs in the vertical direction a similar electrical insulation as in an SOI substrate. The δ-doped layer improves additionally the short-channel characteristics of the transistor. The short channel properties of the transistor result from the fact that the thickness of the charge carrier or Depletion area in the order of magnitude the channel length lies. A particularly disturbing short channel characteristic in practice is the emergence of shorts. The use of a arranged below the channel δ-doped However, layer is associated with the disadvantage that the capacity between is suppressed only slightly in the active region of the transistor and the substrate. In addition, act Fluctuations in the process parameters in which the generation the isolation areas used lithography process directly on the capacity out. The switching characteristics of different transistors of the same Type thereby have an undesirable high fluctuation range.

US 4,523,213 describes a MOS semiconductor device in which a region of silicon oxide or silicon nitride buried in a substrate extends partially below the channel region of a MOS transistor. A field oxide is formed on the silicon substrate and encloses the source, drain and channel regions. For forming the buried layer, oxygen ions are implanted in the substrate, and thereafter, an annealing step is performed so that a buried silicon oxide region is formed. The buried silicon oxide region may extend only below the source or drain region.

US 5,043,778 describes a MOS device in which the source / drain regions are almost completely isolated by a dielectric. For this purpose, first a field oxide and a dummy gate gebil et et wells etched between the Dummmygate and the field oxide. Thereafter, the wells are covered with a dielectric and then filled by deposition of silicon oxide. Alternatively, the wells can be completely filled by a grown dielectric. The recesses are filled in by conformal deposition of amorphous silicon, polysilicon or metal and then etched back so that the surfaces of the source / drain contact regions are coplanar with the gate oxide. Then, the dielectric on the source / drain contact regions is removed by etching, whereby grooves are formed at the edge of the source / drain contact regions. Thereafter, the grooves are filled by deposition of a thin polysilicon layer. The nitride spacers are removed and oxide spacers are formed. Thereafter, source / drain regions are formed by implanting dopants and a subsequent annealing step.

US 5,620,912 A relates to a semiconductor device and a method of manufacturing the same. According to US 5,620,912 A In a substrate, a field oxide for defining an active region, a gate stack is formed with spacers. In a further step, the substrate is selectively isotropically etched relative to the spacers and field oxide, thereby forming trenches. Then a nitride layer is applied to the entire substrate and then anisotropically etched so that the nitride layer remains only in the trenches below the spacers. In a subsequent oxidation step, an oxide layer is formed in the trenches, wherein the nitride layer below the spacers prevents oxidation of these portions of the trenches. Then, the remaining nitride layer is removed, and a polysilicon film is formed on the entire surface of the substrate. Subsequently, the polysilicon film is etched back so that the polysilicon film remains only in the trenches. Then, the polysilicon film is doped and a heat treatment is performed.

Of the Invention is based on the object, an improved MOS transistor, the one possible has high switching speed and its power conversion as possible is low and specify a method for its production. Especially should a heating of the MOS transistor as much as possible avoided become. Furthermore, a possible low and at the same time precisely definable electrical capacity between the active region of the transistor and the substrate can be achieved.

According to the invention this Task by a MOS transistor according to the features of the claim 1 solved.

The The invention thus provides to provide a MOS transistor, at the areas below the source and / or drain are different are designed as the area located below the channel.

The Reaching the insulating layer to the channel includes both the case that is below the channel no insulating layer is located as well the case that is a portion of the insulating layer below a portion of the channel extends.

Of the Part of the layer extending below the channel is preferably less than the half the area of the canal. This allows a good heat dissipation from the active region of the transistor. This will cause a heating of the transistor during of the operation avoided, so that it not to an undesirable Lowering the drain current comes.

Conveniently, is the area extent limited to the layer. This limit can be different in different ways respectively. For example, it is possible for a continuous layer is interrupted, or that one or several areal limited Layers each under certain areas, for example, respectively are arranged below the source or the drain. Preferably stretches the layer is in its outer area up to an isolation structure that is the transistor over others Circuit elements such as adjacent transistors isolated.

Basically the layer consist of any insulating material. Preferably, however, the dielectric constant of the layer is preferably low.

A particularly advantageous embodiment of the invention is characterized in that the layer contains nitrogen or a nitrogen compound. This has the advantage that on the layer the regions for the source and the drain can grow up by selective epitaxy. Examples of nitrogen-containing layers include nitrides such as Si ₃ N ₄ , nitrided oxides or oxides grown or post-treated in NO, N ₂ O. Depending on the manufacturing process, the nitrogen atoms are deposited at both interfaces (ie polycrystalline silicon / oxide and silicon substrate / oxide), or are at least preferably enriched near a boundary surface to form a silicon layer.

It is particularly convenient that the layer containing nitrogen or a nitrogen compound forms the topmost layer of several superimposed layers. Such a Schich The advantage is that the regions for the source and the drain can grow up well with a low effective dielectric constant. As a material for one or more of the other layers are in particular oxides such as SiO ₂ into consideration. While a nitride layer has a relative dielectric constant of 7.5, the relative dielectric constant of an SiO ₂ layer prepared by the TEOS method is only 4.

It is also advantageous that the insulating layer has a thickness of at least 20 nm, preferably at least 50 nm. A minimum thickness of the insulating layer of about 50 nm has the advantage that the capacity between the source / drain regions and the substrate by more than the half decreases.

A expedient embodiment draws the MOS transistor according to the invention characterized by the fact that he contains two layers of an insulating material, wherein one below the source and the other below the drain is arranged.

at the presence of several layers, it is expedient that the layers at the same height are arranged. This is manufacturing technology particularly simple to realize and at the same time has the advantage that the value the remaining capacity remaining can be determined very precisely.

at the transistors according to the invention can These are both p-channel transistors and n-channel transistors to do something. It is thus possible all Transistors of a CMOS circuit in the inventive manner to design. For an intended different circuit behavior the individual transistors is sufficient it only that one or a few of the transistors in the manner according to the invention are designed.

The The invention further relates to a method for producing a MOS transistor, wherein on a substrate, a semiconductor material is deposited, and wherein doped regions in the semiconductor material for source and drain are formed. This method is carried out according to the invention so that below the source and / or the drain at least one layer of a insulating material is applied, the layer being applied she will reaches to the canal.

Preferably becomes the production of the MOS transistor in the substrate a Insulation structure formed, which is an active area for the MOS transistor surrounds. Within the isolation structure becomes a gate electrode formed, which provided on flanks with insulating spacers (spacers) become. By selective etching will be afterwards trenches educated. The etching occurs selectively to the isolation structure and to the insulating spacers. Thereby the trenches last from the insulation structure to that provided with the insulating spacers Gate electrode. The layer of insulating material is then in the trenches educated. This is the height of the layer so that they less than the depth of the trenches is. As a result, at least below the gate electrode in the trenches an edge of the semiconductor material of the substrate free. Subsequently, will above the layer of insulating material by selective Epitaxial semiconductor material deposited. By the selective epitaxy that grows Semiconductor material from the exposed in the trench edge of the Substrate monocrystalline. Above the layer of insulating Materi al grows it is polycrystalline. In that in the trenches of through selective epitaxy deposited semiconductor material, source / drain regions are formed. The source / drain regions be by in situ doping in selective epitaxy or doped by subsequent implantation. This procedure offers the advantage that the trenches self-aligned to the gate electrode and the isolation structure are formed and that deposited semiconductor material in which the source / drain regions be formed, self-aligned to the location of the trenches are formed. The layer of the insulating material that is formed in the trenches, and that deposited semiconductor material in the trenches have the same width. That the layer of insulating material that reduces the parasitic junction-substrate capacitance is in terms of their width optimized in a self-aligned manner.

Further Advantages, expedient further education and features of the invention will become apparent from the dependent claims and the following description of a preferred embodiment with reference the drawings.

From the drawings shows

1 a cross section through the substrate 5 during the tub and canal implantation,

2 this in 1 shown substrate after the growth of the gate oxide and polycrystalline silicon,

3 a cross section through the substrate after deposition of a nitride layer,

4 a cross section through the substrate after the structuring of the gate electrode,

5 a cross section through the substrate after deposition of a spacer on the gate electrode,

6 a cross section through the substrate after the etching of isolation trenches,

7 a cross section through the substrate after filling the trenches,

8th a cross section through the substrate during the implementation of a planarization process,

9 a cross section through the substrate after removal of the nitride layer on the gate electrode

10 a cross section through the substrate after removal of oxide residues on the flanks of the spacer and

11 a cross section through the substrate after growth of a silicon layer.

A particularly preferred embodiment of the invention begins with a conventional isolation of the active regions by the creation of an isolation structure 10 For example, with a LOCOS or STI (shallow trench isolation) process.

following the process goes on the base of an insulation structure produced by the STI process was explained. It could but technologically also a LOCOS or Recessed LOCOS isolation be used.

Thereafter, well and channel regions are formed by ion implantation with boron in the case of an NMOS transistor or with phosphor in the case of a PMOS transistor (see 1 ). Subsequently, a gate dielectric 20 which preferably contains an oxide grown. Subsequently, a gate stack is deposited, for example by deposition of a polycrystalline silicon layer 25 and a nitride layer 28 (please refer 2 and 3 ).

In the next process step is by structuring the polycrystalline silicon layer 25 and the nitride layer 28 a gate electrode 30 formed (see 4 ) and optionally dopant implanted in a slightly increasing concentration (LDD implantation). Such a flat concentration gradient prolongs the life of the transistor.

This is followed by the formation of spacers 40 , preferably by the deposition of SiO ₂ by decomposition of tetra-ethyl-ortho-silicate (SiO (OC ₂ H ₅ ) ₄ ; TEOS), and subsequent anisotropic etching, which is referred to as TEOS spacer formation (see 5 ).

The following are with a resist mask 50 Diffusion areas for well contacts that are outside the isolation structure 10 are located, covered and silicon plasma etched (see 6 ). The plasma etching is selective to the isolation structure 10 , the spacers 40 and the nitride layer 28 , As etchant HBr, chlorine and helium is suitable. The etching takes place at 100 to 500 mTorr and 10 to 50 ° C. Self-aligned, about 300 nm deep trenches are created 60 that of the with the spacers 40 provided gate electrode 30 up to the insulation structure 10 pass. Subsequently, a thin oxide layer 70 formed, which can be done for example by deposition by the TEOS process or by thermal oxidation. This is followed by the deposition of a nitride layer 80 that is so thick that they are the trenches 60 fills and the gate electrode 30 covered (see 7 ). Preferably, the nitride layer 80 about 600 nm thick. The nitride layer 80 allows growth of silicon selectively to an oxide layer.

With the help of a CMP (chemical-mechanical polishing) step, unevenness in the surface of the nitride layer 80 removed and the nitride layer 80 to a target thickness of about 100 nm to 200 nm on the gate electrode 30 brought (see 8th ). The CMP step is stopped before there is a removal on the upper surface of the gate electrode 30 located thin oxide layer, the so-called thin oxide nitride lid, can come.

During subsequent wet-chemical thinning of the nitride layer, the thin-oxide nitride cap also becomes on the gate electrode 30 removed so that the surface of the gate electrode 30 is exposed (see 9 ). Here, a target thickness of the nitride layer becomes 80 achieved, which is less than the height extent of the insulating trenches 60 is. The target thickness of the nitride layer 80 is about 100 nm to 200 nm, with 150 nm being preferred. A short etching step removes oxide residues on the flank to the spacer (spacer) 40 and any nitride residues on the gate electrode 30 (please refer 10 ).

There now follows an epitaxy step in which a semiconductor material 90 , preferably silicon (depending on the application in situ doped or undoped), selectively grows only on nitride and silicon, but not on the oxide. The selective epitaxy is carried out with a H ₂ , SiH ₂ Cl ₂ and HCl-containing process gas to which doping gases are added in the case of in-situ doping, in the temperature range between 750 and 950 ° C and in the pressure range between 1 and 100 Torr. The growth takes place monocrystalline on silicon and polycrystalline on nitride. A semiconductor layer, preferably a polysilicon layer, is formed on the nitride layer with monocrystalline connection to the channel region below the gate electrode 30 , At the same time, the semiconductor material is growing 90 on the gate electrode 30 (please refer 11 ).

If the growth of the semiconductor material is performed in situ, this forms laterally of the gate electrode 30 grown semiconductor material source / drain regions 91 , Is the growth of the semiconductor material 90 undoped, so are source / drain regions 91 by implantation with phosphorus in the case of an NMOS transistor or with boron in the case of a PMOS transistor and subsequent annealing.

in the Connection to the illustrated process steps the transistor will go through the usual Process steps such as applying a passivation layer, contact hole opening and Contact formation completed (not shown).

By the proposed method is located under all source / drain regions an insulating layer that dramatically reduces the parasitic junction-substrate capacitance reduced.

Claims (8)

MOS transistor, - with source, a gate electrode, drain and a channel, - wherein the source and the drain are formed by doped regions of a semiconductor material, - wherein the semiconductor material is located on a substrate which at least in the region of a major surface of a flat disc from a single crystal, wherein below the source and / or the drain a layer stack of several superimposed layers ( 70 . 80 ) is arranged from insulating materials, wherein the layer stack of several superimposed layers ( 70 . 80 ) extends to the channel and is arranged at most below a part of the area between the source and the drain, and - wherein the uppermost layer ( 80 ) of the layer stack of several superimposed layers ( 70 . 80 ) Contains nitrogen or a nitrogen compound. MOS transistor according to claim 1, characterized in that the layer stack consists of several superimposed layers ( 70 . 80 ) has a thickness of at least 20 nm. MOS transistor according to one of claims 1 to 2, characterized in that it comprises two of the layer stacks of a plurality of superimposed layers ( 70 . 80 ), wherein one layer stack is arranged below the source and the other layer stack below the drain. MOS transistor according to Claim 3, characterized that the layer stacks are arranged at the same height. Method for producing a MOS transistor comprising: forming an insulation structure ( 10 ) in a substrate ( 5 ), the insulation structure ( 10 ) surrounds an active region for the MOS transistor, - depositing a polycrystalline silicon layer ( 25 ) and a nitride layer ( 28 ) - structuring the polycrystalline silicon layer ( 25 ) and the nitride layer ( 28 ) and thereby forming a gate electrode ( 30 ), - forming insulating spacers ( 40 ) on flanks of the gate electrode ( 30 ), - formation of trenches ( 60 ) in the substrate, that of the with the spacers ( 40 ) provided gate electrode ( 30 ) to the isolation structure ( 10 ) by selectively etching silicon with respect to the isolation structure ( 10 ), the spacers ( 40 ) and the nitride layer ( 28 ), - forming an oxide layer ( 70 ), - deposition of a nitride layer ( 80 ), wherein the nitride layer ( 80 ) the trenches ( 60 ) and the gate electrode ( 30 ), - leveling the nitride layer ( 80 ) by chemical mechanical polishing, - thinning of the nitride layer ( 80 ) while exposing a surface of the gate electrode ( 30 ), - selective growth of a semiconductor material ( 90 ) on nitride and on silicon, thereby forming a semiconductor layer on the nitride layer and on the gate electrode ( 30 ). Method according to Claim 5, in which the selective growth of the semiconductor material ( 90 ) With a H ₂ , SiH ₂ Cl ₂ and HCL-containing process gas. Method according to Claim 6, in which the selective growth of the semiconductor material ( 90 ) takes place in a temperature range between 750 and 950 ° C. Method according to one of claims 6 or 7, in which the selective growth of the semiconductor material ( 90 ) takes place in a pressure range between 1 and 100 Torr.