DE19725091B4 - Lateral transistor device and method for its production - Google Patents

Abstract

Lateral transistor component with at least one insulated gate electrode (13), with lateral and vertical current flow, in a p-substrate (3), on the front of which an n-region (4) is arranged, in which a heavily p-doped anode region (5 ) is embedded, the vertical current flowing via a rear-side contact (7), characterized in that the rear-side contact is electrically connected to the p-substrate via a heavily p-doped region designed as a diffusion region (8).

Description

The invention is based on one lateral transistor component or a method for its production according to the genre of independent claims. It is already a lateral bipolar transistor with an insulated gate trained transistor device known that has lateral and vertical current flow (D.N. Pattanayak et al, IEEE Trans. ED-33, pp. 1956 to 1963, 1986). The transistor component there is an n-channel LIGBT (LIGBT = Lateral Isolated gate bipolar transistor) formed on epitaxial silicon, that grew on a low or high doped p-substrate is. The back can the component over a back contact be connected. It is also known to realize high Locking capabilities in well-known LIGBT's apply the resurf principle (Resurf = Reduced Surface Field), too using an epitaxial layer (J.A. Appels et al, IEDM Tech. Dig. Pp. 238 to 291, 1979).

From the EP 0 630 054 A1 a vertically arranged thyristor is known, all of the p-wells introduced on the front side of the semiconductor component are connected to a common emitter connection.

The transistor component or Method with having the characterizing features of the claims In contrast, the advantage of a high current carrying capacity and good transmission behavior or the advantage of simple manufacture of a component higher

Current carrying capacity. There is only a few volts of voltage drop in the static switched-on state with a current density in the order of 100 amperes / cm ² component area. By connecting the rear side contact via a p- / p + transition formed by diffusion in a p ^- substrate, a good rear side connection is achieved. For a given blocking capacity, a large number of charge carriers are provided for good transmission behavior, the charge carriers present in a p ^- substrate region with rear-side diffusion having an increased lifespan in comparison to charge carriers which are in an epitaxially formed p ^{- region} at p ⁺ - move the substrate. This results in a further increased current carrying capacity. Increasing the current carrying capacity by increasing the vertical current component in the component would also be possible through a reduced thickness of the p ^- epitaxial layer with an epitaxially formed P- / P + transition. However, this would lead to a reduced blocking ability of the component, both in the static and in particular in the dynamic shutdown case. In the case of a backside diffusion, the diffusion profile runs far less abruptly into the depth of the wafer than in the case of an epitaxial layer. This enables a high current carrying capacity with simultaneous blocking capability in both static and dynamic shutdown cases. A multichannel principle contributes to a small effective total channel resistance in both LJGBT and MOS transistors by means of parallel-connected channel regions and thus to an increase in the current carrying capacity or to a good transmission behavior. Another advantage is increased latch-up strength, which is ensured as a result of the rear diffusion at the same time as the increased current carrying capacity. The area formed as a diffusion region, via which the component is connected to the rear-side contact, reduces the necessary horizontal current component of the component, thereby preventing the lateral parasitic thyristor from igniting; at the same time, the component as a whole has an improved current carrying capacity.

As a result of the reduction of the necessary horizontal current component and thus increased latch-up strength optionally the total area of the component can be reduced somewhat, which is advantageous and proves to be space-saving.

With a LJGBT, the multi-channel principle also has a positive effect on the latch-up strength. A smaller current flows through a multiplicity of channel regions connected in parallel per parasitic thyristor, which also reduces the risk of ignition of this parasitic thyristor. Contacting the rear side over a region designed as a diffusion region furthermore guarantees high impulse resistance, ie the component can cope with the simultaneous occurrence of high voltages and high current densities. In contrast to the formation of the p ^- / p ⁺ transition by means of epitaxy, the design as a diffusion region creates smaller doping gradients. This ensures a high level of pulse resistance, especially in the event of a dynamic shutdown. As a result of the smaller doping gradient, the vertical current flow in the component and the blocking capability are less sensitive to a variation in the thickness of the substrate. This enables a simpler manufacture of the component.

Through the measures listed in the dependent claims are advantageous developments and improvements in the independent claims specified devices or methods possible.

The formation of an n-region arranged on the front side of the component as a resurf region advantageously leads to an increased breakdown voltage, that is to say an increased dielectric strength of the component as a result of a favorable profile achieved due to the thinness of the resurf layer in conjunction with its doping concentration the field strength in the space charge zone. Should not breakdown voltage can be selected, a smaller lateral extension can be chosen, in order to ensure, for example, in a multi-channel arrangement or simply by connecting several components in parallel on the same given chip area, an increased current carrying capacity or increased latch-up strength. If, instead of a smaller lateral extension, the option of ensuring a higher breakdown voltage is selected, breakdown voltages of a few 100 V in the statically switched-off state, ie if there is no voltage at the gate electrode, are possible with the resurf area. If the resurfing area is produced by means of a diffusion process instead of by epitaxial deposition, then, analogously to the rear side diffusion, there is an increased service life of the charge carriers, which in turn has a positive effect on the transmission behavior of the component.

The provision of a buffer layer around the anode area to avoid a punch-through effect. Assigns the anode area a big one Doping concentration and thickness and consequently the buffer layer a greater depth of penetration than the n-area, then, with continued avoidance of a Punch-through effect a good rear connection, that is good state behavior, allows.

The provision of heavily endowed Impregnation zones over the the cathode or source connections with the semiconductor substrate communicate, lead too low contact resistance at the connections.

drawing

Embodiments of the invention are shown in the drawing and explained in more detail in the following description. Show it 1 a first embodiment,

2 a second embodiment, 3 a third embodiment, 4 a fourth embodiment, 5 2 shows a plan view of a transistor component according to the invention, 6 a first detailed view of the top view, 7 a second detailed view of the top view and 8th a third detailed view of the plan view of a transistor device according to the invention.

1 shows a transistor device designed as a LIGBT with a rear contact 7 , On a side of the p-substrate called the front 3 is an n-region 4 introduced, in turn, a p-tub 11 is embedded. The 1 shows a cross section through the component, as well as the following 2 to 4 , The areas in the semiconductor component that are now mentioned and will be described further below are to be continued so that the top views as shown in FIG 5 to 8th are shown. In the p-tub 11 again is an n-tub 12 embedded through a cathode connector 16 with mass 14 connected is. So is the p-tub 11 over a heavily p-doped doping zone 19 with the cathode connection 16 connected. From the p-tub 11 through part of the n-area 4 is spatially separated in the n-area 4 a heavily p-doped anode region 5 brought in. This anode area 5 is from the n-area 4 by one towards the n-area 4 shielded more n-doped buffer layer. This shielding also takes place against the p-type substrate below 3 , The anode area 5 is via the anode connection 17 electrically contactable. cathode terminal 16 like anode connection 17 are with a cathode field plate 15 or an anode field plate 18 provided for field shielding. One as the inversion channel area 41 Switchable area of the p-tub 11 between n-tub 12 and n area 4 is over a gate electrode 13 controllable by an insulation layer 1 is isolated from the semiconductor substrate. Anode and cathode field plates are from the gate electrode through another insulation layer 2 isolated. Another layer of insulation 92 , for example made of silicon nitride, covers the entire component as a passivation layer and is only opened via bond pads via which the component can be controlled. In the embodiment of the 1 is the depth of penetration 10 the buffer layer 6 chosen greater than the penetration depth 9 of the n-area 4 , The rear side contact arranged on the side of the semiconductor substrate referred to as the rear side 7 is also like the cathode connection 16 with mass 14 connected. The electrical contact to the semiconductor substrate 3 takes place over a heavily p-doped region designed as a diffusion region 8th , The in the 1 with reference numerals 21 and 22 Lines provided indicate a first or second line of symmetry, with respect to which the section shown 20 can be continued several times in mirror image. The entire outer edge of the component lies on ground and contains a deep p ⁺ diffusion to shield the component from the outside, which extends into the p ^- substrate (not shown in the drawing).

If the LIGBT transistor shown shows a positive potential at the gate electrode 13 are created in part of the p-tub 11 Electrons to the surface below the insulation layer 1 drawn so that a 2nversionchannel 41 is trained. With a potential at the anode contact that is positive compared to the reference potential (ground) 17 electrons flow from the n-well 12 through the inversion channel and the n-area to the anode area 5 , from which holes in the n-area 4 be injected. This will make the n-area 4 conductivity modulated. In addition to the described lateral current flow, there is a vertical current flow between the anode area 5 and back contact 7 one, as a result of that from the anode area 5 injected holes especially in the dynamic shutdown case, i.e. when one in ductive load is present between the cathode and anode, is carried almost exclusively by holes. In the stationary switched-on state of the transistor component, approximately one third of the total current flows through the rear contact 7 , In the event of a switch-off, particularly with an inductive load, approx. 80% flow through the through the anode area 5 , the n-doped buffer layer 6 and the p-substrate 3 with adjacent p-doped area 8th layer sequence functioning as a PNP transistor. In addition to the above-mentioned lateral current path, the vertical current path described last should also have the greatest possible current carrying capacity, that is to say good transmission behavior. In particular, a good current carrying capacity of the vertical current path is advantageous if the lateral current at the part can thereby be reduced, which can otherwise lead to a latchup at high currents. This latchup can be explained by an unwanted firing of a parasitic thyristor, which is formed from the laterally successive areas 12 . 11 . 4 respectively. 6 and 5 , n-well 12 and p-tub 11 are via the cathode connection 16 shorted. However, flow from the anode area 5 injected holes below the one tub 12 through the p-tub 11 and reach the cathode connection 16 , then there is a lateral voltage drop, which is used to control the n-well 12 and p-tub 11 leads formed lateral diode, so that the parasitic thyristor already mentioned is ignited and the current flow can no longer be easily controlled by the gate electrode. In contrast to the prior art, the heavily p-doped area is now 8th as a diffusion region in the weakly doped p-substrate 3 formed and not a highly doped p-substrate on which a lightly doped p-doped layer is generated epitaxially. This leads to a diffusion profile, that is to say a concentration distribution of the p-type dopant atoms, which, far less abruptly runs from the rear into the depth of the wafer, than a substrate diffusion into an epitaxial layer. Due to the smaller concentration gradient at the p ^- / p ⁺ transition, the local field strengths are also lower, which, in the case of a high vertical current carried mainly by holes in the dynamic shutdown case, leads to the prevention of dynamic avalanche and thus to a higher pulse stability. However, a high level of doping alone, which would also be achievable via an epitaxial process, is not expedient, since a strong concentration gradient leads to high power loss. The vertical PNP transistor in the LIGBT structure, on the other hand, is electrically well connected to the back as a result of a p ⁺ back diffusion and easily carries about a third of the total current in the static case, and even 80% in the dynamic shutdown case. The use of backside diffusion has the following advantages over epitaxy on a highly doped substrate: The pulse strength of the LIGBT is higher because the diffusion profile runs less abruptly into the depth of the wafer: A dynamic avalanche breakdown at high voltage and high current is better, especially in the event of a shutdown to suppress. Furthermore, the forward behavior, that is the voltage drop between the anode and the rear contact, reacts 7 in the switched-on state at a given current density, less sensitive to a fluctuation in the thickness of the p-substrate because of the gentle leakage of the rear diffusion. Furthermore, in comparison to an epitaxial zone in a substrate region with the same doping concentration, the lifetime of the charge carriers is longer. It is generally so high that the transmission behavior is not dominated by the carrier life. For this reason, the resurfing area, which is described in the following, should not be created epitaxially, if possible, but with a diffusion process.

The n area 4 is designed as a surfing area in the exemplary embodiment. The condition for such a layer is specified in the article on resurfing applications cited at the beginning. The integral of the doping concentration over the layer thickness must be approximately 10 ¹² cm ⁻² . This choice of parameters ensures that between the cathode connection 16 and anode connection 17 larger voltages can be applied (if the gate electrode is not positively driven); without an unwanted breakthrough; the field strength near the surface of the component at the PN junction between the p-well 11 and n area 4 is particularly critical if the dose of the dopant in the RESURF zone is too high, since near the surface the PN junction has a curvature at which the electric field of the space charge zone is excessive due to the geometry. Otherwise, if the dopant dose in the RESURF area is too low, a critical field increase occurs at the n-doped buffer 6 ,

If a positive voltage is applied to the anode connection, then there is the transition between the p-well 11 and the n-area 4 polarized in the reverse direction. Likewise, the transition between the substrate 3 and the n-area 4 , When the gate electrode is not driven positively and positive voltage is applied to the anode connection 17 there is now a certain field strength at the transition between the p-well 11 and the anode area 5 due to carrier depletion around this transition. This field strength at the transition is now determined by the immediately adjacent interface between the n-area 4 and substrate 3 affected. This adjoining horizontal PN junction, which is also polarized in the reverse direction, works in conjunction with the lateral pn junction between the p-well 11 and the RESURF area 4 an enlargement of the space charge zone, which for a given anode voltage is not only close to the PN junction between the n-region 4 and p-tub 11 extends, but very quickly with increasing anode voltage whole n-area 4 Fulfills. This results in the connection between the cathode and the anode in the n-region 4 a more uniform field strength curve, which causes the PN junction between the p-well 11 and n area 4 even a smaller field strength prevails compared to the case when the n-area 4 is not designed as a resurf area, ie in the case when the horizontal PN transition between n area 4 and substrate 3 would lie deep in the substrate and would have a dopant concentration that deviates from the optimal dose. It can be explained that with the in 1 shown transistor component with a thin resurf layer N-region 4 higher voltages at the anode connection 17 can be created until it is at the PN transition between p-tub 11 and n area 4 an unwanted breakthrough occurs. If a certain dielectric strength is already sufficient, the distance between the first line of symmetry can optionally be used 21 and second line of symmetry 22 can be reduced in order to achieve a reduction in size of the component as an alternative to increasing a dielectric strength.

The application of the resurf principle would be the absence of the buffer layer 6 due to the complete depletion of the resurf zone 4 of charge carriers to break down the diffusion barrier between the p-anode region 5 and the resurf area 4 as a result of a punch through. To avoid this, in the exemplary embodiment is between the anode area 5 and the n-area 4 a buffer layer 6 arranged that the anode area 5 from the n-area 4 shields in that the buffer layer 6 is more n-doped than the n-region 4 , This prevents the space charge zone from reaching through from the resurf area to the anode, so that a punch-through breakdown can be avoided. The doping concentration of the buffer layer 6 is higher than that of the n-area 4 , but must not be chosen too high, so that in the case of passage, that of the anode area 5 in the n-area 4 and p-substrate 3 hole injection taking place is not obstructed too much, which would be disadvantageous for the passage behavior of the component. The anode area 5 should protrude as deep as possible into the component in the vertical direction for good transmission behavior of the component and have a large p-dopant dose. This explains that in the embodiment of the 1 the depth of penetration 10 the buffer layer is greater than the depth of penetration 9 of the n area 4 , On the other hand, the anode area 5 not be inserted too deeply, since otherwise the locking ability of the component would be lost in the vertical direction.

The insulation layers 1 can be produced in the well-known LOCOS technology (Local Oxidation Of Silicon), which enables the production of oxide layers of variable thickness with the aid of nitride passivation. The field plates described serve to reduce field peaks, for example in the vicinity of the gate electrode 13 or on the buffer 6 , However, the field plates are optional, can be designed in one or more stages and consist of metal and / or polysilicon.

2 shows an inventive multi-channel arrangement of a LIGBT transistor. The component has a first gate connection 13a , a second gate connection 13b and a third gate 13c on. These gate connections are over insulation layers 1 and 34 isolated from the semiconductor substrate. These gate electrodes are areas 41 . 42 . 43 respectively. 44 the interconnected p-tubs 11 respectively. 11a assigned, these areas being switchable as inversion channels via the gate electrodes. The basic structure is the same as in 1 except for the fact that per half anode area 5 three inversion channels can be switched. It is therefore the cross section shown along the first line of symmetry 21 and the third line of symmetry 39 to continue thinking in mirror image, so that analogous to 1 a parallel connection of many transistors results, but with more than one per half anode area 5 switchable area as an inversion channel. In the exemplary embodiment shown there are in the two connected p-wells 11 respectively. 11a more n-tubs 12 a . b and c intended. The previous reference numerals designate the same parts as in 1 and will not be described again. insulation layers 35 isolate the gate connections 13b respectively. c from the cathode field plate above 15 , In 2 are also a first top view level 28 , a second top view level 29 and a third top view level 30 located. The top view planes denote the planes that follow in the 6 to 8th are shown.

The parallel connection of several channel areas per anode area reduces the effective total channel resistance. This results in a high current density for a given voltage drop between Anode and cathode enabled. The latch-up strength is compared to the LIGBT with only one Channel increased by that the flowing from the anode to the cathode Proportion of the hole current itself divided into several channel areas. Opposite a trench LIGBT SOI (Silicon on Insulator) with several parallel channel areas is the component according to the invention cheaper and easier to manufacture, since the process and wafer costs are lower, because only Standard processes and standard wafers can be used. This multi-channel principle is can also be used with LIGBT components with vertical current flow, their rear side contact no over a diffusion area but over For example, a highly doped substrate is made on the front epitaxially applied layers are arranged.

3 shows another section 50 another embodiment. It is compared to 2 the anode area 5 and the buffers layer 6 through a single heavily n-doped drain area 51 replaced. In contrast to 2 is the embodiment according to 3 a MOS device that has a drain connection 52 , a drain field plate 53 and a source field plate 55 has that with the source connection 56 connected is.

The exemplary embodiment illustrates the applicability of the multi-channel principle to MOS devices Achievement of a small effective total channel resistance through parallel switched channel areas. With MOS devices too, the construction according to the invention a high current carrying capacity or a good passage behavior of the component, achievable with a high locking capacity.

4 shows a MOS device similar to 3 with the only difference to 3 that the drainage area as a flat drainage area 61 is formed, so not directly with the p-substrate 3 communicates, but through the n-area 4 is separated from him. Depending on the use of the component, there is a deep drainage area 51 or a flat drainage area 61 be provided. The deep drain area 61 is to be selected if an optimal transmission behavior is desired, ie the lowest possible forward voltage at a given current. Because of the deep drainage area, the strong current density increase occurring at the tip in the case of the flat drainage area is avoided and a more homogeneous current flow is achieved in the resurfing area. In contrast, the use of the flat drain area saves the long diffusion time necessary for deep drain diffusion.

5 shows a plan view of the third top view level 30 of a transistor device according to the invention. The line is marked 70 the cross-sectional plane shown in the cross-sectional drawings in the 1 to 4 is shown. The anode or cathode connections arranged like tines of two combs placed one on top of the other can be seen 17 respectively. 16 and their associated field plates 18 respectively. 15 , With reference numbers 73 the anode bond surfaces are provided with reference numerals 72 the cathode bond surface of the component is marked. In the intermediate area 71 between the interlocking teeth of the cathode or anode field plate, the insulation layer can be seen, which electrically insulates the field plate from the underlying gate connections. The gate manifold 74 connects the gate connections of the individual transistor cells to one another, whereby it can be seen that per tine of the "cathode comb" ( 15 . 16 ) three gate connections 13a, b, c are drawn. In this detail of the drawing it is in 2 described multi-channel principle recognizable in this view. Details of the layout are in the 6 to 8th shown. 6 shows the top view of a transistor device according to the invention in bipolar technology with multi-channel arrangement, in the first plan view level 28 as in 2 is marked. The unit cell of the periodically continuing layout is given by the area between the first line of symmetry 21 and the third line of symmetry 39 , In the example shown are per half anode area 5a three channel areas 41 . 42 and 43 assigned. The channel regions are regions of the contiguous p-wells that can be controlled via overlying gate connections that are insulated from the semiconductor with an insulation layer 11 respectively. 11a , N-tubs are embedded in the p-tubs 12 respectively. 12a such as 12b that have been introduced into the p-wells, as well as heavily p-doped doping zones 19 have been introduced into the p-tubs. In the exemplary embodiment shown, the component has one island per unit cell of the layout with three channel regions per half anode finger 83 of the n area 4 in the p-tub area. Otherwise the n-area runs 4 in the first top view level 28 meandering both around the anode areas 5a . 5b , ... as well as around the P-tub areas. The buffer layer lies here 6 between the anode areas 5a . 5b , ... and the N area 4 , This multi-channel arrangement is as already with 3 and 4 occupied, transferable to a MOS transistor component by the anode regions 5a . 5b , ... as well as the buffer layer 6 through a heavily n-doped drainage area 51 or alternatively through a flat drainage area 61 be replaced. Both in the case of the LJGBT and in the case of the lateral MOS transistor component, the rounding radii are to achieve a high reverse voltage 90 . 91 be sufficiently large at the anode and cathode finger ends so that the breakdown voltage of the component is not significantly reduced by geometrically induced field tips on the finger ends. For this reason, the cathode finger in a high-blocking LJGBT or MOS transistor for accommodating a plurality of channel regions connected in parallel does not generally have to be made wider than is necessary to achieve a high breakdown voltage anyway.

7 shows one too 6 corresponding top view of the second top view level 29 , where in 7 however only two unit cells of the layout are shown. In this second top view level 29 is the anode connection 17 to the anode area 5 seen. The two-part cathode connection per unit cell 16 contacts the heavily p-doped doping zones 19 and parts of the n-tubs 12 . 12a such as 12b , The gate connection 13 is made in two parts per half cathode finger, with the gate connection 13a meandering and the second gate connection part 13b is designed as a strip. Both gate connector 13a as well as gate connector 13b are on the buffer layer 6 facing away to the outside, as in 5 can be seen at the gate collector connection 74 to be able to be connected. The same applies to the third gate connection 13c in the second half of each cathode finger.

8th finally one of the shows 6 and 7 Corresponding top view of a semiconductor component according to the invention in the third top view level 30 , 8th provides an enlarged detail of the 5 dar with the assigned lines of symmetry 21 respectively. 39 and illustrates the covering of the component with field plates 15 respectively. 18 , between which only in the intermediate area 71 the insulation layer underneath looks out.

Claims (14)

Lateral transistor component with at least one insulated gate electrode ( 13 ), with lateral and vertical current flow, in a p-substrate ( 3 ), on the front of which is an n-region ( 4 ) is arranged, in which a heavily p-doped anode region ( 5 ) is embedded, the vertical current flow via a rear contact ( 7 ), characterized in that the back contact via a heavily p-doped diffusion region ( 8th ) formed area is electrically connected to the p-substrate. Lateral transistor component according to Claim 1, characterized in that the n-region ( 4 ) is designed as a resurf area. Lateral transistor component according to Claim 1 or 2, characterized in that the anode region ( 5 ) from adjacent areas of the n-region (4) through an n-doped buffer layer ( 6 ) is separated. Lateral transistor component according to Claim 3, characterized in that the buffer layer ( 6 ) has a greater depth of penetration than the n-region ( 4 ). Lateral transistor component according to one of the preceding claims, characterized in that the anode region ( 5 ) as a strip-shaped, at least two strips ( 5a . 5b ) area that is formed in the n-area ( 4 ) at least one strip-shaped p-tub ( 11 ) between the at least two strips ( 5a . 5b ) of the anode area is embedded in the at least one p-well at least one strip-like n-well ( 12 ) is embedded and that at least one inversion channel ( 41 ) can be generated. Lateral transistor component according to Claim 5, characterized in that at least two connected p-wells ( 11 . 11a ) between the at least two strips ( 5a . 5b ) of the anode area are provided and that as inversion channels ( 42 . 43 ) switchable areas of adjacent p-tubs ( 11 . 11a ) via a common gate electrode ( 13b ) can be controlled. Lateral transistor component with at least one insulated gate electrode ( 13a ), with lateral and vertical current flow, in a p-substrate ( 3 ), on the front of which is an n-region ( 4 ) is arranged, in which a heavily n-doped drain region ( 61 ) is embedded, the vertical current flow via a rear contact ( 7 ), characterized in that the drainage area ( 61 ) is designed as a strip-shaped area having at least two strips that into the n-area ( 4 ) at least two strip-shaped p-tubs ( 11 . 11a ) are embedded between the at least two strips of the drainage area, the drainage area ( 61 ) with a high potential relative to the strip-shaped p-wells ( 11 . 11a ) it can be loaded that at least one strip-shaped n-well in each of the p-wells ( 12a . 12b ) is embedded and that as inversion channels ( 42 . 43 ) switchable areas of adjacent p-wells via a common gate electrode ( 13b ) can be controlled. Lateral transistor component with at least one insulated gate electrode ( 13a . b ), with lateral and vertical current flow, in a p-substrate ( 3 ), on the front of which is an n-region ( 4 ) is arranged, in which a heavily p-doped anode region ( 5 ) is embedded, the vertical current flow via a rear contact ( 7 ), characterized in that the anode region ( 5 ) as a strip-shaped, at least two strips ( 5a . 5b ) area that is formed in the n-area ( 4 ) at least one strip-shaped p-tub ( 11 ) between the at least two strips ( 5a . 5b ) of the anode area is embedded, the anode area ( 5 ) with a high potential relative to the strip-shaped p-well ( 11 ) it can be acted upon in the at least one p-well at least one strip-shaped n-well ( 12 ) is embedded and that at least two inversion channels (via the insulated gate electrode) 41 . 42 ) can be generated. Lateral transistor component according to Claim 8, characterized in that at least two connected p-wells ( 11 . 11a ) between the at least two strips ( 5a . 5b ) of the anode area are provided and that as inversion channels ( 41 . 42 . 43 ) switchable areas of adjacent p-tubs ( 11 . 11a ) via gate electrodes that are electrically connected to each other ( 13a . 13b ) can be controlled. Lateral transistor component according to one of Claims 5 to 9, characterized in that cathode or source connections ( 16 respectively. 56 ) each via a heavily p-doped doping zone ( 19 ) with the p-tubs ( 11 . 11a ) are in electrical contact. Lateral transistor device as described in one of the preceding claims, because characterized in that, if n-type dopings are provided, they are replaced by p-type dopants, and if p-type dopings are provided, they are replaced by n-type dopants. Process for the production of semiconductor components in a p-substrate, with cathodes arranged on the front, Anode and gate connections and one on the back arranged rear connection, thereby characterized that before an attachment of the rear connection p-type doping atoms on the back diffused the p-substrate become. A method according to claim 12, characterized in that on n-doping atoms are diffused into the front of the component, so that emerging n-doped area is formed as a resurf area. A method according to claim 12 or 13, characterized in that instead of p-doping n-doping and instead of n-doping p-doping be used