DE1938647A1 - Arrangement of electrical connecting conductors - Google Patents

Description

Arrangement of electrical connecting conductors

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The invention also relates to an arrangement of electrical connecting conductors (Conductor tracks) on module carriers (prints), · those with electronic components or modules on one or both sides and can be filled with conductor tracks on both sides. Building block carrier plates that are fitted with building blocks or components are to be obtained - as is known - on the rear side conductor tracks, which are the components located on the front side of the plate or modules should connect to each other and to the power supply at the rear; the tax and Power supply connections of the modules through holes in the board and are soldered to the "conductor tracks" on the back. Since a large number of connecting conductors * (conductor tracks) is required to make the necessary electrical connections to establish a short, direct connection from one connection point to the next is usually not possible; rather have to the conductor tracks are laid in loops, as track crossings are not possible. This looping is special Complicated and confusing when, as is common today, a large number of components or modules, especially integrated ones Blocks, must be arranged on a single block carrier plate. Despite the small spatial dimensions With modern, integrated control modules, the space on the top of a is usually sufficient for extensive control or regulation systems single building block carrier plate for the inclusion of the required building blocks is not enough; therefore it is customary when necessary not only the top, but also the underside of the building block carrier plates with both building blocks or building block groups as well as to be filled with conductor tracks. It is often unavoidable that both command-processing input control modules, which voltages or currents in the microvolt or micro-

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Process ampe ^x re area, as well as output control modules, which under certain circumstances output voltages of a few hundred volts and currents of several amperes, must be accommodated on a single module carrier (print). With such a compact structure, capacitive and inductive couplings occur between output and input and / or the intermediate stages. The capacitive couplings, which are caused by the close juxtaposition of the conductor tracks, can still be avoided relatively easily, whereas the inductive couplings, caused by the extensive conductor track loops, can hardly be prevented.

To avoid interference on the module carrier (print), therefore, a favorable arrangement of the components and conductor tracks must be ensured from the outset. Such an order can however only be optimized to a certain extent because of the difficulty of the circuit unbundling, so that extensive additional interference suppression circuits are often necessary because of the costs and the additional space required are undesirable. Even 'module carriers (prints), which essentially only contain command-issuing control modules, such as power transistors or relays are common still equipped with integrated control circuits for these power amplifiers, which can lead to inductive coupling, which can trigger malfunctions or even destroy the integrated control circuits. A close concatenation of the Conductor tracks (loops) can also be taken into account known Hardly avoid decoupling rules in the event of a possible unbundling. The problem of highly sensitive lines (input lines) leading to integrated circuits in addition to lines carrying higher currents Arranging relays or contactors is recognized, but so far, to the desired extent, has not been resolved. Is that what it is? about the decoupling of conductor tracks on a module carrier (print), then there is only a very limited possibility of one Decoupling, since there is no longer any great possibility of variation in the unbundling and arrangement of the building blocks, especially then not if such a module carrier (print) is optimally used shall be.

Experiments and findings from it have shown that an optimal

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inductive (and partly also capacitive) decoupling is then achieved can be when the conductor tracks or conductor track sections to the contacts of the relay or the collector current of the power transistors leading conductor tracks practically on top of each other, but at the smallest possible distance from each other., in pairs be arranged above and below the module carrier plate (print). This means that all of the remaining conductor tracks are in place (Loops) of the lines which can be disturbed and which only carry low currents, e.g. control currents, largely in a neutral zone. On the basis of the knowledge gained in this way, it can be achieved that the interference suppression circuit that is usually required is dispensed with can.

Accordingly, the invention relates to an arrangement of the electrical connection conductors (conductor tracks) on module carriers (Prints) that have electronic components or modules on one or both sides and with conductor tracks on both sides can be occupied by the fact that the higher (or disturbance) currents carry them Conductor tracks are laid in loops, the planes of which are perpendicular to the loop planes of the only control currents Conductor tracks run.

According to a further feature of the invention, either the higher (or interference) currents carrying conductor track sections can be paired on both sides of the carrier (prings) are spatially one above the other, while the interference-prone, e.g. control current leading, conductor tracks each run in any loops on the top and / or bottom of the carrier (print) can or vice versa.

Embodiments of the invention are based on the following explained in more detail by four figures.

Relay decoupled output module carriers (prints) included, In addition to interfering conductive paths to integrated circuits, there are also conductive paths leading from the relay contacts to lead outside (to terminals). These conductor tracks have a signal level that can be several orders of magnitude higher than the integrated circuits. In order to avoid interference on the print ", a favorable arrangement of the conductor

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paths are strived for. Particularly the inductive coupling of contact-switched connection conductors (conductor tracks) prepare considerable difficulties, because an estimate of the coupling conditions (mutual inductance of the coupling loops) is extraordinary is difficult.

It is therefore desirable to connect the conductor tracks to the relay contacts to be spatially arranged in such a way that the coupling with conductor tracks to the integrated circuits is as small as possible are. This is the case when the two conductor tracks are closely adjacent to the relay contacts carrying high currents run towards each other (small loop). In one level (print area) however, no arrangement can be found in which every conceivable coupling is a minimum.

Using the example of linear lines according to FIG. 1, the mutual inductance for such parallel conductor tracks 1, 2; 3, 4 on the module carrier (print) P from the equation

M = / V ¹ in ^a U ^a 23
^{Zlr a} 13 ^a 24

calculate, with the disturbing (high current carrying) lines with 3 and 4, the disturbed (low current carrying) lines with 1 and 2 and the distances between the lines are denoted by a and the corresponding indices. In the formula: M the mutual inductance, / Uq the permeability, 1 the Line length and (e.g.) a .. * the distance a between conductors 1 and Ladder 4 etc.

The mutual inductance M becomes zero when the expression

^a 14 ^a 23 = 1

^a 13 ^a 24

becomes (In 1 = 0). However, this is not the case if they do not overlap Grinding according to Fig. 1 is not possible.

In the case of overlapping loops according to FIG. 2, an arrangement can be found in which the mutual inductance M = 0; With loops or distances of the same size a = a _1? = a ,. is there-

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if -

at the removal of the two loops, b = a (1 + 1/2. V ~ 2).

Understandably, with the large number of coupling loops on a print, only one arrangement of two inductively influencing one another can be used Lines that provide zero mutual inductance.

Decoupling is only possible when, according to the invention, a transition is made to a three-dimensional arrangement, as the exemplary embodiments according to FIGS. 3 and 4 are intended to illustrate. A decoupling is always given when the two loop planes are perpendicular to each other and the arrangement is essentially symmetrical with respect to a loop plane: a .., = β ... , a ₂ 3 = 8 · ρ4 · It results

M = / ¹ O * ¹ InI-O.

This arrangement can largely be implemented if the (interfering) conductor tracks 3, 4 (Pig 3, 4) carrying higher currents to contact r one, in Pig. 4, not illustrated, relays in pairs on both sides of the print P spatially one above the other lie as shown schematically in the Pig. 3 and in perspective in the Pig. 4 is shown. The magnetic fields the disturbing loop 3, 4 are approximately in the neutral zone of all disturbed loops 1, 2, regardless of the Location and arrangement.

With such an arrangement according to the invention, the inductive and largely also the capacitive interference level can be decisive be lowered without any special during the disentangling of the print Additional conditions must be observed; in addition, interference suppression circuits can largely be dispensed with.

4 figures

2 claims

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Claims (2)

PLA 69/1136 - 6 -. Claims 1.) Arrangement of the electrical connection conductors (conductor tracks) on module carriers (prints) that have electronic components or modules on one or both sides and with Conductor tracks can be occupied, in particular on carriers (prints) equipped with power components, characterized in that that the higher (or interfering) currents carrying conductor tracks (3, 4) are laid in loops, the planes of which are perpendicular to the loop planes of the conductor tracks that only carry control currents (1, 2) get lost. . 2. Arrangement according to claim 1, characterized in that either the higher (or interfering) currents carrying conductor track sections (3, 4) in pairs on both sides of the carrier (print P) are spatially on top of each other, while the fault-prone, e.g. control current carrying, conductor tracks (1, 2) each in any Loops can run on the top and / or bottom of the carrier (P) or vice versa. 009886/1916 Blank page