DE1931765A1 - Coincidence memory matrix - Google Patents

Description

DR. MOLLER-BORS DIPL.-ING. GRALFS DR. MANITZ DR. DEUFSL

PATENT LAWYERS

Braunschweig, June 21, 1969 Our reference: Q- 1792 - Kl / Lie

MOTORS CORPORATION Detroit / Michigan "TJ" S "A.

Coincidence memory matrix

The invention relates to magnetic information storage devices, in particular a coincidence memory matrix which contains information in a plurality of addressable memory locations can save.

They are storage devices with variable content and Memory devices with permanently programmed content are known. The latter use multi-hole cores.

The invention aims to meet the requirement that a part of the memory of a computer in an aircraft should be permanently programmed so that the information stored in it is retained in the event of a transient malfunction. Two different memories are to be provided, one of which is for fixed programmed operation and the other one designed for variable operation would increase the cost, technical Cause problems and an inadmissible packing space

demand. 009840/1824

To achieve this object, a coincidence memory matrix according to the invention is characterized by a variable part with erasing readout, which has a switchable biremanent magnetic storage element at each of its addressable storage locations has, and by a fixed part with non-erasable readout, which can only be addressed to certain addressable A switchable biremanentes memory element has memory locations permanently programmed in accordance with a scheme Information of a magnetic property that is permanently in fixed part of the memory is stored, as well as by locking means for the memory section with erasing readout for restoring and changing the information in this. Part and by reading means common to the part with erasable omission and the part with non-erasable reading and serve to read out the information.

By combining the firmly programmed and changeable programmed memory are those mentioned at the beginning. technical problems are overcome and costs are reduced. In addition, the elimination of cores in the. fixed programmed parts of the memory system reduce the total cost of the cores and the alignment time for each matrix, since the blocking winding in the part with fixed content is omitted. In addition, the memory can be used together with the conventional electronic control devices associated with the variable storage devices are operated.

The invention particularly relates to coincidence memories from a Plurality of matrix units, each of which has a part erasing readout (DRO) and a permanently programmed part

009840/1824

with non-extinguishing tripping (NDHO),

The invention provides a combined memory of one
Part with erasing read-out (notepad) and a wired part with non-erasing read-out, in which the same elements are used for address selection, read-out and the storage cycle and in which a fixed concept is used
non-erasing readout by omitting magnetic core storage elements at preselected storage locations in each of the
Matrix units obtained while using
Reading windings with the same geometric pattern is allowed regardless of the different pattern of the omitted core positions in each matrix.

The invention is described below in connection with the drawing described.

Fig. 1 is a block diagram of the general storage facility a computer using a memory according to the invention.

Fig. 2 is a timing chart for explaining the timing and timing

Addressing logic used for memory operation will.

Fig. 3 is a block diagram of the control circuit for a
Axis of control lines of the accumulator »

009840/1824

Figures 4A and 4B explain the stringing patterns the control lines through the various matrix units of the memory.

Fig. 5 shows the type of assembly of the various

Matrix units of memory according to, orientation.

Fig. 6 explains the relative proportions of a matrix,

which are assigned to the parts of the memory with erasable and non-erasable readouts and the blocking winding for the part with the canceling readout.

7 shows a part with erasable and a part with non-erasable readout on a memory matrix according to the invention.

fe Fig. 8 shows the scheme of the reading winding in the matrix units of memory and

Fig. 9 shows a hysteresis loop for explaining a Operating mode of the memory part with non-erasing readout.

009840/1824

-r 5 τ

1 illustrates the general memory system of a computer in which a memory according to the invention is shown at 10 together with the associated input, output and clock controls is shown. It is a coincidence core memory with a "notepad" part with erasable reading and a permanently programmed part with non-erasing readout. The total storage capacity is 6144 words in thirteen matrix units. Each matrix has 128 χ 48 memory positions between the combined parts with erasing and with non-erasing readout and represents a different bit position of each of the memory words.

The central processing unit has access to the memory of the computer (not shown), which supplies an encoded address to a 13-bit position flip-flop address register 11. The binary outputs of the address register are supplied via an address decoder 12, which is connected to the line selection matrix 14, the X- and Y-axis access switches Section 14 contains X and 14Y.

The X-axis access switch section 14X comprises an array of 14 read switches and an array of 14 write switches for the selection of one of the 48X control lines to be used in a 6x8 matrix with six groups of eight lines arranged. One end of each control line included in a group of eight lines are connected to the same switch of the six read and six write switches that act as Read sink and write source switches are designated. The other end of each control line in a group of eight control lines is via a control diode, with another pair of read / write switches joined by eight such pairs, the

009840/1824

are designated as read source and write sink switches. Each X control line can therefore be activated by activating a the six reading sink switches or sohreib source damage and one of the eight read source switches or write sink switches can be selected.

The Y-axis access switch section 14-Y comprises two arrangements of 24 read and write switches for selection one of the 128 Y control lines in an 8x16 matrix with eight groups of six ten lines are arranged.

The address a send encoder 12 decodes the memory address command, to logical addressing signals the read and write sink and Supply source switches connected to the X line and the Y line associated with the addressed word are. Depending on whether the addressed word is in the part with the erasure or the part with the non-erasure readout of the memory, the decoder also enables an output signal to be derived with a level for erasure readout or non-erasure readout from one or more arrangements of outputs of the address register.

The addressed read and write switches become different Times from the clock control section 15 of the memory activated and connect a thereby selected X-line and Y-line in separate control circuits for the Receipt of control currents supplied in the reading direction and for

009840/1824

a series of control currents supplied in the write direction during the corresponding periods of the memory cycle.

The ■ clock control section 15 of the memory is activated by a memory start pulse MSP 60 from the clock pulse unit. It contains a flip-flop binary counter which is controlled by a bit clock generator to provide the read, lock and write clock input signals for the memory at C _t E and B in the timing diagram of FIG. The clocked output signals for reading out the memory sections with erasing and non-releasing readings are shown at K and P in FIG.

The control circuit for the X axis of the control lines is shown in FIG. 3 together with the activating clock control signals for it. The read sink switch $ 0 and read source switch 51 are activated for a read-pulse-controlled, erasing readout and for a clock-pulse-controlled, non-erasing readout NDRO (DRO * ¹ ). During this time, current flows from the power supply device 32 in one direction through the read sink switch 30, the control line 33, a control diode 34, the read source switch 31 and a current regulator denoted by 16 in FIGS. The write sink switch and write source switch 37 are activated for a write clock controlled DRO process and a read clock controlled NDRO process, during which current from the power supply in the opposite direction through the control line 33 t

009840/1824

Write sink switch 36, a control diode 38, write source switch 37 and current regulator 16 flows.

The control circuit for. is the Y axis of the control lines similar with the exception that the Y-axis current regulator 17 a slower rise of the control currents in the Y-axis control lines as the current regulator 16 for the X-axis control lines, as in Fig. 2 in lines F and G is indicated. In addition, the Y read sink and Y read que 11 it receives write for a non-deleting read process * cycle-controlled and not cycle-controlled.

The sense amplifiers shown at 18 in Fig. 1 are during of the readout in conjunction with the read windings for each core matrix is used to perform a parallel readout of a To obtain bits of information from each matrix into the data memory 20. The sense amplifiers are used for an erasure readout with the marking pulse in line K of FIG. 2 and for a non-erasing readout with that shown in line P of FIG Marking pulse controlled.

The reverse current amplifiers shown at 19 in FIG. 1 are connected to the reverse winding during writing used to ensure that information from data memory 20 is stored in parallel in the part of each matrix which is responsible for the erasure reading is intended, is written. The reverse current amplifiers are by the in line E of FIG Locking clock signal shown and controlled by a data bit

009840/1824

from an associated part of the data memory 20 selectively activated.

The matrix 40 shown in Figures 4A and 4B includes toroidal memory elements 42 which are rectangularly arranged on the X and Y control lines. The cores are made of lithium ferrite and can be operated over a wide temperature range. Each matrix contains a part for erasable readout and a part for non-erasable readout, with cores being omitted at certain memory locations for the part with non-erasable readout in order to achieve a fixed memory program. The parts with extinguishing readout (DRO) and with non-extinguishing readout (NDRO), the head of a coordinate axis of control lines and the L _e sewicklungen together. The DRO part contains a conductor group of the other coordinate axis and a blocking winding. No blocking winding is provided for the NDRO part of each matrix.

After the matrices are aligned and wired as described below, they are assembled by using the Core matrices over the front and rear sides of four spaced-apart mounting plates 51 to 54, as in FIG Fig. 5, can be folded to provide a compact arrangement to train. Each of the mounting plates has a heating surface 57, which is used for heat dissipation and noise suppression serves.

The matrices are rectangular in shape and are wired with 128 Y lines and 48 X lines. These lines run continuously

009840/1824

- ίο -

through all of the matrices to avoid the need for soldered connections between adjacent matrices. Every matrix has that same core orientation pattern, with adjacent cores in each matrix in mutually perpendicular directions are aligned.

Each Y line runs straight through all of the matrices while every X line between adjacent matrices changes direction. The odd rows 1 to 127 of the Y lines, which are designated by YOOO to Y 126, enter on the left side of the matrix 13 and leave the right side of the Matrix 1, as shown in Fig. 4A, while the even Rows 2 through 128 of the Y lines labeled Y001 - Y127 are to enter on the right side of the matrix 1 and exit the left side of the matrix 13, as shown in Fig. 4B is. The unequal columns 1 through 47 of the X control lines XOO through X46 occur on the top of the matrix 13 and leave the lower side of matrix 1, as in 4A, while the even columns 2 to 48 of the X lines X01 to X47 on the lower side of the matrix 13 enter and exit the upper side of matrix 1, as in Fig. 4B indicated.

So that every matrix has the correct electrical properties and using the same core orientation pattern, the odd X-conductors such as XOO through X46 used in the first and appear in the forty-seventh column of matrices 13 and 1, crossed to go through the even columns, like columns two through forty-six, in reverse to run through the matrices 12 and 2 while the ladder

009840/1824

of the even columns, such as XOI to X47, which are in columns 2 and 48 of matrices 13 and 1 appear to be 'crossed' to duroh the odd columns, like 1 and 47, in opposite directions Direction to run through the matrices 12 and 2, as indicated in Fig. 4B.

The blocking windings, only one of which is only for the Part of the matrix with a canceling readout is intended to start and end on the same side of each matrix. Each blocking winding runs continuously back and forth in such a way that the Direction of the reverse current flowing through the direction of the current flowing through the X control conductor during a Write cycle is opposite. According to FIG. 6, in which the Matrix is aligned so that the course of the X and Y conductors can be seen in their assigned axes, the Blocking winding 62 in parallel with the X conductors in the DRO part every matrix

Two read coils 51 and 52 are provided for each matrix. The reading windings run through both the DRO and the HDRO part of each matrix in a complementary manner Pattern along opposite diagonals of the matrix. As shown in FIGS. 6 and 8, the begin and end Windings on the same side of the matrix.

Of the 6144 words of the storage capacity, 1024 words are variable Contents and are contained in the DRO part (with erasing readout) of the memory. The remaining 5120 words

009840/1824

of the memory have a fixed program content and are in the NDRO part (with non-erasing readout), as shown in FIG. 7 provided} included. The first eight of the 48 X addressing control conductors (each matrix are used for the in (each matrix DRO part used. The remaining 40 X control conductors are assigned to the permanently programmed part of the memory. The Y-conductors run through both the DRO and the NDRO part (each matrix and are assigned to both parts »

The memory receives a fixed memory program through the elimination of cores at the memory locations from which zero values can be read out. They are therefore only in certain storage locations of the NDHO section provided according to a cores Pattern of fixed information of a magnetic polarity that corresponds to a pattern of stored unity values. Since the in Each word contains different information, each matrix has a different pattern of free zero values representing the Corresponding to core positions in the NDRO part.

Fig. 7 illustrates a combined DRO and NDRO part a matrix in a memory array in which the first two rows of X conductors are in the variable DRO part contained in the matrix and combine a complete set of memory cores * The permanently programmed Part only has cores at the memory locations that represent the value one and is open to core positions which are assigned to the zero values and are marked in the figure by a (^).

009840/1824

In addition to reducing the number of cores, this type enables a fixed memory program to be achieved, eliminating the need for a blocking winding for the permanently programmed memory section, with the consequent lower power requirement for the blocking amplifier and for the core alignment time for the variable memory section. The removal of cores from the NDRO part of the memory can, however, lead to an imbalance in the shuttle noise on the read lines that originates from the remaining cores on a control line from which an unequal number of oppositely oriented cores are removed. Under the most unfavorable conditions, all the remaining cores on a control line induce shaking noise of the same polarity on the read lines. This shaking noise can therefore, instead of canceling itself out, grow cumulatively and generate a noise voltage in the read output signal which exceeds the threshold value or the one / zero discrimination level of the sense amplifier and can lead to an ambiguous interpretation of a zero as one.

In the described embodiment with the relatively slow one Increase in the Y current can be assumed that the characteristics of the cores and the sense amplifier are such that up to twelve unquenched shaking noise voltages are permissible in order to achieve an acceptable signal-to-noise ratio in the amplifiers. The worst case occurs when there are 64 cores on an X line and 20 cores on a Y line are. The resulting shaking noise then exceeds the permissible number of unquenched noise voltages, um ; Distinguish a one from a zero in the sense amplifiers to be able to.

009840/1824

The present memory is therefore designed so that the the larger delta or the smaller hysteresis loop shuttle effects are concentrated in the X-lines a greater number of core positions is created on an X line than on a Y line, and that the memory by controlling the X lines with a faster rising Electricity than is operated in the Y-lines. This is done by the various rise time control parts in the Current controllers for the X and Y axes. In addition, the X lines of the NDEO part of the memory become an earlier one Time controlled as the Y lines in which a blocking clock signal is used for the control currents of the X-axis and a write clock signal is used for the control currents of the Y-axis, to feed the X and Y control streams to the X and To offset Y-lines for a NDEO-Le sevor gang in time, as shown in lines N and 0 of FIG. In this The greater delta effect sounds wise, that of the large number of undeleted vibration noise voltages on an X line of the NDEO part comes from before the current in the later controlled Y-line has reached the level to together with the field generated by the current flowing in the X-line to switch a chosen core in the NDEO part. Fig. 2 explains how the slow rise time of the Y read current in line 0 prevents a zero output signal from being erroneous is interpreted as a one output due to the delta noise of the Y-axis. That shown in line Q in FIG Signal shows that the delta noise generated by the X read current occurs and decays again before the rise / of the Y read current takes place.

If the Y read current had the same increase as the X read current, the delta noise it generated would be in the read-off mode.

009840/1824

superimpose output signal and the sum of these voltages would exceed the one threshold value. The supply of the NDRO marking signal would therefore result in a read signal with the level one instead of the level zero. A relatively slowly increasing one However, Y read current reduces the size of the delta appearance the Y-axis and thus allows the zero level to be read out correctly.

The delta noise, i.e. the sum of the shaking noise voltages, is further processed by dividing the read winding of each matrix into a number of windings such that that the maximum number of unquenched shaking noise voltages from an X or Y line in any of the read windings, crossing this conductor remains within the allowable number and below the discrimination level of the sense amplifiers. In quantitative terms, the number of read turns for each matrix depends on the number of NDRO-X lines, (or possible core positions on a Y-line), divided by twice the value of the permissible number of undeleted shaking noise voltages

In the present case, two such reading windings are used, each of which traverses the entire area of the matrix, but only half of the cores or storage locations each X and Y lines of the matrix served. The total number of undeleted Shaking noise voltages in each read line thus remain within the permissible undeleted shaking noise and below the discrimination level of the sense amplifier provided for each sense winding

009840/1824

I OO I / 00

The sense amplifiers are of conventional construction · The 'amplifier outputs are connected to the input of the associated {part of the data memory. It should be noted that that each reading winding has the same geometrical configuration regardless of the different patterns of open core poeitions on every matrix. ·

In addition to the aforementioned tools, the part of the memory with non-erasable readout uses a read preparation mode which results in a high output signal level leads from a switched core. Instead of reading a core during the initial part of the memory cycle, as in the part with the erasure reading occurs, a core is stored in an addressed memory location of the part with the non-erasable Read-out of its permanent state of a magnetic one Polarity is opposite in its undisturbed remanence state magnetic polarity brought. The core is then read out when it has subsequently returned to its original state magnetic polarity is switched back, giving a full output signal

This process is illustrated in FIG. 9. In this figure denote the points P and N the remanence states of an undisturbed Kerns, according to the main hysteresis loop shown is controlled. The delivery of half-size selection streams to the control lines causes the cores, which are subject to the action of only one of these lines, magnetically along the smaller hysteresis loops, e.g. NQT. This also explains the nature of the shaking noise

009840/1824

■ »Effect of an unselected or partially disturbed nucleus
on the control line · Depending on the previous history, namely whether positive and negative or read and write currents of half size flow through the control line on which the core is located
is located, this can be at one of two bemanence levels such as
B or L be disturbed · or deviate from the points N or F · If such a disturbed core would be read out after it
is controlled along the curve BSO or LMN, the resulting change in flux induces less than a full output voltage from this core in the read winding.However, if the core is controlled from point L to its undisturbed, oppositely directed emanence state at point N and reads it out, after it is then controlled along the curve NOP, the result is a higher output signal that is assigned to the full output signal "one".

To increase the improvement of the one-zero distinction level or signal-to-noise ratio in the read-out signal, the interrogated kernels of salvation with non-erasing readout are in
brought to their state corresponding to signal one, each time the NDEO part is to be read out
possible loss of information »between the memory cycles or switching the memory off and on is prevented.

From Pig. Figure 2 shows that the parts with erasable readout (F to K) and with non-erasable readout (L to B) of the memory are selective and reversed with respect to read and write operations during the corresponding parts of the memory access
were operated.

009840/18 * 4

In the case of an addressed word in the DEO memory section, the addressed line pairs which select the reading switches of the X and Y axis switching sections 14-X and 14Y are actuated upon receipt of a reading clock signal. This read clock signal is derived from the memory control logic 15. Upon activation of the read switches, half selection control current flows in one direction through the selected X and Y lines. The sense amplifiers are driven by the marker signal shown in line K of FIG. 2 in order to carry out an erasing read operation during the reading phase or the initial part of the variable memory cycle.

The addressed pair of line select write switches of the X and Y switch sections 14X and 14Y are activated upon subsequent receipt of a DRO write clock signal so that a current flows through the same selected lines but in the opposite direction during the subsequent write phase of the memory cycle. Before activating the write switch, however, the blocking amplifiers 19 for the matrices which require an input signal zero for a specific memory location of the data memory are activated by the blocking clock signal which occurs before the write clock signal, as can be seen from columns D and E in FIG. The activated blocking amplifiers cause a current to flow in their respective blocking windings in order to prevent the subsequently supplied write currents from switching the addressed cores of the special matrices to the on-state. ⁱ

Is the addressed word in the part of memory with non-erasing Readout included, so will the write switches

009840/1824

activated in front of the read switches. An addressed pair of Writing holders of each of the parts 14X and 14Y are received upon receipt of an NDRO read clock signal, so that half selection currents in the write direction during the initial phase of the hard-coded memory cycle through the selected X and Y lines flow · This becomes a one-state representative Core at the addressed memory location of the NDRQ part Everyone Matrix prepared. The read switches for the X and Y switching parts are subsequently activated so that half selection currents through the selected X and Y lines flow in the reading direction after an NDRQ blocking clock signal is applied to the addressed Read switch pair of the part. 14X to drive, and after an NDRO write clock signal is supplied to the addressed Activate pair of readout holders of part 14-Y. The one in line P the marking pulse shown in Fig * 2 is then during the the latter part of the memory cycle is fed to the sense amplifiers in order to receive the information from the read windings in parallel operation output to the memory output data memory.

009840/1824

Claims (1)

Patent claims Coincidence memory matrix for storing information in a plurality of addressable memory locations, characterized by a changeable part with an erasing Readout (DHO) at each of its addressable memory locations a switchable biremanentes magnetic storage element (42), and by a fixed part with non-erasing readout (NDRO) that only has a switchable biremanentes at certain addressable memory locations The memory element (42) has a magnetic piece of information permanently programmed in accordance with a scheme Property which is permanently stored in the fixed part of the memory, as well as locking means (62) for the part with erasing readout (DRO) of the memory (10) for restoring and changing the information in this part and by reading means (51 »52), which the part with erasable readout (DRO) and the part with non-erasable readout (NDRO) of the memory (10) are common and for reading serve for information « Coincidence memory according to Claim 1, characterized in that the magnetic storage elements (42) are coupled to control lines (33) which run in the two directions of a pair of coordinate axes (X, Y), and that the control lines (33) one of the coordinate axes ( X, Y) are common to the DRO part and the NDRO part of the memory. 009840/1824 -3 coincidence memory according to claim 2, characterized in that that the magnetic storage elements (42) are magnetic cores • and that the part of the memory (10) with non-erasing readout (for example X3 to X6) only in certain memory locations Has cores, while these cores (# ■) to the remaining places are missing. 4. Coincidence Speieher according to claim 3 »characterized in that that the memory (10) consists of a plurality of different bits representing matrix units (40), of which each has a DRQ part and an NDRO part that the NDRO -'- part has a different scheme of core defects (*) in each of the memory matrix units (40) and that the reading means have separate reading windings (51 » 52) contain the same geometric configuration for each matrix (40) of the memory (10), regardless of the different one Schemes of core vacancies (# ') of each of the matrix units. 5. Coincidence memory according to Claim 4, characterized in that the reading means for each matrix (40) contain a plurality of reading windings (51 »52-) , each of which runs through the entire area of the matrix (40), but only a proportional number of storage locations in accordance with the number of read turns (51, 52) for each matrix (40). 6 · coincidence memory according to claim 5, characterized by means (30, 31, 32, 34, 16) for feeding the memory control logic (15) with a first clock signal (C) and a second clock signal (D) and by means which operate the DRO part and - the NDRO part selectively and vice versa during the corresponding cycle times of the storage cycle 009840/1824 Coincidence memory according to Claim 6, characterized in that the NDRO part of the memory carries out a read preparation cycle in which a magnetic storage element (4-2) at an addressed storage location in the NDRO part is brought into an undisturbed remanence state during the first! part of the memory cycle and during dee second! part of the memory cycle is read out. 8. coincidence memory according to claim 7 »characterized» that the clock control means for the memory cycle is a Leee-T akb signal (G), after its decay a locking clock signal (E) follows, as well as a write clock signal (D), which begins after the beginning of the lock clock signal (Ξ) that the Control lines that run in the X direction between the DRO part and the NDRO part of the memory (10) arranged and that the control lines in the X direction, which are assigned to the NDRO part of the storage unit (for example X3 to X6) are energized during the blocking cycle (E) of the memory cycle, while the Y-directional conductor during the subsequent write cycle (D) of the 'memory cycle within the read process of the NDRO part of the Memory are excited Coincidence memory according to claim 8, characterized by a sense amplifier (18) for each of the sense windings (51 * 52) of a matrix (40) and in that the Speichersteu- _f erungslogik (15) to the sense amplifiers (18) of each matrix (40) during the supplies a first marking signal (K) during the first part (G) of the storage cycle for a DRO readout and a second marking signal (P) during the second part (D) of the storage cycle for an NDRO readout. 009340/1824