DE1916353A1 - Digital phase meter - Google Patents

Description

Digital Phasonmesserb Phase measurements are known to be phase difference measurements, by which the phase difference between a measurement signal 5M and a reference signal SB, both of which have the same frequency, is determined. Such phase difference measurements are known especially very difficult when the frequency of the measurement signal or the reference signal is unknown and the phase difference measurement is not only fully automatic, but can also be carried out in the shortest possible time.

The invention is based on the object of specifying a phase meter, who works digitally and avoids these difficulties.

The digital phase meter proposed to solve this problem is characterized in that the sinusoidal kleßa signal 5M and the sinusoidal Reference signal SB first time stamps ZM and derived using means known per se which in the case of both signals mark the temporal occurrence of the same phase, that to obtain a measure of the temporal length of the period of the reference signal SB and / or the measurement signal SM identified by two successive time stamps ZB Period TB of the reference signal Sg and / or that of two successive time stamps ZM marked period TM of the measurement signal SM with pulses I, which at least have approximately constant pulse repetition frequency fI, counted and thereby in in the former case the count value WB and in the latter case the count value WM obtained and is displayed and / or output, where = TB.fI = WM = TM that to obtain a Measure of the phase difference between the reference signal SB and the measurement signal SM the Time interval TBM, which begins with the occurrence of a time stamp ZB and with the temporal occurrences of those immediately following this time mark Z in time Time stamp ZM ends with pulses I, which are at least approximately the constant pulse repetition frequency fI, counted and thereby the Count value WBM obtained, displayed and / or is output and / or that to obtain a measure of the phase difference between the measurement signal S14 and the Besuggsignal SB the time interval TMB, which with the temporal occurrence of a time stamp ZM begins and with the temporal occurrence the time marks Eg immediately following this time mark ZM ends with Pulses I which have the at least approximately constant pulse repetition frequency f1, counted and thereby the count value W14B obtained, displayed and / or output is that to obtain the phase difference then with known computing means one of the count values WBM or WMB is divided by one of the count values WB or ltM and the result obtained is multiplied by one of the values 360 °, 2 # or 1 @, and the result of this multiplication is displayed and / or output (note that depending on the values used, the result is either in degrees, Bo.

gen Maß or in a J4ass determined by k and either the real phase difference or the difference between 3600, 2 # or k and represents the real phase difference) that in the case of simultaneous occurrence of the time stamps ZM and ZB, no pulse counts and no calculations are carried out instead, the value lTull is displayed as the result of the phase difference measurement and / or is issued.

The figures serve to explain advantageous examples the invention.

Fig. 1 shows the block diagram of a typical embodiment the invention.

The source of the measurement signal is called QM, that of the Reference signal the designation QB. These sources can e.g. B. his antennas or Generators.

Both sources are only then available with one channel VM resp.

a so-called double-channel amplifier V connected when the from Signals supplied to the sources are too high-frequency or too high for a phase comparison are weak. The amplifier V can therefore be a pure double-channel receiver (such as e.g. B. the TELEGON-V) or a double channel amplifier.

The sources QM and QB or diq two outputs of the double channel amplifier V are connected to the time stamp formers FN and FB, the time stamps from the measurement signal SM ZM and derive the time markers ZQ from the reference signal SB and pass them on to the measuring stage M. In this measurement level 1, the count value WM or WB and the count WMB or WBM obtained and passed on to the computing stage R, which consists of these two Counter values, the phase difference is calculated and output to æ. B.

a display device D.

Fig. 2 shows the basic circuit of a typical embodiment the measuring stage M.

In Fig. 2, flip-flop 24 represents the electronic switch for commissioning the measuring stage.

to switch off the operation of the measuring stage the input EA is on Short signal supplied and thereby passed on to the R input of the flip-flop 24, so that this flip-flop switches over and then supplies a voltage to its Q output, which is fed to the R input of flip-flop 20 and thereby prevents flip-flop 20 supplies a voltage at its Q output.

To switch on the operation of the measuring stage, input EE is on short signal supplied and thereby passed on to the S input of flip-flop 24, so that this flip-flop switches over and then a voltage at its Q output supplies. When this voltage is switched on, the so-called single shot 25 causes a pulse to be generated which is fed to the input of the flip-flop 6 is and thereby switches this flip-flop, so that flip-flop 6 from now on its Q output supplies a voltage. As can be seen from Fig. 2, this Voltage used to reset flip-flops 9 to 12 and counters 17 and 18 to zero. When this reset is done (flip-flops 9 to 12 provide their Q output and counters Z1 and Z2 have a corresponding voltage at their A0 output), is also AND gate 13 opens and supplies the R input of flip-flop 6 and the input of Flip-flop 20 a voltage.

This toggles these two flip-flops and flip-flops 6 now supplies a voltage to its output 4, each of which has an input of the AND gates 1, 4 and 5 is fed, while flip-flop 20 now has a voltage at its output Q delivers a different input of each of the AND gates 1, 4 and 5 and to which one input of the AND gate 23 is fed. The measuring stage is now ready for operation for the first reading.

The embodiment of the measuring stage shown in FIG. 2 is arbitrary designed in such a way that the measurement can be carried out after the measurement readiness for operation has been established A start is always made as soon as the measurement time mark ZM occurs and not the reference time mark, for example E.g. (Of course, ZM and ZB occur simultaneously when the measurement signal SM and the reference signal SB have the same phase, but this special case will only be treated more often).

Aagenonnen, however, only the reference time stamp ZB occurs first, so it comes from the. Entrance EB intended for them, inter alia. to and gate 5. This The gate is blocked, however, since flip-flop 9 is still set to zero and is therefore on his Q-Aus £ ang, which inter alia. flit is connected to an input of the AND gate 5, none Voltage supplies. As a result, this reference time stamp is ignored by the measuring stage.

But if the first measuring time mark ZM hits the one intended for it Input EK on, then it arrives at AND gate 4 and opens and passes it; because at three of the four entrances of the AND gate 4 yes are already before the arrival the Measurement time mark ZM voltages: firstly, the output voltage of inverter 11 (since an Input EB no reference time mark occurs), secondly the voltage of the Q output from flip-flop 6 and thirdly the voltage of the Q output of flip-flop 20. These The first measurement time marker ZN therefore passes AND gate 4 and arrives, among other things. to the S inputs the flip-flops 9 and d0 and switches these flip-flops over. This becomes an AND gate 13 blocked, AND gate 5 is ready for the next reference time marker ZB, and the AND gates 14 and 15 are opened, so that the generator 19 generated from now on Counting pulses that are already at one of the inputs of the AND gates 14 and 15 (AND gate 16-Yes is open, since flip-flop 20 supplies a voltage at its Q output) to the counting inputs EZ of counters 17 and i8 arrive and counted in these counters will. The resulting current count / end values are continuously from the count value outputs AW of the counters 17 and 18 the inputs of the temporarily blocked AND gates 21 and 22 transmitted.

As soon as the next reference time stamp ZB arrives at the input EB, it arrives she to the AND gate 5 and opens and passes it; because at four out of five entrances to the And-gates 5 are already before the occurrence of these. Firstly, the output voltage of the inverter I2 (there at the entrance EM no measurement time marker occurs), secondly the voltage of the Q output of the flip-flop 6, third the voltage of the Q output of flip-flop 20 and fourth the voltage of the Q output of flip-flop 9. This reference time mark thus happens and gate 5 and goes to the S input of the flip-flop 11, which is toggled thereby and therefore no longer supplies a voltage at its Q output that is necessary to keep it open of the AND gate 14 is a prerequisite. Thus, the AND gate i4 and the counter are now blocked 17 Leine can receive and count more counting pulses.

The final count of the counter 17 is a measure of the phase difference between the measurement signal SM and the reference signal Sg, The counting operation of the counter 18 becomes however, it is not stopped, but continues until the next measurement time stamp arrives ZM.

If the next measuring time stamp ZM arrives at the input EM, then it arrives she to the AND gate 4, opens and passes this gate, opens and passes the AND gate 7, at one input of which the voltage of the Q output of the flip-flop already lt lies, passes OR gate 8 and reaches the input of flip-flop 12, which thereby is switched and thus no longer the one to keep the AND gate open 15 needed Supplies voltage from its Q output. Therefore can now the counting pulses of the generator 19 no longer reach the counter 18 either and be counted. The end value of the counter 18 is a measure of the phase difference from 2X resp.

Since now flip-flop 12 from its Q output from a voltage each one of the entrances of the AND gates 25 and 22 leads, these two AND gates are opened and the final count of counter 17 leaves the measuring stage via output hD, the final count of the counter i3, however, via output Ap.

Since the two end-of-count values are output at the same time, opens AND gate 23 and supplies a signal via OR gate 26 to the S input of flip-flop 6, that switches the flip-flop 6, so that its Q output now has the voltage again supplies, which for the already described zero resetting of the flip-flop 9 to i2 and the counters 17 and 13 are required, d. H. to produce the new Neß operational readiness. The measuring operations repeat themselves continuously in the same way until they by supplying a short signal to input EA and thus to the R input be stopped by flip-flop 24 (shutdown!).

In the special case of simultaneous Ein fons the measurement time stamp ZM and the reference time stamp ZB (i.e.

Phase difference is zero) AND gate 1 is opened and delivers over the OR gate 18 to the S input of flip-flop 12 a voltage that this flip-flop toggles and thereby the immediate output of the nonentan end-of-count values of the two Counter 17 and 18 effected. It should be noted that the counter in this special case Yes, have not counted at all, so that two values zero are output.

Of course, instead of what is described here and chosen arbitrarily Embodiment of the measuring stage also any other suitable measuring stage circuit be used.

As already mentioned, the phase difference z. B.

as follows: phase difference characterizing phase difference = counter value / total period. 2 # (or 360 °, or k).

Characteristic counter value For this it is also possible to write in a simplified manner and therefore WD.K = WP. ## also applies. (2) Now X is freely selectable, ie given and either equal to 2 #, 360 ° or k. Furthermore, the two count values WD and Wp Ja are obtained through the two counting operations.

Sonit it is completely indifferent whether the phase difference on direct Paths according to equation (1) or indirectly according to equation (2) is obtained. While the extraction of the phase difference is easy to understand on direct days and with well-known division and multiplication circuits. so z. B. can also be easily carried out with a normal digital computer, allows the Determination of the phase difference in an indirect way, namely according to equation (2) possibly the acquisition of special operational advantages and the use less complex computing circuits, which are, however, less well known.

This is described in more detail below.

Since the determination of the two count values is anyway by counting the pulses of two pulse trains of a very specific length, the phase difference could be determined also advantageous through the use of so-called binary rate multipliers take place, those in the Handbook of Automation, Computation and Control, Volume 2, by Thompson Ramo Wooldridge Inc., Verlag John Wiley & Sons, Inc., New York in detail on pages 28-11 to 28-15 and 29-05 to 29-14, consider namely, the block diagram shown in the above publication on pages 29-06 (Fig. 1), it can be seen that the so-called binary rate multiplier shown is particularly suitable for directly obtaining the product (WD. K) according to equation (2) and in one not shown in the cited figure and used as a memory Counter, the input of which is to be connected to the output of the shown OR gate, save. In this case, WD would be represented by the pulse train shown in the measuring circuit already described above (FIG. 2) the AND gate 14 during a counting period of the counter Z1 happens, the value shown in Fig. 1 of the cited publication the so-called multiplier was represented by the given (and thus permanently storable) K.

The multiplier input would be entered into another so-called binary rate multiplier (a1 to a) can be represented by e.g.

the counter 18 (Z2) of the Neßstufe described above, so could after Termination of a counting period of the counter 18 as a (hitherto unknown) so-called Multiplicand counting pulses I are used and counted for as long (e.g. in the C2 register), up to the sum of the impulses output by the Oder gate of the cited publication at least approximately the same as those determined with the other binary rate multiplier Product (WD.K) is. Then the counted counting pulses I represent the one sought Phase difference.

Instead of this method, however, a combination, for example, can also be used of the so-called divider method, the block diagram of which (FIG. 7) is based on the quoted Page 29-11, with the so-called (binary) rate multiplier method be used.

So you can see that in addition to the well-known fully automatic computing means even the less known ones can be used very advantageously.

Claims (1)

P a t e n t a n s p r ü c h Digital phase meter, characterized in that the sinusoidal Measurement signal SM and from the sinusoidal reference signal SB with means known per se first time stamps ZM and ZB are derived, which in the case of both signals the temporal occurrence of the same phase mark that to gain a measure the length of the period of the reference signal Sg and / or the measurement signal SM the period TB des marked by two successive time stamps ZB Reference signal SB and / or marked by two successive time stamps ZM Period TM of the measurement signal SM with pulses I which are at least approximately constant Have pulse repetition frequency fI, counted and thereby the count value in the former case WB and in the latter case the count WM obtained and displayed and / or output where WB = TB.fI = WM = TM that is used to obtain a measure of the phase difference the time interval between the reference signal 5B and the measurement signal SW TBM, that begins with the temporal occurrence of a time stamp ZB and with the temporal one Occurrence of the time stamp ZM immediately following this time stamp TB ends, with pulses I, which determine the at least approximately constant pulse repetition frequency fI, counted and thereby the count value WBM obtained, displayed and / or output and / or that to obtain a measure of the phase difference between the measurement signal SM and the reference signal SB that time interval TMB that begins with the line occurrence a time stamp ZM begins and with the temporal occurrence of this time stamp ZM immediately following time stamp ZB ends with pulses I that at least have approximately constant pulse repetition frequency fI, counted and thereby the Count WMB won, displayed and / or output that to obtain the Phase difference then one of the count values WMB with per se known computing means or WMB is divided by one of the count values WB or WM and the one obtained thereby Result is multiplied by one of the values 360 °, 2 # or k, and the result this multiplication is displayed and / or output (please note that that depending on the values used, the result is either in grams, radians or is obtained to an extent determined by k and either the real phase difference or the difference between 360 °, 2 # or k and the real one Represents phase difference) that in the case of the simultaneous occurrence of the time stamps ZW and Zg no pulse counts and no calculations are carried out, but the value zero is preferably displayed and / or as a result of the phase difference measurement is issued.