DE1814677A1 - Arrangement for secure data transmission - Google Patents

Description

Telefunken patent collecting company with limited liability

Ulm / Donnu, Elisabethenstrasse 3

Constance, December 13th, 1968 Rl / Ro

Arrangement for secure data transmission

The invention relates to an arrangement for secure transmission binary coded data in which the data supplied by a data source is cyclically transferred to a memory with a A plurality of separately controllable memory cells are stored and read cyclically from the memory and to one remote recipients are sent, and in the case of a data retransmission a renewed readout of already sent Data is taken from memory. Such an arrangement is known from DAS 1 202 311. Is with one of these Arrange the source, e.g. a punched tape reader with a maximum reading speed of 300 characters per second and is <the transmission speed by the properties of the The transmitter or the transmission channel is limited to a lower transmission speed, the problem arises the higher speed of the source to the lower speed of the transmitter. When using the arrangement mentioned at the beginning, the punch reader would through frequent Starting and stopping (before or after filling each memory cell) mechanically heavily stressed. Another possibility

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would be to use a paper tape reader whose reading speed is changeable. Such a tape reader but is very complex.

A similar problem of adjusting different speeds of source and transmitter results when the source works slower than the transmitter and it the aim is to ensure that the transmitter works with relatively few interruptions over a long period of time. The invention solves the problem in a simple manner by allowing the memory to be used at the same time to be used as a buffer for speed adjustment . The invention is that a random access memory is used; that the outcome of the Memory is connected to the input of a transmitter; that a control device is provided with the cyclic storage and the cyclic non-destructive read-out effecting switching means, the data source and the Transmitter is connected and controls some or all of these facilities so that when the data source works slower than the transmitter, uei Deginn one Data transfer first the memory is filled and, as soon as the memory is almost full, with the readout and sending is started and cyclic writing is continued, and that when the Data source works faster than the transmitter, at the beginning . a data transmission, the reading out and sending is started immediately after the start of storage; and that

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the steering device repeats an error in the event of an error Triggering and sending of already sent data, starting with the memory cell, the content of which is considered to be faulty was reported received.

According to a further development of the invention, the same memory is also used in systems that work in duplex mode used for intermediate storage required between reception and forwarding to the data sink.

The invention is explained below in an example with reference to the drawings. Show it

1 shows an arrangement according to the invention,

2, 3 and k show the time course of writing and reading from the memory in different operating states.

In FIG. 1, a source 1 is connected to an input of a core memory 2 via a shift register 1 'serving for parallel-series conversion, and the input of a transmitter 3 is connected to an output of the memory. The output of the transmitter 3 h via a Sendekannl connected to an unillustrated remote receiver. The * core memory 2 consists of a level with Gh rows and 16 columns. The content of a column corresponds to a data block. Various functions are used to control the memory, which is only indicated schematically

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Counters, each corresponding to its position Control the cores of the memory for the purpose of storing or reading out »These are a first reading counter for reading out 5 »which controls the respective column and thus the data block, and a second read counter 6 which controls the controls the respective line of the memory and thus the individual bit of a data block. Serves in an analogous manner for storing a first memory counter 7 and a second memory counter 8. The remote receiver determines whether it has received the information sent without errors has received and gives via an acknowledgment channel 9 fin an acknowledgment receiver 10 acknowledgment signals or false signals for each correctly or incorrectly received data block. The acknowledgment receiver 10 feeds an acknowledgment counter 11, which is connected to a delay counter 12 is. The. Delay counter 12 rushes the receipt counter 11 always in a certain number of steps, e.g. three, after. All counters as well as source 1, shift register 1 'and Transmitters 3 are connected to a control device 13. The elements 11 to 19 in Figure 1 will be explained later.

Let us first consider the case that the source 1 works faster than the transmitter 3. At the beginning of a transmission, the control device 13 sets all counters 5 to 8 to 1 and 11 to 0 and 12 to 0-3 = 13 and starts source 1 (Counter 12 counts modulo 16). The source is 7. Vi. a punched tape reader, which transfers the character read in parallel into the shift register 1 ', through the

31/68-KN 009826/1043 _{/ 5}

a parallel-serial conversion is carried out and a very rapid insertion of the character in the memory is made possible. The first bit of the memory is stored according to the position of the memory counters 7 and 8 in S] iaite 1 and line 1, the second bit in column 1, line 2, etc. When the source 1 transfers the next character to the shift register 1 ', the previous content of register 1 'is already shifted into memory 2 as a result of the high storage speed. When column 1 of the memory is full, the control device switches the first memory counter 7, which counts modulo 16, to one another and the second memory counter P), which counts modulo Gh , is switched back to 1 Writing into the memory controlled by the memory counters 7 and 8 takes place in such a way that information originating from earlier writing processes is overwritten.

The stored bits are read out and fed to the transmitter 3 in an analogous manner under the control of the read counters 5 and 6, which, like the memory counters and 8, count modulo 16 or modulo Gk , which enables cyclical reading. In the operating state discussed here, that the source 1 works faster than the transmitter 3, the first bit of the first character is expediently read out as soon as possible after it has been stored. The nus-read bit is fed to the special 3, which converts it into a form that is due for transmission

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converts and at the same time in a known manner In addition to redundancy, the verifiability of emitted Bi τ allows the remote receiver to follow. Reading out dor information from the memory 2 should be non-destructive in order to avoid an error in the data transmission to allow repetition; each time a bit has been read out from memory 2, it is therefore rewritten necessary. The person skilled in the art is familiar with the measures and facilities required for this and therefore not shown. Since the memory 2 also works much faster than the transmitter, one is temporal nested cooperation of memory 2 and source 1. on the one hand and memory 2 and transmitter 3 on the other possible. This is controlled by the control device 13.

In the following, the mutual dependency is shown with reference to FIG of writing and reading out of the memory explained; the temporal nesting of the two processes is not apparent from, Figure 2. The time axis of the diagram is carried horizontally and vertically the 102'i memory locations of the core memory 2 are plotted, namely, the direction from bottom to top corresponds to the sequence of the storage locations when writing or read out. The writing is represented by a solid line, the reading out by a dashed line. At time 0, writing is started at address 1. A kxirzo time later that will

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Reading started at address 1. At time a, all storage locations are filled by writing and es rewriting begins at address 1 with deletion of the previous content, since the lower addresses are already have been read for a long time and are no longer required for a repetition. At time b is the whole content written into the memory is read out on the first pass, and further reading starts again at address 1. At time c, the memory is filled for the second time. At time d, the registered mail stopped, because storage locations were overwritten with further writing, their contents with a possible data repetition would be required for repeated transmission. The registered mail will only start again at time e, in which almost all of the information previously written has been read out. At time f occurs because of an error in the data transmission a data repetition. This is done by jumping back to lower addresses when reading out.

The processes just described at times d, e and f run under control by the control device 13 » the Qxxitturtgszähler 11, the delay counter 12 and the " first read counter 5, as will be explained below. The acknowledgment signals or false signals sent by the remote receiver are transmitted by the acknowledgment receiver 10 receive. The acknowledgment signals for correct reception are forwarded to the acknowledgment counter 11, its

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iejiigjaru- & eeteiibi-orclc in memory ¹ I. -

Receipt was last reported as correct by the remote recipient. WircTTiem "acknowledgment receiver IO a signal that reports an incorrect reception of a data block. So the acknowledgment receiver sends a signal to the control device 13. The control device 13 stops the transmission after the complete transmission of the data block currently being transmitted by the control device 13, the status of the acknowledgment counter 11 is transferred to the first read counter 5, increased by one and the data block already read out and the subsequent data blocks are read out again Errors, the delay counter 12, whose count always lags the acknowledgment counter 11 by three units, enables data blocks that have already been correctly received to be sent again to increase the security of the data repetition 2 in the first read counter 5 ^ur * d starts the data repetition.

The areas required for a possible data repetition of memory 2 must not be overwritten when writing. This is ensured by the fact that the control device 13 the status of the memory counters 7 and 8 and

f. -

of the delay counter 12 compares and the registered mail

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then interrupts when that data block is in the Memory 2 is written in immediately before that block whose number is in the delay counter 12 Standing lying. In Figure 2 corresponds to the vertical distance of the two lines for writing and reading at time d, at which the writing is stopped, this area required for any data recovery. Registration is stopped at the end of a block, and started when the first bit of the relevant block is sent. This gives you a buffer time (Transmission time for a block) to start the Source. Even greater delay times of the source are also taken into account by the control device.

In FIG. 2, writing is started again at time e.

FIG. 3 shows how the control device 13 is used for writing and reading purposes controls when the data source works slower than the transmitter, and the transmitter with as few interruptions as possible should work. First, the memory 2 is through Registered mail filled as far as possible before reading and sending started. After the memory is currently

nearly
point h / filled *, reading begins and. starting at address 1, the writing to the memory is continued. At time i, the readout process has reached the last written information, which the

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13 by comparing the status of the counters 5, 6 ₉ 7 "" S, and reading is stopped. At time j there are three whole data blocks between the write-in address and Ämsieseadaresse, and reading out begins again. A batem repeat takes place at time k.

With the arrangement shown in FIG. 1, data can also be stored at the remote receiver. Transmitter are sent, which works with the shown Äaaordnraag in duplex, on the way from a nationally provided receiver 1 * j to a data station 15 are buffered. For this purpose, two further storage counters 16 and 17 as well as further reading counters 1S and 19 are provided which, like the receiver 1'1 and data recorder 15 ', are connected to the control device 13. The counters Ί6 Isis 19 control, in the same way as the counters 5 Isis S, the writing and reading of intermediary sponsors. For the intermediate storage of the receptive Bajceia, the memory 2 is expediently subdivided so that some memory columns can only be controlled by the counters 19 and the rest of the memory can only be controlled by von.- deaa Zülilem 5 to 8. The storage and readout of the data being sent and the data received are stamped interleaved in time by the control device 1).

Using the Fijgiar 4 -will now show the interdependence

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of! store and read out when temporarily storing the received data. A prerequisite here is that the data sink can receive data more quickly than the receiver 1'i delivers. The opposite case, that the receiver 1 k delivers the data faster than it can receive the sink 15, is not considered here, since continuous data transmission is not possible in this case.

The writing begins at time 0 at address 1.

nearly
At time 1, the memory / is full, and read-out begins at address 1. At time η, the control device stops reading because the receiver 1 '| has found that the data block received at the beginning of time m contains an error. The control device now also stops writing and only starts writing again (time p) when correct data blocks are received. The incorrectly received block is overwritten. At time q, the memory is filled again with correctly received blocks and reading is started again.

The required size of the memory 2 depends on how much data are to be delivered or received by the fast source in the case of FIG. 2 or by the fast transmitter or the fast data sink in FIGS. 3 and k without interruption; secondly, the size of the memory 2 depends on the speed difference between source 1 and transmitter 3 or receiver 1 '| and data sink 15 dependent: With a small speed difference

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allows a certain memory size, a longer uninterrupted one Operation than at a greater speed difference.

To set up a control device which works in the manner described does not present any difficulties for the person skilled in the art. Switching of the operating mode of the control device, which may be required by changing the data source can either be done manually or automatically based on a detection of the speed of the data source.

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Claims (1)

Claims 1. Arrangement for the secure transmission of binary-coded data, in which the data supplied by a data source are cyclically stored in a memory with a plurality of separately controllable memory cells and read out cyclically from the memory and sent to a remote receiver, and in the case of a Data retransmission data that have already been sent are read out again from the memory, characterized in that a memory (2) with random access is used; that the output of the memory is connected to the input of a transmitter (3); that a control device (13) is provided, which is connected to the switching means (5 »6, 7» 8) i of the data source (1) and the transmitter that effect the cyclical storage and the cyclical non-destructive readout and controls individual or all of these devices in such a way that that when the data source works slower than the transmitter, at the beginning of a data transmission, the memory is first filled and, as soon as the memory is almost full, reading and sending are started and the cyclical writing is continued, and then, if the data source works faster than the transmitter, at the beginning of a data transmission reading and sending is started immediately after the start of storing »; and that the control device in the event of an error a ' 1Q43 '6AD OßJÖJNAL Repeated reading and sending of already sent dots, starting with the memory cell, its content was reported as received incorrectly. 2. Arrangement according to claim 1, characterized in that that the control device (13) when the source (l) works faster than the transmitter (3), when a broadcast is deginned, the source and transmitter start almost simultaneously, and the source stops immediately before it was previously stored that was reported to have not been received correctly Data overwrites that the control device starts the source again about when the transmitter last has sent stored data that the control device will read out again in the event of an error and sending data that has already been sent. 3. Arrangement according to claim 1, characterized in that the control device (13) when the source (l) works slower than the transmitter (3), when deginned a broadcast, the source starts first, and then starts the transmitter when the Memory (2) is almost full, but in any case in good time so that data required for a possible repetition at the time the memory is completely filled have not yet been overwritten, so that the control device stops the transmitter approximately when it receives the last written data 'has sent, and the transmitter starts again about when the source olle previously saved times to 31/68-CN 009 * _26/1043/15. ■ i ■■ .- '■ j ^; SAD ORIGINAL on one needed for a possible repetition Remainder has overwritten that the control device in In the event of an error, read out and send again already sent data. ¹ I. Arrangement according to one or more of the preceding claims, characterized in that the memory (2) is a core memory with a level with m columns, which form the memory cells, and η rows, that the switching means is a first read counter (5) and a first memory counter (7), which both count modulo m, and a second read counter (6) and a second memory counter (8), both of which count modulo η, which are set and advanced by the control device (13). 5. Arrangement according to claim 1 and k, characterized in that a receipt receiver (lO) and a receipt counter (ll) which counts modulo m, are provided, which are connected to the control device (13) that the remote receiver to the receipt receiver Messages about the correct or incorrect reception of each data block forming the content of a Speiclifirzel] ο provides, ünl '> dor security receiver with every message for correct chin catch <ien Qui. 1. i unjrsziihler to "the toilet i terschal t ei,?; ο dal '· .Stand which always corresponds to that of the memory cell whose' content received correctly get as.-.- · Μο1 zuleizi was dal '· represents C _(u i ι i ungsemnf änjrer in. a I · mi.! ¹ for (' ¹ IiI ei Itafi.eii receiving a Si irma 1 to the η p 2 8 7 B / 1 O 4 3 BAD ORIGINAL Control device, which then sends a data retransmission, starting with the memory cell, the content of which is reported as received incorrectly caused that at the beginning of a transmission, the control device the first and second memory counter sets to one and the receipt counter to st e1It. 6. Arrangement according to claim 5 « characterized in that a delay counter (12) is provided which is connected to the control device (13) and to the receipt counter (11), and the status of which is always the status of the receipt counter by a certain number of steps lags behind that, in order to increase the security in the event of a data retransmission, the control device (13) transfers the status of the delay counter to the first read counter (5). 7. Arrangement according to claim 1, characterized in that during the transmission in duplex mode, in which a further transmitter is provided at the location of the remote receiver, which sends data to a further receiver (lh) provided at the location of the transmitter (3), from where they are forwarded to a data sink (15) whose operating speed is greater than the speed of the received data, the memory (L!) is divided into two areas, one of which is only through the switching means (5 »6» 7i ö) is controllable; 31/68-KN 00 9826 / 10-4 3 ^ _, / ₁₇ Further switching means (1.6, 17, 18, 19) are provided through which only the other area can be controlled, and which cyclically write the received • Allow data and cyclical readout; and that the control device (13) with the further receiver (l'i), the data sink (15) and the further switching means is connected and the data sink and the writing and reading controls so that at the beginning of a reception a data transmission is first written in and reading is only started when the other area is almost full that data received again without interruption in the memory cells that have been read out are written in, and that the read-out is only stopped when the last or almost last written Data are read out. 8. Arrangement according to one or more of the preceding claims, characterized in that storing and reading out of both the transmitted data and, if necessary, the received data are interleaved in time. 9. Arrangement according to one or more of the preceding claims, characterized in that delays in starting and stopping the data source (l) or data sink (15) due to inertia are taken into account by the control device (13). BATH ORIGINAL 31/68-KN 00 98 26/1043