DE1810810A1 - Code reading and control circuitry - Google Patents

Description

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Code reading and control circuitry

The invention "relates generally to a circuit arrangement for reading a Codes and for controlling movements in accordance with the code read and in particular a switching arrangement of this type for a system for sorting packages or objects.

The invention provides a switching arrangement for sorting packages in front of the identification mark on the package of the label as a desired label and initiate the generation of synchronizing clock pulses.

Furthermore, in the switching arrangement according to the invention, clock pulse marks applied to the pack determine the reading time and the duration for reading the identification code on the package, being light-sensitive Facilities are preset in such a way that they perceive whether the clock pulse marks are the desired rakes. '

The inventive arrangement of the identifier, which at the same time initiate the generation of clock pulses, the sorting process regardless of the speed of a front on which the object or the pack is conveyed forward

A further object of the invention is to provide a switching arrangement of mentioned type of creating the malfunctions and incorrect readings due to dirt or black? read marks or misalignment of the label.

According to the invention of a switching arrangement for reading a Codes and for the corresponding control of sorting the objects !! elements first made an identification of the label, to prevent malfunctions; this happens before the destination code marks can be read to improve sorting accuracy.

Further objects and advantages of the invention will become apparent from the following Description based on the accompanying drawings. The painting represent:

Pig. 1 is a schematic front view of a coded label such as it is read by the switching arrangement according to the invention;

2A and 2B, placed next to one another, show a circuit arrangement according to the invention for reading and controlling a code as a block diagram a label according to the type of § shown in Fig. 1

3A and 3B, placed side by side, show a circuit diagram of an identification circuit, which is part of the switching arrangement according to the invention;

4 shows a circuit diagram of the code reading and counting circuit * the cable of the switching arrangement according to the invention is ι

5 shows a circuit diagram of a test circuit for the mark spacing and the mark width, which is part of the switching arrangement according to the invention;

Fig. | Üi-60 assembled in the manner shown in Fig. 7 a Debugging and correcting circuitry as part of the invention Switching arrangement g "■." "■ ■

Fig. 8 is a block diagram of the memory circuit for iie invention® «= appropriate switching arrangement »-

Course ssusanmisngefasst'works the inventive Schaitanosdnttng * _s ' - by reading the eti & ett & eanung-reading with the help of your reading part - it is first of all fixed j »oTb the scanned label is aiaöa B © gtiimeiigee®: ä © © -during

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'i'aktimpulszeitspanne scans, which from the clock pulse marks on the Label is initiated. Preset groups of photosensitive devices in the reading part do not only read the characters the label, but perceive the width of the clock pulse marks as well as the space between successive clock pulse marks, to ensure that the correct clock pulse marks control the sampling time for determining the code characters.

In Fig. 1, a label L is shown, which is labeled by a conventional labeling machine or a computer printer and is attached to a specific point on a package of goods. In the following we speak of a package, but it can just as easily be an object. The label L contains an identification zone, which comprises three leading vertical marks or characters Ay-A-, the marks A, and A ₂ are parallel to each other and are spaced in the direction of travel of the label A, while the mark A, under the marks A, and Ap is arranged. The mark A is also vertical and is aligned under the space between the marks Αη and A ₂ . As can be seen from Fig. 2A, the label is attached to a package which is moving in the direction of an arrow. Zone A is therefore the leading end of label L.

In the rear area of the label L, namely in its upper rope, a number of clock pulse marks Cy-O ^ Q are provided. In the picture example there are ten. The clock pulse marks Cy-G-iQ are also vertical and are in the direction of movement of the label arranged at intervals one after the other. Below the tick pulse marks is in the rear part of the label the identification code I for identification the destination or distribution area for the package bearing the label. The destination code includes in the example five vertical parallel marks I, -Ic · You can see » that the marks Iy-Ic are vertically aligned with certain clock pulse marks and are at a distance from one another in the direction of movement of the label. Marks are therefore present at the In-Ic points, whereas one A gap under a tactical mark indicates that a mark is missing. Both the presence and the absence of a mark can be used to identify the identification code I.

The marks Aj-A determine whether the label 1 should be read at all. The series of brands O ₁ -O ₁₀ initiate the generation of clock pulses and the brands Ι-ι-Ις identify the destination or the diversion zone for the pack carrying the label.

In a goods sorting system, a switching arrangement 15 (Fig. 2) is provided for scanning the Oodes and for controlling the labels, for example the label L, reading and sorting the packs, which labels carry, controls by the fact that it diverts the packs at certain sorting stations.

Packs with labels L come from a storage area of a goods » house and are delivered to an endless sorting conveyor with the help of various feeder conveyors. Are along the sorting conveyor some sorting stations with their own ejection mechanisms or deflectors arranged. The packs on the endless sorting conveyor are selectively placed in conveyor troughs or delivery conveyors at the selected sorting station diverted, which load the packages into certain trucks; a sorting system of this type is more precisely described in US patent specification 3,379,321 issued April 24, 1968. The patentee is the assignee of the present invention.

2A shows a pack P bearing a label 1. The pack P runs forwards in the direction of the arrow 10. The switching arrangement 15 according to the invention (FIGS. 2A and 2B) contains a reading part 16,. of the three groups of conventional light-sensitive devices, for example phototransistors 16A, 16B and 160, comprises "The phototransistors 16B are arranged vertically one above the other and do not quite reach the height of the marks A ₁ , A ₉ and C -, - C _1n . Since they are approximately the same

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Highly attached and ₉ ν like the aforementioned brands, they face them while the label L moves in the direction of the arrow 10.

Correspondingly, the phototransistors 161 are also arranged vertically and at the same height as the bototrane transistors 16B. They are aligned with the phototransistors 16B in the direction of continuous movement of the label L. Furthermore , the IMf © transistors 16B and 16A have a w ^ given distance B from each other and

this distance S is smaller than the width of the marks Α, -Α ,, but larger than the width of the individual jyjarken A ₁ -A-, but larger than the width of the individual marks C ₁ -On ₀ *

The phototransistors 160 are also arranged vertically and their height is less than the height of the marks A and I _n Ir ·. In addition, the phototransistors 160 are vertically aligned with the phototransistors 16A and are approximately at the same height as the marks A and I ₁ -IcI so that they come to lie opposite these marks when the label L moves in the direction of arrow 10.

The construction and operation of the reading part 16 are the same except the location and configuration of the phototransistors 16A-160 that described in the above-mentioned patent. Not shown Lamps illuminate the label L as it passes through the reading part 16.

At the output of the phototransistors 16A-160 are conventional gate circuits 2OA - 200 connected. If two or more of the phototransistors 16J3 change their conduction state, then that changes logical output of the gate circuit 2OB. The same applies to the phototransistors 16A and the gate circuit 2OA, as well as to the Phototransistors 160 and the gate circuit 200,

Connected to the circuits 20A -200 via lines 26A -260 is a detector 25 for recognizing the label, which detector 25 will be described in detail later. At the output of the detector 25 there is a rejection conductor 27, which is led to a conventional OR gate, as well as an acceptance conductor 31, also connected to an Oodelese- and clock counting circuit 35 and also to a detector 40 for the mark in between. The detector 25 determines in a manner still to be described whether the label L is a desired label for the switching arrangement 15.

If the imprint of the label Ii is so applied that the marks C ₁ -G ₁₀ for the synchronization pulses are so close to the marks A ₁ -A for detection that the phototransistors 16B and 16A do not have a gap between these marks A ₁ - A ₂ and O ₁ -Ci ₁₀ can determine more, a rejection signal is given via the conductor 27.

This reduces the risk of reading the wrong code. If the label L is tilted too far, a rejection signal is also given sent through the conductor 27. If, however, the label L is a proper label, an acceptance signal is sent over the conductor 31 given that the Oodelese- and clock counting circuit 35 and the Detector 40 is entered. The reading and clock counting circuit 35 is connected to the reading part 16 via the gate circuits 20A-200.

The odeleading and clock counting circuit 35, which will be described in more detail later, permits the reading of the determination _{code I 1} -Ic only in the period after the label L has been _{identified as correct by the marks A 1} -A and during the phototransistors 16B and 16A read a clock mark. In order to ensure that the scanning of the destination codes takes place during the clock pulse duration and that valid Synchronisierungsimpulsamarken be read 35, the clock pulses allows the circuit to count only when the phototransistors 16A detect the absence of a clock pulse brand währendjdie phototransistors 16J3 the presence of such a mark perceive _β The determination _{code I 1} -Ic iß in the form of binary bits is transmitted from the code reading and clock counting circuit 35 serially via a conductor 41 to a troubleshooting and correction circuit 45.

At the output of the reading part 16 there is a test circuit 40 for the mark spacing via lines 26A, 26B and 260, which will be explained in more detail later. This checking circuit 40 determines whether the clock pulse marks are the desired marks. For this purpose the distance is to the Breitejdep to check between the phototransistors 16B and 16A vorgesgeb6ü ₉ clock pulse marks and their distance from each other. " If you perceive groups of the phototransistors 16B and 16A at the same time clock pulse marks, then the test circuit 40 sends a rejection signal for 'the mark spacing over a conductor 46 to the OR, element 30. The test consists in determining whether or not the wanted one The clock pulse mark is wider than the distance S between the phototransistors 16B and 16A and furthermore whether the space between successive clock pulse marks is smaller than this distance S _{0 A} mark with a width greater than the permitted maximum and / or a smaller distance between successive marks, than corresponds to the permitted minimum distance, causes a Eekwelsunga signal in the conductor 46.

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The test circuit 40 also carries out yet another test, namely whether the distance between successive clock pulse marks is greater than an allowed maximum. When the phototransistors 16B and 16A simultaneously at some point during the readout detect an absence of marks, a time delay is set in motion which provides a rejection signal if at the end of the delay period the phototransistors 16A still have the absence report a trademark. If this is the case, the test circuit transmits 40 a reject signal through line 46 to the OR gate 30. At the entrance of this OR element there is also the ladder 27, via which a rejection signal generated when the label is recognized is transmitted, as well as conductor 46 through which the rejection signal from the test circuit for the mark space is sent.

A binary rejection signal in any of the three conductors 25 » 46 or 47 generates a read prohibition signal at the output of the OR gate 30, which is input to a memory 50 via a conductor 51. However, if a read signal arrives through conductor 47 and no reject signals Are sent through the conductors 25 and 46, a read signal is generated at the output of the OR gate 30, which is in the Spei cher 50 is entered. When the memory 50 receives the read signal, he takes the identification code in the form of bits of a binary code from the troubleshooting and correction circuit in reception via conductor 60-69. -

The memory 50, which is described in more detail below, controls the activity of mechanical switches or deflectors at the sorting stations in order to sort the packs. The packs will be selected in conveyor troughs and on conveyors to be delivered to the corresponding trucks.

Label recognition implementation

As already mentioned, there are only binary outputs of the gate circuits 20A-20G via conductors 26A-26C to detector 25 for detection of the label. The circuit of this detector is shown in Figures 3A and 3B. The gate circuit 20A receives the signals of the landmarks from the phototransistors 16A and the gate switch.

device 2OB from phototransistors 16B, likewise receives the gate circuit 2OC the signals of the identification tags from the phototransistors 160.

The detector circuit 25 includes identification circuits 75 »76 and 77, the binary signals over the lines 26A and 26B and 260 received by gate circuits 20A, 20B and 200.

The identification circuit 76 has a customary AND gate 78, 'its Output to two conventional flip-flop circuits 81 and 82 is. An inverter 84 connects the output of AND gate 78 with the Input of the flip-flop circuit 82. The identification circuit 75 has a conventional AND element 85, the output of which is connected to two usualaa flip-flop circuits 86 and 87 are connected, with between an inverter 88 is connected to the AND gate 85 and the flip-flop circuit 86. In the same way, the identification circuit 77 has a conventional AND element 89, the output of which is connected to flip-flop circuits 90 and 91, between the AND gate 89 and the flip-flop circuit

90 an inverter 92 is inserted.

When the phototransistors 16A, 16B and 160 make the transition from a gap or detect the absence of a mark for an identification mark, the binary outputs of the gate circuits 2OA, 2OB, 2OC change and thus cause a change in the logical output of the AND gates 78, 85, 89. This process leaves the flip-flops 87, 89,

91 change your line mode. When the phototransistors 16A, 16B and 160 the transition from mark to gap or absence perceive a mark, the binary output of the gate circuits 2OA, 2OB and 200 causes the binary. OUTPUTS of the AND gates 85, 78, 89 to change the conduction state of the flip-flop circuits 86 or 82 or 90.

However, before the AND gates 78, 85, 89 change their binary outputs, they have to. "set" (enabled). This is done by a "setting signal" (enabling signal), which is sent by a light-sensitive Device, for example a photocell 80 (Fig. 2A) via a conductor 81 is applied. The photocell 80 is on the path of the pack P

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appropriate. A light source, not shown, throws a constant beam of light q.uer over the path of the pack P onto the photocell 80. When the leading edge of the pack P interrupts the light beam, the photocell 80 changes its conduction state and then remains in that changed state until the rear edge of the package P has passed the photocell so that the light beam is no longer interrupted is.

Before the label is recognized, the light beam is interrupted for photo cell 80 through the front edge of pack P all flip-flops reset. When the on the photocell 80 falling light beam is interrupted by the front edge of the package, the photocell changes its line status and sends a set signal through conductor 81. As a result, a common OR gate 95 changes its binary output and thus causes a monostable multivibrator 96 to change its state. Of the Multivibrator 96 generates a reset pulse that affects all flip-plop circuits of the detector 25 with the exception of a conventional output flip-flop 97 resets.

The output flip-flop 97 is determined by the monostable multivibrator 96 via conventional jerk set-AND gates 98 and 99 reset ·., The binary output changes in either the AND gate 98 or the AND gate 99, a change usual OR gate 100 its output. This change generates a reset pulse for the output flip-flop 97.

All of the flip-flop circuits of the detector 25 for the detection of the tag are reset when the phototransistors 16A make a second transition from an identification tag to a void or absence detect a mark without the phototransistors 16B also reporting such a transition from a mark to a gap. this happens to reduce the risk of having a number of narrow Marks is read as an identification code.

A conventional Rüokeetz UITD element 101 is provided for this purpose, that has four entrances. TJm the binary output of this AND element 101 To change, the mode of a conventional flip-flop S © must first be used

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can be changed, which is done by changing the binary output of a conventional AND gate 103. How this occurs will be described in detail later. W _e nn the phototransistors 16B read no identification mark or if they perceive a Eennungsmarke for the first time, one of the inputs of the gate MD] O1 of the binary output of the flip-flop circuit 84 is set via a conductor 102nd An input is also set at the AND element 103 by the flip-flop circuit 84 which changes the conduction mode. A second input of the AND element 103 was already initially set by the flip-flop circuit 91 via the conductor 111, as described above.

Once the phototransistors 16A make the second transition from a landmark to detect a gap or missing mark, the flip-flop circuit gives 87 a binary output, which sets the AND gate 101 via lines 104 and 105. At the same time, the flip-flop circuit generates 86 a binary output to the AND gate 101 via lines 106 and 107 to set. In addition, the flip-flop circuit 87 has already set the AND element 103 via a conductor 109 with its binary output. The last input of the AND gate 101 is from a conventional flip-flop 110 set.

The mode of the flip-flop circuit 110 is from the binary output of the AND gate 103 controlled. At this point, two of the three entrances are of AND gate 103 is set. When the phototransistors 16C begin to read a gap or a lack of the identification mark, a set signal is sent from the flip-flop circuit 91 through lines 111 and 112 to the AND gate 103.

Now the AND gate 103 changes its output and thus causes the Switching the mode of the flip-flop circuit 110. The AND gate 101 was triggered when the flip-flop circuit 86 changed state. Then the OR gate 95 causes the multivibrator 96, a Generate reset pulse in the manner described above.

When the phototransistors 16A make a second transition from a gap to perceive an identification mark without also affecting the phototransistors 160 read a single transition, all flip-flop circuits of the detector are reset for the recognition of the label. This pro--

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gang causes a conventional reset AND gate 115 with three inputs.

As the phototransistors 16A make a second transition from a gap became an identification mark, became an input of the MD link 115 set by flip-flop circuit 86 via lines 116 and 117; the flip-flop circuit 87 set a second input of the AND gate 115 via conductors 104 and 105. During the period in which the phototransistors 160 a gap or the lack of an identification mark read and before a transition from this gap to an identification mark takes place, the flip-flop circuit 91 sets the last one Input of the AND gate 115 via the conductors 111 and 112 and a conductor 118. The AND element 115 now changes its binary output, whereby the binary output of the OR gate 95 also changes. This action causes the multivibrator 96 to apply a reset pulse generate, and the flip-flop circuits of the detector 25 are in the reset as described »

All of the flip-flop circuits of the detector 25 are reset when the Phototransistors detect a second transition from a landmark to a gap while phototransistors 160 detect a landmark read »A common reset AND gate is used for this purpose 120 with four entrances. This arrangement is intended to make the flip-flop circuits of the detector 25, if not the desired one Identification code is read.

When the phototransistors 16A make the second transition from black z.u white perceive, an input of the AND gate 115 from the binary The output of the flip-flop circuit 87 via the lines 104 and 105 is set. A second input of the UTTD gate 115 is from the binary The output of the flip-flop circuit 86 is set via a conductor 121. The flip-flop circuit 90 sets one with its logic output further input of the UHD-GIiedes 120 via a conductor 122 until the Phototransistors 16C transition from mark to space determine. The last input of the AND gate 120 is from the logical output of the flip-flop circuit 91 is set via conductors 123 and 124 when the phototransistors 160 for the first time an identification mark read.

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The üiTD element 120 changes its binary output in order, as mentioned, to cause the OR element 95 to operate the multivibrator 96. Thereupon the multivibrator 96 generates a reset pulse which the flip-flop switching of the detector 25 in the above-described! Way resets.

In the exemplary embodiment of the invention, there must be an acceptance signal is sent from dem.setzenden output flip-flop 97 through the conductor 31 to the code reading and clock pulse counting circuit 35, the following Conditions exist in the correct order;

1) phototransistors 16A read an identification mark; the phototransistor 162 and the phototransistors 16C do not read an identification mark.

2) The phototransistors 1633 and 160 read an identification mark for the first time and the phototransistors 16A make their first transition from an identification mark to a gap.

3) The phototransistors 16A read the second identification mark while the phototransistors 16B a gap after reading an identification mark and the phototransistors 160 make their first transition from a landmark to a gap.

4) The phototransistors 16B read their second tag while the phototransistors 160 perceive a gap and the phototransistors 16A make their second transition from a landmark to a void.

When the phototransistors 16A read an identification mark, the logic output of the flip-flop circuit 87 sets an input of the AND gate 103 via the conductor 108. While the phototransistors 16B detect a gap or the absence a: identification mark, the flip-flop sets Circuit 82 with its binary output a further input of the AND element 103. The last input of the AND element 103 is set by the logic output of the flip-flop circuit 91 via the conductors 112 and 113. This happens when the phototransistors 160 read a gap.

After the above conditions are met , the logic output of the AND gate 103 changes and causes the flip-flop circuit ll

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changes their state. This change of state becomes an input a common IMD link 125 set "

At this time have the phototransistors 16B is a Eennuagsmar "ke read so represent logical outcome of Plip-lFlop circuit 84 via a conductor 126 a sweiten input of the MD-G, song .125 sets * '■' ■ W _e nn the Phototranaistoren 160 perceive an identification mark, a third input of the UlSiD-G-Iiedes 125 is set from the binary output of the S ¹ Up-Plop circuit 91 via lines 123 and 124. When the phototransistors 16A perform their first transition from a Kennungsmarka a gap from the last input of the AND GlJsdes 126 is set "This is done using DES logical output dsr 3? Lipllop-Scnaltung 86, CISR as a set signal through the conductor 116 being scared.

Now ändert.das AND gate 125 bsvsrirktdamit its binary output UNAE that a conventional 3Ί1ρ-5Ίορ 130 changes its mode * When this happens, einSatssignal _β is applied to one input of a common AND gate 131

Now the phototransistors 16A read the wide identification mark. Thereupon the plip-flop circuit 87 sends a logic signal through the conductor 104 and through a conductor 132 "to set a second input of the AND gate 131 ". While the phototransistors 16A read the second identification mark, the phototransistors ΙβΒ take a gap true after they have previously read an identifier. The reason for this is that the plip-3? Lop circuit 82 sends a set signal through lines 133 and 134 to a further input of the AND element 131. When the phototransistors 160 make their first transition from an identification mark to a gap, the plip-flop circuit 90 transmits a set signal to a further input terminal of the AND gate 131 via lines 136 and 137.

As a result of this, the AND gate 131 changes its logic output and thus causes a conventional flip-Elop circuit 140 to change its line state. This process sets an input of a usual ex

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If this is imprinted on the label. S so aag © "b3? A © Iat is _s iag impulse marks. ^G 3_-ö ^ q so nafes bm ü @ m Identifisierusigsoode A that they do not get meto get2? @Aat algelesea wesäea fe6anea ₉ asS They laelEsag P are rejectediac, ä eu ύ © rMaiesa ₉ Sal © is Baer-wllBeeMes Label read w @ rd @ n 2caaa _ffl - - "..".

When reading the identification code in the manner described, the plug-in circuit 140 has changed its mode, but the OTD elements 141 and 142 have not yet changed their logical output. The package P is to be rejected if the phototransistors 160 read an identification tag _t - while neither, the phototransistors let the phototransistors 6Β perceive a gap.

ORtGINAL INSPECTED

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When this occurs, a bet signal is issued from the flip-flop through lines 151 and 152 to a standard reject AND gate 150 created. Had the flip-flop attitude 37 changed its Mcaus, then a feed signal 1 would be sent to the Rejection IßiE link placed. The flip-flop circuit 62 sends in Set signal from another input of the Rilckweisuags ^ UI-D element 150 via lines 133 and 144. The "ilip-flop" circuit also sends 86 a set signal through conductors 116 and 117 to a third input of the reject MD gate. The flip-flop circuit finally sends 87 a set signal through conductors 104 and 153 to the fourth input of reject AND gate 150.

The reject AND gate 150 changes its logic. Output and sends thereby a set signal to a common rejection AND gate 155 * The flip-flop circuit 140 should change its mode in the manner described have changed, then another input of the rejection AND gate 155 is set by conductor 142 to ensure that the state remains unambiguous. When the phototransistors 160 have a Read tag after making a transition from a tag made a gap, the flip-flop 91 transmits a set signal through the conductors 111 and 112 to the final input of the AND gate 155, and thus causes the AND gate 155 to be logical output changes.

The% change in the output of AND gate 155 causes a change of the output of a standard reject OR gate 156 *. This change in turn supplies a rejection pulse which is sent via the conductor 27 to a rejection i-OR gate 30.

If ehototransistors 160 detect a second tag to void transition before phototransistors 16B read a second void, package P must be rejected. This is intended to detect the condition that the label L is too low or has a number of spots which simulate identification marks.

For this purpose, the output of a standard AND gate 160 is for the rejection of crooked labels with an input of the OR

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ORfGfNAL INSPECTED 909834/1224

Link 156 connected. When the photo transistors 1633 a second identification mark discover, the flip-flop circuit 83 sends a set signal via the conductor 145 to an input of the MD element 160 and. the flip-flop circuit 82 sends a set signal down the conductor 133 and a conductor 161 to a second input of the AND gate 160.

When the phototransistors 160 make a second transition from a mark read to a gap, the flip-flop circuit 90 sends a set signal through the conductor 122 and a conductor 162, which sets a third input of the AND gate 160, and the flip-flop circuit 91 sends a set signal through lines 111 and 112 to a fourth input of AND gate 160.

Now the AND gate 160 changes for the rejection of crooked ones Label its binary output, which also changes the binary output of the OR gate 156 and a rejection signal through the conductor 27 is seeded to OR gate 30 (Fig. 2B) «

GodeI eBe and cycle counting holdings

The code reading and clock counting circuit 35 (FIG. 4) comprises a code memory 165 in the form of conventional shift registers 166-175 'connected in series the first Sehieberegisterstüfe 166 until the last S _c continuously connected chops register stage 175th

To ensure that the shift registers 166-175 of the code memory 165 are reset before a label L is read by the phototransistors 16A, 16B and 16C (FIG is created by the leading edge of a pack P, sent through a conductor 176 to the input side of a conventional monostable multivibrator 180. This actuates a conventional activation circuit 181. The activation circuit 181 generates a reset pulse shortly before the reading part 16 perceives the label L. The shift registers 166-175 are thus reset shortly before the start of a new reading process, so that no remainder of the count remains in the memory 165 .

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In order to shift the bit signals successively through the shift registers 166-175, the circuit 35 contains a clock pulse generator 19O ₁ which has a conventional control circuit 191. Each time the drive circuit operates, a shift pulse is sent through conductor 192, simultaneously to shift registers 166-175. This shift pulse causes each bit in the shift registers 166-175 to be switched to the next following shift register?

A conventional OR gate is connected to the input of the control circuit 191 193 connected; the OR gate 193 and the control circuit 191 cause a pulse with a positive edge for moving the bits stored in shift registers 166-175.

The OR gate 193 has two inputs. To the one input is a line 195 which leads to the output of the reading. The other input of the OR gate is connected to the output of a conventional monostable multivibrator * 195 '. A conventional AND element controls the function of a flip-flop shadow 197, which in turn controls the monstable multivibrator 195 '. The clock pulse generator for the serial shifting of the bits stored in the shift registers 166-175 includes the AND gate 196, the flip-flop holding 197, the monostable multivibrator 195%, the OR gate 193 and the control circuit 191. Every time the AND gate 196 changes to a positive pulse, the control circuit 191 generates a shift pulse which is fed to all shift registers 166-175 at the same time.

The AND gate 196 has five inputs. One entrance is through the ladder 31 connected to the detector 25 for the detection of the label. Consequently a shift pulse can only be generated after the detector 25 has determined that the label L is a usable label. Another input is to the gate circuit 2OA via the conductor 26A and an inverter 198 are connected. A third entrance is over the conductor 28B is connected to the gate circuit 2OB. The fourth The input of the AND gate 196 is connected to a counting circuit 200, in order to make the change in the line status of the AND gate 196 ineffective

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do when the count reaches ten, so that the generation of the shifting pulses for a specific label L is stopped. Finally, the last input is connected to the output of the flip-flop circuit 197 in order to block the IMD-G element 196 from generating a shift pulse as soon as the flip-flop circuit 197 has changed its state. The flip-flop circuit 197 for its part is reset ₅ after the phototransistors 161 read a mark and the phototransistors 1633 read a gap _β

The counting circuit 200 comprises four conventional flip-flops 201-204. An inverter 205 connects the multivibrator 195 "with the first flip-flop 201 of the counting circuit 200 »An input of a conventional WD element 206 is connected to the last flip-flop 204 «The other input of AND gate 206 is connected to the output of flip-flop 202 via one Conductor 208 connected. The output of the MD member 206 is via a conductor 209 and an inverter 210 on the "input side of the .MB-GIi e => - des 196 ,, The four flip-flops 201-204 are a binary counter with the AND gate 206 held together if for the "label see hook = pulses have been generated, the -AND gate 206 changes its state and thus blocks the AND element 196 via a conductor 209 «'

When the Rüeksetsimpuls generated by the control circuit 181, the shift registers 166-174 resets _s puts this same "pulse via a conductor 211 at the same time-the flip-flops 201-204 are siirüek * Consequently, the flip-flops 201-204 on accessible in a" JSuIlbestamd «This gate ensures« that there is no residue from eavesdropping or another foreign entrance Torhanfiea is ₀ "

For a better overview, the following table shows the states of the flip-flops 201-204 for each DesimaliMpulszälilung aai thus explains the function of the counting circuit 20O ₀

BATH ORIGINAL

O O O O 1 O O O O 1 O O 1 1 O O O O 1 O 1 O 1 O O 1 1 O 1 1 r-t O O O O 1 1 O O ι-! O 1 O 1

Deζima! Counting flip-flop flip-flop flip-flop flip-flop

201 202 203

The first one sent by the multivibrator 195 *, the inverter 205 Pulse changes the state of flip-flop 201 from 0 to 1. The next one Pulse causes flip-flop 201 to return to 0 and changes flip-flop 202 from 0 to 1. The third pulse generates in the flip-flops 201-204 the binary states written in the table.

After ten pulses have been supplied to the counting circuit 200, there is the flip-flop 202 is in state 1, in which it supplies a set signal for one input of the AND gate 206, and also the Flip-flop 204 is in state 1 and sends a set signal to another Input of the AND gate 206, whereupon this AND gate the state changes. This has the consequence that a blocking signal via the · conductor; is sent to the input side of the AND gate 196. During the rest Decimal counts 0 through 9 are never both flip-flops 202 and 204 in the state at the same time

Consequently, the AND gate 206 changes its state only after ten pulses .

All shift registers 166-175 and the counting flip-flops are not included 201-204 reset. As a result, set signals are sent to the input side of AND gate 196 via the conductor. If the label is from the detector 25 is identified, a set signal is over the line

- 20 -

909034/1224

- 20 - 181

ter 31 applied to the input side of the AND gate 196. If the Phototransistors 16A one token and the phototransistors 16B one Have detected a gap, set signals are sent through conductors 261 and 26B which change the state of a conventional AND gate 215. Am conventional inverter 216 connects one input of the AND gate 215 with the conductor 26B. When the AND gate 215 changes its state, the flip-flop circuit 197 is reset to generate a set signal for to generate the input side of AND gate 196. The plip-plop circuit 197 has the task of ensuring that the shift registers on the oodeleader, to be described later, are gradually replenished with the file counting pulses be forwarded. In this way, both operations run practically at the same time.

To ensure that a valid clock pulse is perceived by the phototransistors 16A and 16B, a counting pulse is only generated when the phototransistors 16B perceive a real clock pulse, e.g. This input function basically supplies the clock pulses. Both inputs are necessary to rule out that clock pulses are generated by dirt or spots between the clock pulses. From Yopstehendem can be derived, that each time ^ when the AND gate 196 äidert its Sustand to a positive pulse "ea _9, the flip-plop-circuit causes 197 to actuate the monostable multivibrator 195. ⁸ The multivibrator 195 'generates a clock pulse ₉ the front flaoke of which triggers the shift pulse, which is entered into shift registers 166-175 by control circuit 191. The trailing edge of the clock pulse triggers counting flip-flops 201-204 via inverter 205 and triggers the reset of a shift register memory to be described from «■

The readout and clock counting circuit also has a reading circuit 220. It is also possible for the reading circuit 220 to use the aforementioned AND gate 215? furthermore a common one: UfB-GXied 22.1 with «dei entrances» At one entrance there is the conductor 31, which leads the acceptors for identification via the same line 2.22. A second entrance is via a 'conductor 223 ait-dem' conductor 2βΑ connected and the third input is connected to conductors 260. Via conductor 260 "

- 21 -

become the determination code signals read from the phototransistors 16G transmitted.

The AND gate thus allows the identification code on which the conductor 260 appears to be read. This occurs only when the phototransistors 16A sense a clock pulse mark, such as the marks ^G i ~ ^G xo ^äes label L, and after the label L has been recognized by the detector as a desired label.

When AND gate 221 responds to the destination code signals transmitted through conductor 26A out by the destination code marks In-Ic are triggered, its line status changes, a ϊΊΙρ-ΡΙορ circuit flips 225. When toggling, the flip-flop circuit 225 sends in Set signal to a conventional AND element 226 of the read circuit 220. On the input side of the AND gate 226 there is also one more Conductor 227 the output of the AND gate 215 mentioned above.

The AND gate 226th is only able to respond to that of the flip-plop circuit 225 to pass on the received determination code if the phototransistors 16B * detect a gap, while the phototransistors 16A report the presence of a clock pulse mark. This is made possible with the AND gate 215. For this purpose, the AND gate changes 215 its state when the phototransistors 16A the presence of a lactimpuLsmarke and the phototransistors 16B the absence of one Determine the clock pulse mark.

At the output of the memory-llip-lPlop circuit 230 are usual AND gates 231 and 232 connected. Every time the plip-flop attitude 230 with a count of ten clock pulses for one label tilts, the AND elements pass one bit of the identification code conductors 233 and 234 into shift register 166 and so on.

The Elip-Plop position 230, together with the AND element 226, ensures that that only one Oode pulse can occur if the Photptransistors 16A find multiple gaps during the sample time for the destination code or even the phototransiators 160 encounter multiple kicks should.

- 22 - '

909834/1224 "

If the counting circuit 200 has a count of. registered ten clock pulses, If the state change of the MD element 206 is a blocking signal via the inverter 210 and through the line 209 and another Line 235 sent to the MD members 231 and 232, which the üChange of the status of these MB links and thus also the transfer of code bits to shift register 165 prevented after ten clock pulses are counted.

While the destination code in the code memory 165 by the transmission ment of the destination codes via the conductor 41 is written readout signals are provided through conductor 195 in a manner to be described sent · These read signals are sent to the input signal ϊθ of the OR gate 193 placed ^ by the control circuit 191 To generate displacement pulses.

The current through the conductor 195 Ausleseägnale get dirch an inverter 236 to the input side of the IMD members 231 or "232," This process inhibits the transfer of code bits to the shift register through the lines 233 and 234j during the time _s in the code memory 165 is read will.

Test circuit for the

The checking circuit 40 for the space between the marks and the Brand width is connected to the OR gate 30 with a conductor 46, to send a rejection signal through this conductor, jSLIs the width of a! Aktimpulsmarke over the specified maximum width or if the gap between clock pulse marks is less than a predetermined minimum width or if the space between Clock pulse marks exceeds a specified width.

For this purpose, the output of a conventional OR gate 250 is connected to the conductor 46. When the OR gate 250 changes its state _p a rejection signal is generated at its output _s which runs through the conductor 46.

The OR gate 250 has three inputs. An entrance is practice? a ladder 252 This OUD element is connected to a conventional MD element 251 has two entrances. One entrance is via a 'further' UWD-GIied

-909634/1224 bathroom original " ²³ "

and a conductor 254 connected to input 26B. The second The input of the AND gate 251 is via an AND gate 255 and a conductor 256 connected to conductor 26A. On the input sides of the AND gates 253 and 255 are also the acceptance manager 31, who carries the signals of the identifier of the label.

As already mentioned, the phototransistors 16B and 16A have the preselected one Distance S so that they can check and determine the width of the clock pulse marks and the distance between such successive marks whether the clock pulse marks are the desired ones.

If both Kffco transistor groups 16B and 16A have a clock pulse mark at the same time read, a reject signal is given through conductor 46 sent. This operation relies on the fact that the clock pulse width is larger than a predetermined width or the space between successive clock pulse marks smaller than a given one Target distance.

When the width of the clock pulse mark is larger than the specified one Maximum width or the space between successive clock pulse marks smaller than the predetermined minimum distance, both phototransistors 16B and 16A read a clock pulse mark and the gate circuits 2OB and 2OA change their line status. This has the consequence that the AND gates 253 and 255 change their state when the detector 25 has sent an acceptance signal for the detection of the label by the conductor 31. This causes the AND gate 251 to change its state, whereupon the OR gate 250 its mode for the transmission of a Rejection pulse through conductor 46 changes.

TJm compliance with the maximum permitted distance between successive Clock pulse marks to check is a delay circuit 260 is provided which contains a conventional AND gate 261 with three inputs. One input of the AND gate 261 is connected to an inverter 262 connected to the output of AND gate 253. The second entrance is connected to the output of the AND gate 255 via an inverter 263. The third input of the AND element 261 is applied via a conductor 264 the conductor 31 carrying the acceptance signal of the identifier.

- 24 909S34 / 122A

If the phototransistors 16B and 16A simultaneously detect a gap while an acceptance _{signal is transmitted by the detector 25 for the recognition of the label 9} , the output signals of the AND gates 253 and 255 cause the AND gate 261 after passing through the inverters 262 and 263, respectively to change its state. This process sets a monostable multivibrator 265 into operation. Typically the output of multivibrator 265 is a low signal. When the MD element 261 changes its state, the multivibrator 265 changes over from L to output 0 within a fixed period of time and then back again to output L, in order to cause a predetermined time delay.

At the output of the multivibrator 265 is a conventional plip-flop circuit 266, which is used at the end of the delay period, i.e. when the multivibrator returns to the binary output L. to give an impulse. The plip-plop circuit 266 in conjunction with a multivibrator 272 has the task of generating a rejection pulse Exclude the beginning of the delay period β

One input of a conventional MD element 270 is connected to the output connected to the flip-flop circuit 266, the other input is via the inverter 263 and the conductor 271 on the MD link 255.

If the phototransistors 16A always after the delay period has expired still read a gap or absence of a clock pulse mark, a return pulse is sent through conductor 46. this happens in that the flip-flop circuit 270 toggles and the OR gate 250 for sending a rejection pulse through the conductor 4-6 prompted.

If, on the other hand, the phototransistors 16A read a clock pulse mark during the delay period, the IPlip-flop latch 270 is blocked via the conductor 271 so that it cannot tip over. S ¹ OgIlieh no rejection pulse is emitted by the OR gate 250 either.

When the phototransistors 16A sense a clock pulse flag, sets

- 25 909834/1224

the multivibrator 272, which is connected via a conductor 273 to the output of the AND gate 255, the multivibrator 265 and the flip-flop circuit 266 back. In this way, the multivibrator 265 starts a next Versögerungszyklus in the moment in which the phototransistors 16A and 16J3 simultaneously detect a gap or absence of a clock pulse mark.

To reduce the risk of a dirty spot or an accidental ! Spot in the area of the identification code In-Ic causes a godefe here, an OR gate 274 is provided, the inputs of which are via lines 275 and 276 and the AND gate 253 and 255, respectively. To the exit of the OR gate 274 is a conventional flip-flop 280 connected to the output of which a further flip-flop 281 is connected. The one The input of a conventional AND gate 282 is connected to the output of the flip-flop 280 and the other input is connected to the output of the flip-flop 281.

Whenever either the phototransistors 16A or the phototransistors 16B read the transition from a gap to a clock pulse mark, the OR gate 274 changes its state, whereby one after the other the counting Flip-flops 280 and 291 become active.

With the paying flip-flops 280 and 281 is a reset circuit 285 connected, to which an AND gate 286 and a conventional reset multivibrator 287 belong. One input of the AND gate 286 is connected to the conductor 26A via the inverter 263 and the AND gate 255. The other input of the AND gate 286 is via an AND gate 288 and an inverter 289 connected to conductor 260.

When the phototransistors 16A and 160 simultaneously have a gap or Determine the absence of a label, then the AND gate changes 286 its state and causes the reset multivibrator 287 to count Reset flip-flops 280 and 281. On the other hand, if the phototransistors 16A and 16B in the aggregate have three transitions from one gap read to a.spot, bo that a count of three in the flip - Fl ^ s 280 and 281 is reached before the phototransistors 16A and read a gap at the same time, then the AND gate 282 changes its State and sends a rejection pulse through conductor 250.

- 26 90983A / 1224

Error recovery and correction circuit

Lie debugging and correcting circuit 45 (Figs. 6A-6C) seeks and corrects individual errors in the 10-month identification code. How nice mentioned, the code memory 165 of the code reading and clock counting circuit 36 transmits the 10-bit destination code serially over the conductor

The debugging and correcting circuit 45 includes one with a 4-bit Shift register "as allowed parity control stage 290 and a destination code memory 295 with a lObit shift register « The 10-bit destination code transmitted through the conductor 41 becomes similateral the parity control stage 290 and the determination code memory 295 entered. The parity control stage 290 performs a parity check on two adjacent bits of the destination code to determine the Check destination code bits that are three bits away. The destination code memory, r 295 stores the 10-bit destination information and sends the 10-bit identification code in parallel through lines 60-69. to the memory 50, if this via the conductor 47 a Readout signal is received, in fact only the. first 6 bits transmitted and the remaining bits are used for control.

The troubleshooting and correction circuit 45 also includes a clock generator 300, which generates readout pulses and on the way via a conductor 301, a conductor 302, a common NAND gate (comb. NOT-UTiD member) 303 and an inverter 304 through the conductor 195 to Godelese and clock counting circuit 35 sends. The clock generator also delivers 300 also the shifting impulses for the quality control stage 290 and the destination code memory 295

A binary counter 305 is connected to the output of the clock generator 300 and limits the clock pulse count for a label to 20 clock pulses. After the count 10, the binary counter 305 switches off the transmission of the clock pulses from the clock generator 300 to the Godelese- and clock counter circuit 35 in order to reduce the output sent by the conductor 195. interrupt reading impulses. This is done by blocking the IALB element 303 via a conductor 306. The binary counter 305 generates a read signal for the memory 50 through its flip-flop 307 on the way via the conductor 47 and a conductor 308 and also a set signal for the OR Link 30.

.909934 / 1224 - 27 -

The troubleshooting and correction circuit 45 also has mod-2 summation circuits 310-312 with EXCLUSIVE OR function. During the time in which the identification code is read, the Identification code memory 295 a total of 20 shifts by lactic impulses. The 10-bit identification code is used for the first 10 clock pulses stored in the destination code memory 295.

The last 10 shifts represent the correction period in which the output of the destination code register 295 is fed back to the input through the summing circuit 312 with an EXCLUSIVE OR function will. The summa ti ο ns circuit 312 receives the 10 bit destination code from the determination code memory 295 and compares it with the stored information in the equality control stage 290. The summation circuit 311 carries out an equality test in the two letters Steps of the 4-bit register of the parity control circuit 290 through. The summation circuit 311 receives the output of the summation circuit 310 and compares it with the incoming 10-bit identification code via conductor 41.

The incoming 10-bit identification code, transmitted serially through conductor 41, changes the binary output of a conventional NAND gate 315 for each input bit. The NAND gate 315 is effective during the above-mentioned counting of 10 clock pulses for each label. A conventional OR element 317 is connected to the output of the NAND element 315 via a conductor 316. Since the OR gate 317 also changes the XBXi logical output with every change at the output of the NAND gate 315, a determination code bit is entered directly into the 10-bit determination code memory 295 and optionally via an inverter 318.

The destination code memory 295 includes ten conventional flip-flops 320-329. The 10-bit designation code is first entered sequentially into the flip-flop 320 and then stepwise from the clock pulses advanced through the memory.

While the determination code bits are stored in the memory 295 they also become the 4-bit match check circuit 290 entered, namely via the conductor 41 »the NAND gate 315» a

- 28 909034/1224

Inverter 319 and summation circuit 311 with EXCLUSIVE OR function. The vieBbit registry of the equality control circuit 290 has standard flip-flops 320-323. The bits of the destination code become serially fed first to the flip-flop 320 and then from the Clock pulses successively through the equality control circuit 290 moved further.

The shifting impulses for the impropriety control attitude 290 and The pulse generator 295 is generated by the clock generator 300. As can be seen from FIG. 6A, the clock generator 300 contains a common NÄHJD-Gli © d 325, an inverter 326, a common monostable Multivibratoj? 327 »-" one: another mono stab! Ie η multivibrator 328, a common MiHD link 329 and an amplifier 330. The NAND gate 325 * the inverter 326 and the .Multiviteators 327 and 328 are connected to an oscillator, with the "conductor" 331 as a feedback line tang., in "which the ■ XFilHHH.ieä 325 is arranged."

I © s LAIP-325 iliMes animal eioen conductor 332 applied a Setzeignal · ,. WeHQ-: DER MaSre Abler 3œ2 ftir'ein label 20 pulses gesttilt hftt- _r wird- ÜMr- dee; at the beginning is at an input ". letter 532 sent a blocking signal. "The third - Blagaa-gfies. MM3 ^ §li®MB '325 isf-.ttber a ladder 336 with eggs. Ladder 355 -TöEteniesae Js l © it © 2 ⁱ 335.11 © gt gang one Hiotoaell.e _: 340 | fig *. -21). _: ..;

A Sielitcpelle tfisft "fß @ s tlsGi» ä @ s ¥ ag fl © ^ Paek-uag a ray of light aiaf the l% otös © ll © 54O> .Wöiaa f © s? Vos & the pack P iea Mcfetafealil ■ p.sittE 'telefe.tp -wisl fiös'eh. <fi © a page 335 a set signal gaisefeMrfep las ä @ a-logiuekem Äiiügaag ä @ s 325 changes and öaö ^ s? @li € © a fafetggaei ^ tes ¹ 30Θ. © ias @ Mlt © clock generator 3QÖ wIe-I. Is / isi © 2 © üsgei5 © lialt © t _?. S © teli i © 2? 305 den ZÄlBtaai 20 © ^ geiekt hsto li © "l & @ t © s © il © 340.ist so arranged, iaö flew ¹ - © df siQ falleniQ SieMsfealii v © a ^ o ^ aeseo-lancl the Paclciiiig P daafö iaatu ^ s ¹ ©
Reading part 16 § © 1θθθβ igt

The 3! Aktgene3? A ^ © S ^j {^ © ° ^) s © M @ 2st? Ogg © Mol) ©; ijipi, ls © siaa codeepeiclier SfS ö5S3? © la ü @ m

BAD ORfGINAt

that to the parity control circuit 290 through the conductor 301 and a Head 336. Furthermore, the clock generator 300 also sends over the ■ Conductor 195 pulses to the Oodelese- and clock counting circuit 35, which run through the NAND gate 303 and the inverter 304.

During the first 10 clock pulses that the binary counter 305 for a Label receives, it sends a set signal to the NAND gate 303, whereby the forwarding of the pulses to the odelese and clock counter circuit 35 is enabled will. During the last ten clock pulses, binary counter 305 sends an inhibit signal through conductor 306, which prevents it from being passed of readout pulses through the conductor 195 prevented.

The clock generator 300 sends clock pulses to the binary counter 305, the the count for a label is limited to 20 pulses each. The binary Counter 305 has four common flip-flops 340-343, which are for one conventional binary counting operation are interconnected. The clock pulses generated by the clock generator 300 are input to the flip-flop 340. A NAND gate 344 is connected to the output side of the flip-flop 343. In much the same way as above for the counter 200 of the code reading and clock counting circuit 35, the binary counter 305 counts to ten. At the end of the ten impulses the NAHM member changes 344 its logical output. As; As a result, a flip-flop 345 flips after every 10 pulses counted.

After the first 10 impulses for a specific label, the Flip-flop 345 through conductor 306 a lock signal that the passing -Before Yersclie pulses from the NAND gate 303 via the conductor 195 to the Oodelese- and clock counting circuit 55 prevented. The Flip-flop 345 a lock signal at the end of the first 10 pulses for a label through conductor 306 and a conductor 346 to NAND gate 315,. in order to prevent that after the first 10 bits there are still identification code bits to the parity check circuit 290 or to the destination code memory 295 will be sent. Finally, a set signal is sent over a conductor 347 to a conventional NAND gate 348 in the destination. cod.espeieh.er 295 sent.

When flip-flop 345 flips, a NAND gate 350 receives on it

. ■: ■■■ - ■. · - 30 - ■

909834/1224

Input side of a S _e tzsignal _ffl Ifeehdem 20 pulses are counted, the flip-flops cause 342 and 343 of the "binary counter 305, the HAND-GIied 350 to change its logic output. This process can via an inverter 351 tilt the flip-flop 307 : «

When the state of the Ms 20 steeling flip-flop 307 changes, a blocking signal is given via the conductor 332, which blocks the NAMD element 325 and thus the. Clock generator 500 switches off after 20 pulses. Flip-flop 307 sends an extraction signal to memory 50 "via" conductors 308 and 47. deoLeiter 308. The multiple OR element 30 for rejection in the event of an error is connected to the output of the HATSTD-CrIiedes 353 via an inverter 354.

As already mentioned, it stores 10-bit determination code memory; 10 bits of information during the first 10 clock pulses for a label. The shift register of the Bestisuaungscoespeichers 295 is reset,. if the pack following the pack P, the pack with its leading edge falling onto the photocell 80. Light beam interrupts, ■ ■;. _ ■ · When this happens, a signal is sent through a conductor 355 "- .. through reset amplifier 356" si 357 and through conductors 358 and 359, which tickles the flip-flops 320-329. The binary flip-flops 340-543 are activated simultaneously via «lea ladder 355? the amplifier 356 and one. Head 360 reset. At the same time xirerden the flip-flops 320-323 _von: the via conductor 355 'AEEN Teiretlrlcer 356 and 361-363 ^conductor: overall. . given reset pulse ^ reset ·. '".- ■■.

Returning to the condition in which the destination memory 295 was located during the first count of 10 '! Clock pulses. of a particular label stores 10 determination code bits tmain contains. The second 10 impulses for the label are used to correct any errors in the destination code, actually the last six stages of the shift register circuit are used as inputs for the odeospeiclier. The remaining code bits are optical Control »During the last 10 counts of the twenty pulses, the output of the determination

- 31 -

code memory 295 from the shift register 329 via a conductor 365 the EXCLUSIVE OR summation circuit 312 is supplied.

The EXCLUSIVE OR summation circuit 312 includes NAND gates 366-369. Each NAND gate has two inputs and one output. The output of the destination code memory 295 is via a conductor 365 with the input side of the NAND gates 366 and 369. The job of the EXCLUSIVE OR summation circuit 312 is to store the Code bits from the output of the destination code memory 295 in receipt and match them with those stored in the parity control circuit 290 Compare code bits.

As described above, code bits pass through the wire 41 »through the AND gate 515 »the inverter 319 and the EXCLUSIVE OR summation circuit 311 into the equality control circuit 290 for 4 bits. The output sides of shift registers 320-323 of the parity check circuit 290 are on the input side of a conventional NAND gate 370} its output with the input sides of NAND gates 366 and 367 of the EXCLUSIVE OR circuit 312 is connected.

The EXCLUSIVE OR receives those stored by the destination code 295 shifted code bits, compare them with those in the equality control circuit 290 stored bits and corrects one-sided errors stored in the destination code memory 295. this happens in such a way that the exit of the EXCLUSIVE OR-holder 312 accepted by the NAND gate 368 and via an inverter 371 » The AND gate 348 and the OR gate 317 are fed to the shift register 321 will.

The EXCLUSIVE-OR summation circuit 310 has four common KAND CK members 372-375, Each NAND gate has two inputs and one output. The output of the third ϊΊΙρ-ΪΙορβ 322 of the parity control circuit 290 is connected to the input sides of NAND gates 374 and 375 of EXCLUSIVE OR circuit 310. The outcome of the fourth ilip-flops 325 of the parity control circuit 290 are on the input sides the NAND gates 374 and 373 of the EXCLUSIVE OR circuit 310. The output of the EXCLUSIVE OR circuit 310 is connected to the Secondary side of the EXCLUSIVE OR ^ summation circuit 311 connected.

- 32 909034/1224

It is the EXCLUSIVE-OR-view 310 that carries out an equality check of the code bits, for which purpose the flip-flops 322 and 323 of the equality check circuit are used.

As shown in Figure 6A, the EIKUJSIlE OR circuit 311 comprises four common JSAND gates 376-379. Each NAND gate has two inputs and one output. The output of the EXCLUSIVE OR circuit 310 is connected to the input sides of the NAND gates 376 and 378 of the EXCLUSIVE OR circuit 311. In addition, the 10-bit designation code is input from the code reading and clock counting circuit 35 to the NAND gates 376 and 377 through the conductor 41. The output of the EXCLUSIVE OR circuit 311 »which is taken from the NAND gate 379 is fed once directly to the flip-flop 320 of the equality control circuit 290 and then optionally via an inverter 392. The EXCLUSIVE OR circuit JIl compares the output of the EXCLUSIVE OR circuit 31b with the incoming bits of the destination code. Each incoming determination code bit is therefore compared with the last two bits in the equality control circuit 290. In this way, two adjacent bits len * _r Utzt to bits-to check which are bits removed by 3 "

Connected to the output sides of the flip-flops 320 * 525 - "of the equality control circuit 290 is a standard GÜE-Srliecl 385, the output of which is connected to the input side of the IMB-SMeäes 353. If the equality control circuit 290 detects an excessively high number of errors, changes the; logical - output of the OR gate 385 "D _a when the. NAND gate -353" is set · Yes Ate the count-of 20, the NAND gate 353 is also used by the "flip" flop 307 is set. Another set input for the NAND gate comes via a flip-flop 386 and an inverter 387. If the logic output of the NAND gate 370 changes, the flip-flop 586 changes its mode · The flip-flop 386 is reset by a signal that is applied via the conductor 361 and a conductor 388 "- If the JÜIB-Siied 353 changes its logical output; 589. A rejection signal sent to the OR gate 30 -

The OR gate 30 sends a warning signal through the conductor 51 ₁

either if via the one leading to the instruction of the label recognition Head 27 or through whom the rejection of the mark distance check leads to • A reject signal arrives at the end of the conductor 46 or if the parity control circuit 290 multiple! Errors detected.

If the god reading and reading counting circuit 35 does not count "to 10" has before the photocell 340 changes its state, a NAND gate changes 390 its logic output and sends a rejection signal via a conductor 391 to the OR gate 30. The photocell 340 changes their state when the leading edge of the package P interrupts the light beam thrown on the photocell.

The photocell 340 is via the conductor 335 with the input side of the NAND gate 390 connected. The god reading and lact counting posture 35 is connected to the input side of the troubleshooting circuit 45 connected from the AND gate 206 via a conductor 392 and through an inverter 393.

If there is no rejection signal from the OR gate 30 "through the conductor 51 is sent to Speicher'50 and the debugging and correction circuit 45 gives a read-out signal to the memory 50 via the conductor 47, the odebits stored in the determination code memory 295 become sent to memory 50 simultaneously or in parallel operation via conductors 60-65.

Storage

The memory 50 (S ¹ Ig. 8) receives the determination code bits from this circuit 4-5 via the conductors 60-65 in response to a command from the debugging and correcting circuit 45 in the conductor 47. The memory 50 for its part controls the puncture of mechanical objects, such as the deflectors 401-408, in accordance with the recorded determination code bits in order to sort the packs for delivery to their destination in accordance with the destination code on the label of each individual pack.

-34-

909834/1224

The memory 50 also writes down rejection signals sent to it by the OR gate 30 are transmitted via the conductor 51.-If the Memory 50 receives such rejection commands, the diverters are not actuated and the package to be rejected becomes a Rejection chute promoted.

In the embodiment of the figure, the memory 50 contains twenty memory units 411-430. Each such memory unit, designed as a shift register, includes six customary flip-flops. A flip-flop is present for each stored determination code bit _β

The memory unit 411 is connected to the conductors 60-65 and also to the conductors 51. When a suitable logical shifting circuit 431 receives a read signal via conductor 47, it checks via conductors 431a-431fj whether all of the flip-flops of the memory unit 411 have been reset. If this is the case ₉ , it allows via a conductor 411a that the determination code bits appearing on the conductors 60-65 are entered into the storage unit 411 in order to be stored in aevi flip-flops of this storage unit. "

The storage units 411-420 operate in pairs. The storage unit 411 is assigned the storage unit 412 "The storage unit 411 can be referred to as the backup unit and the storage unit 412 as the unloading unit".

After the storage unit 411 receives the u-bit destination code information has saved, a suitable automatic shifting circuit 432 first checks via conductors 432a-452f whether all flip-flops of the memory unit 412 are reset. If oil is the case, then it creates the automatic shift switch 432 in conductor 412a a request signal, that is, the destination code bits stored in memory 411 Transfer to the storage unit 412 via connecting lines leaves. The storage 411 flip-flops are then via a Conductor 411b from automatic circuit 432 reset.

Correspondingly, the storage units 413 and 414 can also be used as a pair The storage unit 413 is the storage unit and the storage unit 414 is the accumulation unit. if

an automatic shift circuit 433 detects over conductors 433a ~ 433f, that all flip-flops of memory unit 413 are reset, it generates a polling signal via a conductor 413a, which the in the Storage unit 412 allows stored bits to be transferred into storage unit 413 via connecting lines. The flip-flops of the memory unit 412 are reset by the automatic shift circuit 433 through a conductor 412b.

An automatic shift circuit 434 checks via conductors 434a-434f whether all of the flip-flops in the memory unit 414 have been reset. W _e nn is the case, sends the automatic shift circuit 434 a polling signal through a conductor 414a "that lets registered in the storage unit 413 Baäimmungscodebits via connecting lines in the storage unit 414 tibet occur. The flip-flops of the memory unit 413 are then reset to a signal in the conductor 413 "b.

Two groups of storage units are described above; should the memory 50 require further such groups, then corresponds to their Operation of the above

In the embodiment of the invention, eight toalenker are provided, namely the deflectors 401-408. The construction and function of suitable deflectors are detailed in the above-mentioned US patent explained. Each diverter is a pair of storage units assigned. For example, the diverter 401 includes the storage units 415 and 416. The storage unit 415 is the storage unit and the storage unit 416 is the unloading unit. Correspondingly, the diverter 408 includes the storage units 429 and 430, of which the former the storage unit and the latter the withdrawal unit is.

An automatic shift circuit 435 provides over conductors 435a-435f determines whether all flip-flops of the memory unit 415 are reset are. If so, it sends a polling signal through conductor 415a which contains the destination code bits stored in memory unit 414 into the memory unit 415 via connecting lines can be trespassed. Thereupon the automatic shift circuit gives

909834 / 122i ^{ORiGlNAUNSPECTED} ~ ⁵⁶ ~

a reset signal on conductor 414b that resets all of the memory unit's flip-flops 414 resets.

If there is a pack, for example the pack P, the diverter 401 approaches, it interrupts one falling on a photocell 441 Beam of light. This changes the state of the photocell 441 and triggers the operation of a logic shift circuit 442. If If this logical shift circuit 442 is active, it checks via conductors 442a-442f whether all flip-flops in the memory unit 416 have been reset are. If this is the case, the overshoot logic circuit sends 442 a polling signal through a conductor 416a which is the one in the memory unit 415 is transferred to the memory unit 416 via intermediate lines. There is also the logic shift circuit 442 a reset pulse to a handlebar 415b, which the flip-flips resets in the memory unit 415.

At the output side of the memory unit 416 is a detector circuit connected in the form of a conventional diode matrix 3445, which the Code scans according to the code applicable to the ümlerücer 401. When the determination code bits stored in the storage unit 416 match the identification code for diverter 401, the Diverter 401 started to move the package P to its destination to direct. When the Umlenker 401 is active, it becomes a backsetting circle 446 triggered, the via a conductor 447 a reset pulse which resets the flip-flops of the security unit 416.

■ - ■■. ■■ ■■■. '-

If the code of the diode matrix 445 for the deflector 401 does not match the destination code bits stored in storage unit 416 match, the diverter 401- is not active and the one in the storage unit 416 stored determination code bits are in the manner described above for the storage units 414 and 415 in the next following Einspeloherungseinheit transferred. Turn the pack on If the photocell 441 darkens the following photocell, it becomes the storage unit of the next pair in the for operation of the storage unit 416. All storage units » Pairs from storage unit 415 to storage unit 430 operate in the same way and are toned in the same way, of course each Pair has its own photocell and diverter.

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When the information stored in the storage unit 416 is rejection information then the code of the diode matrix 445 is correct. does not match the rejection information. The then onset Operation is the same as for any other situation, in that the code of the diode array 445 does not match that in the memory unit 416 stored identification code> its matches. Also none The following diode matrix has one with the stored rejection information matching code; consequently none of the diverters is put into action. The pack to be rejected runs on the deflectors past further to a chute or conveyor for the committee.

It is assumed that the code assigned to the diverter 408 corresponds to the order immungs co de on the label of the incoming package. When an automatic shift circuit 450 is provided across the ladder 45Oa-45Of detects that all flip-flops in storage unit 429 are reset it sends a polling signal through a conductor 429a, that is, the determination code bits located in the preceding unloading unit transferred to the storage unit via connecting lines. In addition, the automatic shift circuit 450 transmits a reset pulse to the preceding storage unit, which resets all shift registers of this unit.

Venn the pack the light beam falling on a photocell 451 interrupts, - the photocell 451 is assigned to the deflector 408, a logic shift circuit 452 is triggered. Now check that Shift circuit 453 via leiter'452a-452f, whether all of the flip-flops Memory unit 430 are reset. If this is the case, the shifting circuit 452 sends a polling signal via a conductor 43Oa, which allows the determination code bits stored in the memory unit 429 to pass into the memory unit 430 via intermediate lines. Furthermore, the shift logic circuit 452 outputs a reset signal on a conductor 429b, which contains all flip-flops of the memory unit 429 resets.

A conventional diode matrix is attached to the output side of the memory unit 430 453 connected. The destination assigned to the diverter 408

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ORIGINAL INSPECTED

code and the code of the diode matrix453 match the identification code on the label of the package which interrupts the light beam falling on the photocell 451 and with the identification code information, which is stored in the storage unit 430. As a result, diverter 408 acts in a manner such as this is explained in more detail in the above-mentioned US patent, and directs the package to its destination.

When the diverter 408 is active, a click-setting circuit 454 is activated, which emits a reset signal via a conductor 455, which resets all lip-flops in the memory unit 430. The change in state of the photocell 451 is set by transmitting a trigger signal via a conductor 457 an automatic reset circuit 456. This sends a reset pulse through a conductor 458, which resets all jlip-flops of the storage line 430 if the diverter 408 fails. Mick reset circuit can not act 454 _s because the incoming packet does not have a matching destination code with the code of the deflector 408th

Changes and modifications of the described are within the scope of the invention .Example possible.

- patent claims -

- 39 "

Claims (18)

Claims 1 «Code reading and control switchgear that has a moving Scans object carrying identification code marks and clock pulse marks, characterized by three scanners (16A, 16B, 160), the first of which and the second scanner (16A, 16B) the clock pulse marks (Ο-ι-Ο, φ) read and the third (16G) to read the identification code marks (I -, - Ic) is arranged, further by a circuit (35) connected to the three samplers, which generates clock pulses and during the corresponding Clock pulse spans the scanned destination code signals "registered, and by a clock pulse test circuit (40) connected to the first and second samplers, which outputs a reject signal generated when the first and second samplers have a non-conforming one Read clock pulse mark. 2. Switching arrangement according to claim 1, characterized in that the first and the second scanner (16A, 16B) have a distance (S) from one another ^{in the direction of port movement of the u object.} 3. Switching arrangement according to claim 2, characterized in that the Distance (S) of the first and the second scanner is greater than the dimension of a compliant clock pulse mark in the direction of travel of the object * 4 »Gearshift configuration according to. Claim 3, characterized in that .die Clock pulse test circuit (40) "on detection of a non-conforming Space between successive clock pulse marks (O ^ C ^ q) a warning signal is generated. 5 «switching arrangement according to claim 3, characterized in that the ! Pakt pulse test circuit (40) generates a instruction signal when a 'JJaktimpulsmarke in the port movement direction of the object a nonconforiae Dimension has. - 40 - 909834/1224 6. Switching arrangement according to claim 1, wherein the object additionally still carries identification marks, characterized in that the three scanners (16A, 16B, 16C) a detection circuit (25) is connected which emits a rejection signal when the three scanners read an identification code that is not the desired identification code corresponds, on the other hand, when the three scanners read a predetermined identification code ·, an acceptance signal to the pulse generating and circuits (35) registering the destination code sends * 7. Switching arrangement according to claim 6, characterized in that the Detection circuit (.25), if the three scanners read a predetermined identification code, also an acceptance signal to the clock pulse test circuit (4-0) gives which this circuit can be activated. 8. Switching arrangement according to claim 6 or 7, characterized in that that a rejection signal is generated if the scanner has an insufficient Distance between the identification marks (Α ·, -Α,) and the hook pulse marks (C ^ -Otq) determine. 9. Switching arrangement according to one of claims 6 to 8, characterized in that that a rejection signal is generated when the scanners perceive an inclination at the identification marks (A ^ -A *). 10. Switching arrangement according to one of claims 1 to 9, characterized in that that the lactic pulse test circuit (40) emits a rejection signal, if the first and the second scanner (ΙβΑ, ΙβΒ) at the same time detect the absence of a mark and then during one initiated time delay of the second scanner (16B) still always detects the presence of a mark. 11 · Switching arrangement according to claim 10, characterized in that the iDakt pulse test circuit (40) contains a delay circuit (260). 12. Switching arrangement according to one of claims 1 to 11, characterized in that that the circuit (35) generating the pulse pulses Troubleshooting and correction circuit (45) is connected downstream for detection and correcting errors in the destination code signals, ■■ - ■ '- 41 - 90983-4 / 1224 to which a memory (50) is connected, which the determination code signals stores and sorting devices (401-408) for the objects ■ controls. 13. Switching arrangement according to claim 12, characterized by lines (27,46) which carry the rejection signals and the detection circuit (25) or the clock pulse test circuit (40) with the memory (50) connect. - 14. Switching arrangement according to claim 12 or 13, characterized in that that the troubleshooting and correction circuit (45) generates a rejection signal upon detection of multiple errors in the destination code and via a line (389) to the memory (50). 15. Switching arrangement according to claim 14, characterized in that the Troubleshooting and correction circuit (45) an equality control circuit (290) for finding multiple errors. 16. Godablese- and control switch arrangement, which a bev / egtes, identification marks and scans an object carrying clock pulse marks, in particular according to Claim 6, characterized by a first and a second scanner (16A, 16B), which the clock pulse marks (Cn-G-wO read and have a greater distance from each other than the dimension of a compliant clock pulse mark in the direction of movement of the object is equivalent to. 17. Switching arrangement according to claim 16, characterized in that the first and the second scanner read the identification marks (A -, - A-) and have a distance from one another which is smaller than the dimension of a conforming landmark in the direction of movement of the object. 18. Switching arrangement according to claim 1, characterized in that the circuit (35) connected to the scanner generates clock pulses, while the first scanner (16A) has a clock pulse mark and the second Scanner (16B) at the same time the lack of a clock pulse mark perceives. 909834/1224