DE1789144A1 - METHOD OF MANUFACTURING A SEMICONDUCTOR ARRANGEMENT - Google Patents

Description

N.V. Philips' Gloeilarapenfabrieken, Eindhoven / Holland Method for manufacturing a semiconductor device

The invention relates to a method for producing a semiconductor arrangement with a semiconductor body made of silicon with at least one semiconductor circuit element, in which a semiconductor surface is provided with a flat silicon oxide layer in the form of a layer-like pattern of silicon oxide which only partially covers one surface with the aid of an oxidation treatment will. -. ■■ "■

Methods of this type are used, among other things, to produce planar ones Semiconductor arrangements used.

The oxide layer provided fulfills an essential puncture with respect to the circuit element. This oxide layer can be used, for example, as electrical insulation between one on the Oxide layer "allegedlyfcers electrical conduction, which with a Zone-des. Circuit element is connected, and the silicon body servers, v.-eitr-r kaiin the oxide layer to improve the -oborfiaciieheitfischaften the silicon body m, d ε-omit

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to improve the electrical properties of the Circuit element are attached, wherein the oxide layer at least those parts of the surface of the Silicon body covered where at least one of the pn junction areas of the circuit element cuts the silicon surface. Furthermore, the oxide layer in the Production still serve as a diffusion mask.

In known methods of this type, the oxide layer is locally removed after application, so that a layer-like Pattern of silicon oxide is obtained. The part of the silicon surface that is not covered by the I / Juster is then placed the processing usual in semiconductor technology, e.g. diffusion treatments and treatments for attachment electrical contacts, subjected to receive the circuit element.

The known methods encounter various difficulties in various applications. In an oxide layer windows can be attached by etching with relatively great accuracy. However, this accuracy decreases in the Dimensions from j in which thicker oxide layers are used, da when etching, oxide is etched away not only in the thick direction of the oxide layer but also in lateral directions; this lateral etching away also limits the smallest achievable dimensions of one to be provided in the oxide layer Penst.ers. Taking into account the exact training of a An oxide layer that is as thin as possible is therefore desirable in the pattern.

For other reasons, however, a thicker oxide layer is often desired, e.g. to provide good insulation between an the line to be applied to the oxide layer and the silicon body and / or to achieve a low capacitance between this line and the silicon body. Furthermore, a

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thin oxide layer easily damaged if a connection line is attached to a metal sheet attached to the oxide layer.

The surface of a planar semiconductor device with a silicon body provided with an oxide layer is, on which metal layers are attached, should if possible being flat «Irregularities arise, among other things, from Openings provided in the oxide layer through which the Metal layers are connected to the silicon body. At The ligaments of these openings can have irregularities and Damage to the metal layers occurs, and the more easily the thicker the oxide layer in which these openings are are provided.

The described advantages and components of both thin and In practice, thick oxide layers can also often cause problems .Compromise "necessary with regard to the thickness of the oxide layer, but none of the difficulties are satisfactorily resolved.

In the case of the methods of the type mentioned, at least a pn junction of the circuit element is obtained by that an impurity is diffused into the silicon body through an opening in the oxide layer. It arises thereby a trough-shaped pn-transition surface, which at the edges is strongly curved and at these edges approximately transverse to the surface of the silicon body and the Oxide layer runs. "This has two disadvantages. The strong curvature of the pn junction area has an unfavorable effect on the breakdown voltage of the pn transition, since the pn - 'transition area near the edges approximately across the oxide layer runs, can in the operation of the circuit element a drift of existing on the surface of the oxide layer, practically unavoidable ions occur, whereby the circuit element becomes unstable. It is therefore often a problem pn junction desired. /

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The invention is based on the object of a method of the type mentioned at the beginning, "with your the above the disadvantages of the known processes described largely be avoided.

According to the invention, this object is achieved in that first of all one surface is locally covered with a masking that prevents the oxidation of the silicon and then the pattern is given an oxidation treatment with at least one rope _; he thickness is sunk, attached, that then at least one rope of the masking layer is removed in order to expose the underlying surface part of the semiconductor body and that φ a metal layer is attached which makes an electrical connection with at least one rope of the surface part of the semiconductor body thus exposed forms and also extends over the recessed pattern.

Since the layer-like pattern of silicon oxide over at least part of its strength is sunk into the semiconductor body, can by the method according to the invention flatter semiconductor arrangements are obtained than when known methods are used, even in the case of a thick one Oxide layer. This means that the surface is very even, so the metal layer has only very low steps, £ Furthermore, the silica sheet is used directly as a slide, ™ ten-like pattern attached so that the oxide layer does not need to be etched, which is particularly in the thick oxide layer is advantageous.

Preferably, at least one metal layer is applied to the layer-like pattern of silicon oxide, which is shown in FIG in a manner customary in semiconductor technology with a diffused zone obtained by diffusion of an impurity is connected, while a connecting lead is connected to this metal layer is connected.

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line is another very important, preferred form of execution Manufacture of a monolithic semiconductor circuit is characterized in that the Silijsrumkörper with a Insulating layer is provided, which consists of the recessed pattern and an adjoining thin part, that circuit elements were attached, of which semiconductor zones bordered on the thin part, and that .on the Insulating layer a 'metal layer forming conductor tracks is attached, which also extends over the recessed pattern.

In the manufacture of monolithic semiconductor circuits it is often desirable to use a thin insulating layer of, for example, silicon oxide or silicon nitride, however during the connection of a connection line to a connection surface of the conductor tracks on the insulating layer, this thin insulating layer can be damaged, so that a short circuit can occur between the connection line and this silicon body. The insulating layer can also be damaged when testing the manufactured semiconductor device, contact pins are pressed against the connection points. In practice, this leads to a large connection. By doing according to the invention a pattern is used, by means of which an insulating layer is obtained, which at the point of the pattern has a thickening and the connection surfaces are attached to the pattern, the aforementioned connection can be practically completely avoided.

The oxidation masking material preferably has one Thickness less than that of the pattern to be applied made of silicon oxide. Such a masking layer can by etching or sputtering more accurately into a desired pattern than a thicker layer. It is advantageous to protect the silicon body locally from oxidation, by applying a layer of silicon nitride. Other Masking materials are possible, for example certain metals such as platinum or iodium. These masking materials are metals

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however, the high temperatures, ζ „Β. from 1000 ° 0 or very, the usual oxidation treatments, in which s.B. wet oxygen below about atmospheric pressure above the silicon body is guided, significantly less resistant.

Becomes locally on a surface of a silicon body If a silicon oxide layer is attached by oxidation, the layer-like pattern obtained is overlaid with silicon oxide sunk part of its thickness into the semiconductor body. Preferably, however, the oxidation treatment is at least once interrupted, with at least part of the oxide layer already formed during the interruption their thickness is removed again, e.g. by etching. In this way one can have a larger rope of its thickness or even Sehten-like pattern sunk into the silicon body over its entire thickness will be preserved. Furthermore, before the application of the pattern of the silicon body already an etching treatment at the places intended for the pattern be subjected.

As can be seen from the foregoing, the invention is particularly important for applying a thick, layer-like pattern, for example with a thickness of at least 0.5 / µm. Preferably, a line-like pattern is sunk into the silicon body over at least 0.5 .mu.m of its thickness appropriate.

An embodiment of the method according to the invention is essential in which a pattern is produced by means of the masking a silicon oxide layer with at least one opening is applied. Even with a thick oxide layer, the opening to be very small, as in contrast to the known Method the opening does not need to be made in the oxide layer by etching. The masking that e.g. aiis a thin Silisiunoiitrxdschicht can exist, can by photolithographic processes exactly in the form of oiiios or more—

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small spots must be attached. Next is on the location of the opening does not contain a small a deep hole that would make it more difficult to make a contact, because the pattern is sunk into the silicon body.

The masking in the opening can advantageously be completely removed from the surface of the safety body and on the surface in this. A metal layer can be applied to the opening, so that a Schottky diode is obtained (diode with a metal-cal lead junction). This metal layer extends over the silicon oxide to enable an electrical connection to be made.

Furthermore: the masking of the surface of the silicon body in the opening can be removed and a pn junction can be applied in the silicon body by diffusing an impurity into this surface and a metal layer can be brought into contact with the latter surface, which extends over the silicon oxide layer, ura to be able to attach an electrical connection. In this way, _x, for example, a very small pn diode can be obtained.

Since the oxide layer can be thick without concern, a good insulation between one attached to the oxide layer Metal layer and the semiconductor body can be obtained while in the attachment of a lead the risk of damage to the oxide layer on the metal layer is very low.

Another embodiment of the method according to the invention is characterized in that after removing at least one 50eil.es of the masking of the surface of the silicon body in the opening by diffusion of an impurity into the exposed surface at least one pn overgarifi j.n the silicon body is attached. This transition is at a lesser depth than the

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Surface as the countersink depth of the pattern in the body. In this way, a practically flat pn junction can be obtained, its pn junction area . "approximately parallel to the surface of the silicon oxide layer runs and yet limited at the edge by the oxide layer will. Thereby, the aforementioned ion drift and reduction the breakdown voltage is limited by the strong curvature of the pn junction area.

Before the impurity is diffused in, the goose Masking can be removed while after attaching the pn junction by means of a diffusion mask in a part the surface of the silicon body in the opening of the pattern, an impurity can be diffused to a second pn junction at a shallower depth from the surface than the already existing pn junction au received. A planar npn or pap transistor structure is then created, one of the pn junctions being practically flat.

In another important implementation of the procedure According to the invention, the masking is only partially removed before diffusion, while after diffusion and after attaching by oxidation of a silicon oxide layer in the opening on the one not covered by the masking Surface, wherein the oxide layer is thinner than that of the pattern and over at least part of its thickness in.den Silicon body is sunk, the remaining part of the masking is removed, and into the exposed surface an impurity diffuses to a pn junction to get that to the already existing pn-junction connects, as well as an impurity to achieve a second pn-Üfoerganges, which is at a smaller depth in the Silicon body lies as the mentioned subsequent pn junctions and as the depth of the recess of the thinner silicon oxide layer in the silicon body '. It can be based on this Way a transistor structure jioit - a practically flat one Emitter junction and a base zone are obtained ', their

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is thinner than the part lying under the emitter zone remaining rope is the base zone.

The invention is also of relevance to manufacture of semiconductor devices in which a silicon body in 3? Form of a silicon chi ent attached to a support is used. Often a number of Sehaltmigselementen are formed in such a silicon layer to obtain an integrated circuit. If it is necessary to isolate the circuit elements from each other, so will often across the SiIiziuraschient and between the circuit elements Grooves are provided so that the silicon layer is divided into parts. This has one major drawback in that the billen bumps in the surface of the arrangements to be made. Isolation can further be obtained by having two pn junctions be attached between the circuit elements. However, parasitic transistor effects can occur. Another important one that avoids this disadvantage Embodiment of the method according to the invention is based on a silicon body. the one on one Carrier-attached silicon layer consists, while in the application of the strip-like pattern of silicon oxide the oxidation treatment is continued until the See pattern over the entire thickness of the insulating layer, wherein the silicon layer is divided into a number of parts which are separated from each other by the pattern. Circuit elements can be accommodated in the parts that are electrically isolated from one another by the pattern.

Several embodiments of the invention are shown in FIGS Drawings shown and are described in more detail below. Show it

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Fig. 1 Ms 3 Schematic cross-sections through a

Semiconductor body in successive stages of the production of a countersunk Silicon oxide pattern

Hg. 4 a schematic cross section through a

Schottky diode produced by the method according to the invention

Fig. 5 is a schematic cross section through a

pn diode produced by the method according to "the invention

3? Ig. 6 shows a schematic cross section through a

pnp- bsw produced by the method according to the invention. npn transistor

Mg. 7 to 9 schematic cross sections through parts of the

Semiconductor body in various stages of manufacture an npn or pnp transistor produced by the method according to the invention with step base

10 shows a schematic plan view of a semiconductor arrangement with two semiconductor circuit elements, which according to the method according to the Invention is made

Fig. 11 shows a cross section along the line XI-XI

in Fig. 10.

Fig. 12 see a cross section along the

Line XII-XII in Fig. 10 and

13 shows a schematic cross section through a

Carrier body on which a SiIi sittffiS'clii ent is appropriate to follow the old deia procedure of the invention with a silicon oxide pattern

is provided.
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For the individual execution dubbing described below among other things, the difference in the! ^ speed of silicon nitride, silicon oxide and a mixed oxide of lead and silicon (lead glass) used in the subsequent etching liquids;

Hydrofluoric acid (50 %)

Etch rate of silicon nitride (mounted on a SiIiziumkörper by heating this body to about 1000 ⁰ C in a 'gas mixture of SiH, and-NEL) is about 300 Å / sec about 0.3 S / sec etch rate of silicon oxide.

In strong, dilute! Hydrofluoric acid they take Etching speeds from.

P-Etching agent, a liquid made from 15 parts of hydrofluoric acid: (50 Yo) ₁ 10 parts of HFO ₅ (70 <? <>) And 300 parts of water. '

Etching speed of silicon oxide about 2 S / sec. Etching speed of lead gals about 300 S / sec.

example 1

This example relates to a method of making a Semiconductor arrangement with a Schottky diode '(see Fig. 4). This semiconductor arrangement 20 consists of a silicon body 1 with a metal-semiconductor junction forming the Schottky diode 11, -13 on the surface 10 of the silicon body 1, on which a silicon oxide layer is applied. The practical flat silicon oxide film is made through an oxidation treatment generated on the surface of the body 1 and applied in the form of a layer-like pattern of silicon oxide 8, whereupon the surface part not covered by the pattern 8 subjected to a treatment customary in semiconductor technology is to produce the circuit element, here the Schottky diode. Dios means in -d-om the present Äusführungixigs-example the application of a metal layer 11..

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In the known methods the entire surface of the silicon body is covered with silicon oxide, whereupon, to To generate the pattern, an opening is made in the oxide layer, e.g. by etching, and then in this opening the metal-semiconductor junction is produced. According to the invention, a layer-like pattern is made of silicon oxide directly attached, which is sunk into the silicon body 1 over at least part of its thickness, as during the oxidation treatment, the surface of the silicon body is locally protected from oxidation.

For this purpose, a silicon body 1 (Pig. 1) is assumed, which consists of a silicon wafer 2 of the n-iP type with a resistivity of about 0.01 hem and a thickness of about 200 / µm. An n-type silicon layer 3 is formed on this silicon wafer by epitaxial growth with a specific resistance of about 1 Jl cm and a thickness of about 4 / µm. The other dimensions of the Silicon bodies are less critical. The silicon body 1 is usually chosen to be large enough to accommodate a larger one Number of circuit elements to be able to attach side by side at the same time, the body is then subsequently in divided the individual circuit elements. For the sake of simplicity, only the production of one circuit element is described below described.

A masking is applied to the layer 3, which consists of a layer 4, 5 of material protecting against oxidation with a thickness which is smaller than that of the pattern 8 to be applied. A layer 4, 5 of silicon nitride is preferably applied. The silicon nitride layer 4, 5 can be applied by a method customary in semiconductor technology, in which the body 1 is heated to approximately 1000 ^° _{C. in a gas mixture of SiH 4} and NH _5. The layer 4, 5 has a thickness of 0.1 μm, for example.

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According to a known method such as a photolithographic Method, the layer 4, 5 is then partially removed, so that a round disc 5 with a Diameter of about 5 µm remains. Since the layer 4, 5 is thin, the small dimensions of this Disc must be adhered to very precisely. In which then water vapor with a pressure of 1 atmosphere at etv / a 1100 ° 0 is passed over the body 1, a pattern of silicon oxide appropriate. This oxidation treatment is interrupted after 2 hours; is then already an oxide layer 6 with a thickness of about 1 / µm, which is sunk into the body 1 over about 0.5 / µm (Pig. 2).

During the interruption of the oxidation treatment, the oxide layer 6 obtained is through over its entire thickness Etching with hydrofluoric acid removed again. The oxidation treatment is then repeated so that the 1 / um thick pattern of silicon oxide 8 (Pig. 3), which is provided with an opening 7, is created that practically over its entire thickness is sunk into the silicon body 1.

Then the body 1 is in the presence of a lead oxide plate, which is close to the masking disk 5, for example in a The distance of 0.3 is now held for about 5 minutes heated to 700 ° ö. As a result, the silicon nitride of the disk 5 is converted into lead glass. This lead glass can by heating in the above-mentioned P-type etchant approximately 1 minute to be solved.

The masking 5 is then completely removed from the surface of the silicon body 1 in the opening 7. A gold layer 11 is then applied to this surface 10, which gold layer 11 forms a Schottky contact with the semiconductor body, as a result of which this gold layer 11 extends over the oxide layer 8 in order to produce an electrical connection. The gold layer 5 has, for example, a diameter of 20 / ura and can be made by a known method, for example by

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vaporizing attached. The electrical connection is in usually produced by attaching a lead 12 to the gold layer. This attachment is facilitated by the fact that the gold layer 11 is practically flat, since the pattern 8 is sunk into the body is.

The body 1 can be attached to a metal support plate 13 in a conventional manner, for example by soldering or alloying which serves as the second electrical connection of the Schottky diode.

Example 2

A p-type silicon body with a specific resistance of 25 -Sicm and a thickness of 200 μm is, as described in Example 1, with a practically over its The entire thickness is provided in the silicon body 21 (FIG. 5), which consists of a pattern provided with an opening 22 flat silicon oxide layer 23 with a thickness of about 1 / um. The opening has a diameter of 100 / um.

The masking layer is based on that described in Example 1 Way from the surface 24 of the 3 silicon body 21 in the opening 22 removed. A pn junction 25 is then produced by diffusion into the surface 24 in the body 1 and a metal layer 26 forming a contact is applied to the surface 24. If the opening 22 is small, so can the metal layer 26, as in the embodiment described above, extend over the oxide layer 23 to a sufficiently large surface for attachment of a To get connecting conductor.

The depth of the pn junction 23 is from the surface seen shallower than the depth over the da.fi pattern 23 .in

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the silicon body 21 is sunk. The pn transition 25 v / ird e.g. at a depth of 0.7 / u: n through the usual Phosphorus diffusion attached, the η-conductive zone 28 being formed. The result is a practically flat one pn junction 25, the edge of which is nevertheless adjacent to the oxide layer 25.

After cleaning the surface 24, an aluminum contact layer is applied in the usual way, e.g. by vapor deposition? .6 appropriate. This leaves you a px * actically ohii.sch.er contact reach. The semiconductor body is then fastened in the usual way on a metal plate 27, which is also forms a contact. A connection conductor can also be attached to the contact layer 26. The one made in this way The semiconductor arrangement thus forms a pn diode. The diodes made by this method of the invention showed a breakdown voltage of about 200 V, while those made from the same Ma.terial according to the previously customary methods manufactured diodes that do the same thing (Oxidations, diffusions) have a breakdown voltage of not more than 100 V.

The difference in breakdown voltage is caused by the fact that by the method according to the invention diodes produced have a practically flat pn junction, while those produced by the usual planar process manufactured diodes have a curved, ultra pn junction.

Example 3

A semiconductor device with an npn or pnp transistor structure can be prepared by the method of the invention as follows.

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After the masking layer has been removed from the surface 34 (Pig. 6) of the silicon body 31 in the opening 33 of the recessed pattern 32 is removed, and a practically flat pn junction 35 on that described in example 2 Has been applied in the manner, the surface 34 is provided with a diffusion mask. This diffusion mask is, for example, a silicon oxide film 41 having a thickness of about 0.3 / .mu.m with an opening 37. This diffusion mask can be in a manner customary in semiconductor technology and way to be attached. This is followed by diffusion of an impurity through the opening in the usual way 37 a second pn junction 36 is attached at a shallower depth than the already existing pn junction 35, see above that a pnp or npn structure results.

As is customary in planar technology, then on the oxide layer 32 metal layers 40 and 39 attached, through openings 38 and 37 with the through the pnp junctions 35 and 36 limited diffused zones 45 and 44 are connected. The metal layers 40 and 39 are then used to form connecting conductors 44 and 43 connected. Finally, the semiconductor body 31 is attached to a metal plate which is also used as a contact 42 attached.

The transistor structures so produced have a practical one flat pn junction 35 »which can serve as a collector or emitter junction, while the pn junction 36 is used as a Emitter or collector junction is used.

That part of the semiconductor body containing the junctions 35 and 36 31 can be an epitaxially grown silicon layer the pattern 32 may extend over the entire thickness of this layer. It is then a Structure possible that of an epitaxial mesa transistor structure is equivalent to.

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In the case of a transistor *, the silicon oxide cluster 32 can advantageously have a greater thickness (for example 2 μm) than in the case of a diode, as a result of which the shallow junction can be made deeper and more space is available to accommodate the second pn junction.

Since the metal layers 39 and 40 are iru v / es arise Extending across the thick pattern 32 is the capacitance between these metal layers and the body 31 is small.

Example 4

Using this example game, it is briefly described as by the method according to the invention a Tranrdstor can be made with a practically flat emitter junction and a base zone, the one below the emitter zone lying part is thinner than the rest of the base zone.

Similar to the exemplary embodiments already described, a silicon body 50 (Pig. 7) is countersunk Provided pattern that consists of a SiD.ituumoxidschicht

51 with an opening 52 consists. The masking layer 49 »

52 consists of silicon nitride .. The masking layer is used then partially removed, so that a ßcheibcnartiger Part 53 of the masking layer 49, 53 remains.

This can be achieved in the following ways. The part 53 of the masking layer is in the usual way with a Aluminum layer coated with a thickness of about 0.1 / µm. Subsequently, the part 59 of the layer 53 is removed by a sputtering process in a high vacuum. The pattern 51 becomes a little thinner. Finally, the aluminum is removed from part 53 of the masking layer by etching in nitric acid.

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The pattern 51 has a thickness of about 2 µm, for example. By doing If an impurity is diffused into the silicon body in a manner known per se, the pn junction is created

54 at a depth of, for example, 1.5 μm. By means of oxidation, during which the remaining masking layer has a protective effect, a silicon layer 55 (see also Pig. 8) is applied in the opening 52 to the part of the surface not covered by the masking layer 53. The oxide layer

55 is thinner than pattern 51 and has a thickness, for example of 1 / µm and is about about 0.5 / µm in the silicon body 50 sunk. The oxide layer 55 thus forms a pattern with an opening 56 that is sunk over half its thickness.

The masking layer 53 is removed as described above, and a pn junction 58, which is located on the already existing transition 54 connects, an impurity diffused. The pn junction 58 is, for example, in a would run from about 0.6 / mn. Next, to produce the second pn junction 59 at a shallower depth than the subsequent pn junction 54 and the junction 58, e.g. a depth of about 0.3 / µm, another impurity diffuses in. The depth of this second pn junction 59 is also less than the countersunk depth of the thinner ones Silicon oxide layer 55 in body 50.

After cleaning the opening 56 and producing an opening 60 (FIG. 9), the emitter contact layer 51 and the base contact layer 62, e.g., by vapor deposition Aluminum attached. A collector contact 66 can be attached to the underside of the body 50. Further For example, conductor tracks 61 and 62 with parts extending over the thick pattern 51 can be applied.

The result is a transistor with a practically flat one Emitter junction 59 and a base region 63 which has a thin part lying under the emitter region 64.

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According to the method described above, transistors can be used for high frequencies with a low base orbital resistance which, in addition, since contact 3chients 61 and 62 extend across the thick pattern 51, a small capacitance between these contact layers and the Body 50 have.

Example 5

This is an example of a method of manufacture a monolithic semiconductor circuit with a silicon body 70 (Fig. 10, 11 and 12), one surface of which is covered with an insulating layer 71 »90, on the conductor tracks 72 to 75 are attached, the through the openings 76 to 80 in the insulating layer 71 with zones 81 to 84 adjoining the layer 71 two circuit elements make contact, namely at a transistor with a transistor with the emitter, base and collector zones 81, 82 and 83 and with a resistor element with a zone 84. The zone 85 is provided in the usual manner only for insulation purposes. Conductor tracks 72 to 75 comprise contact areas 86 to 89, at which connecting lines are connected to the conductor tracks. For the sake of clarity is only in Pig. 12 shows a connection line which is connected to the contact surface 87. According to the invention, the surface of the silicon body 70 is first provided with a layer-like pattern of silicon oxide 90 provided, which is preferably sunk into the body 70 practically over its entire thickness. The pattern 90, which is formed in a strip-like manner has, for example, a thickness of at least 1 / µm.

It is then in a manner customary in planar technology with the aid of an insulating layer 71 which is thinner than that Mustex * 90 and which follows on from the pattern 90, the named Tra.nsif3tor and claw Y.'i (lcrstands .-- u.eT:>'->nt an ^ elir ^ oht. The 2'jonen 83 and 85 can already be installed before the

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Insulating layers 71, 90 are produced while the zones 81, 82 and 84 generated after the application of the layer 71, 90 will. The thin insulating layer 71 has a thickness of about 0.4 / µm, for example. An insulating layer of such thickness is often used in conventional planar technology.

The conductor tracks 72 to 75 are attached to this in the usual manner, with the contact surfaces 86 to 89 on the thick pattern 90 can be attached. The conductor tracks and the contact surfaces are made of aluminum, with it it is inevitable that there will be a thin layer of aluminum oxide forms on the aluminum.

In a common manufacturing process, the Semiconductor device tested, with contact pins against the Contact surfaces 86 to 89 are pressed with sufficient force to penetrate the aluminum layer. Included an insulating layer with the usual thickness of e.g. 0.4 µm located under the contact surfaces is easily damaged. The thick pattern 90 significantly reduces the possibility of such damage. Next is the possibility Damage even when attaching connecting lines 88 to the contact surfaces 87 is less. Pure one Number of circuit arrangements, it is also a significant advantage that the capacitance between the silicon body 70 and the contact areas 86 Ms 89 is small because of the thickness of the pattern 90.

The thin insulating layer 71 is made of silicon oxide and can be applied in the usual way after the masking s layer that was removed when the Pattern 90 is used in the manner described above in order to protect the silicon surface locally from oxidation. The thin insulating layer 71 can also consist of this masking material, for example if it is formed by silicon nitride will.

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It will be evident that there are more tmd / or other circuit elements such as diodes and field effect transistors in the silicon body can be accommodated. The mother 90 can be designed quite differently and e.g. formed by a ring surrounding the thin insulating layer, over which the contact areas are distributed. Can continue the pattern extend under a conductor track, which is useful, for example, when the capacitance is between the conductor track and the silicon body should be small.

Example 6 ^

Semiconductor arrangements are often produced nowadays, starting from a silicon body in Porra, a silicon layer attached to a carrier. The carrier usually consists of an insulating material such as Al ₂ O _5. The silicon layer, which can be polycrystalline or practically monocrystalline, can be applied to the carrier by depositing silicon. A number of circuit elements are then formed in the silicon layer such as diodes, field effect transistors with insulated gate electrodes and resistors attached * An insulating layer, e.g. made of SiIi ziurooxid can be applied to the silicon layer, on which conductor tracks can be applied, which are connected to the circuit elements in a similar manner as has been described in Example 5.

The circuit elements in the silicon layer can through Etching of a pattern of grooves in the layer electrically from each other ", the layer being divided into a number of sections, e.g. contain. This has the disadvantage that, because of the grooves, the surface is no longer smooth, and so are the grooves cause electrical leakage paths.

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In the case of a layer of one conductivity type, the insulation can be obtained by applying a pattern of zones of the opposite conductivity type, which zones extend over the entire thickness of the layer, whereby the layer is divided into a number of sections of the one conductivity type, each of which can contain a circuit element and are separated from one another by the zones of the opposite conductivity type. In this case, however, the zones of the opposite conductivity type can cause transistor scattering effects.

By means of the method according to the invention, electrical insulation is achieved which avoids the disadvantages mentioned. In this case, the silicon layer applied to a carrier is provided with a layer-like pattern of silicon oxide in the manner described in the previous examples, the oxidation treatment being continued until the pattern is applied. the pattern extends over the entire thickness of the silicon layer, whereby the silicon layer is divided into a number of sections which are separated from one another by the pattern.

In Fig. 13, the pattern of silicon oxide is 100, the parts of the silicon layer separated from one another by this pattern with 101 and the carrier with 102.

In the parts 101 circuit elements can be accommodated in the usual way and the whole can with a Insulating layer and covered with conductor tracks.

Of course, the invention is not related to the described limited exemplary embodiments, and within the Many variations are possible within the framework of the invention for those skilled in the art.

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The layer-like pattern on the SiIisruisöxiä needs e.g. not sunk into the siliaiu body beyond its ganae thickness to be. For a number of applications it is sufficient if the! button into the body over at least half its thickness is sunk. The pn junctions of e.g. a high frequency transistor can be applied to a greater depth than the depth of the recess of the pattern. There are then no flat pn transitions, but they do need it no openings to be provided in a thick oxide layer, while Met all layers with which connection leads must be connected, can lie essentially on a thick oxide layer (pattern), whereby the Capacitance between these metal layers and the body is low. Oxidation treatment can be used to obtain a pattern that is sunk into the body over practically its entire thickness interrupted more than once in order to preserve the oxide layer over at least part of its thickness to remove again.

Furthermore, before the pattern is applied, the silicon body can already undergo an etching treatment on the for the pattern intended positions.

Patent claims:

309827/0500

UMi - - '-

Claims (1)

-.24 - 1789U4 Patent claims: 1. Method for manufacturing a semiconductor device with a semiconductor body made of silicon with at least one Semiconductor circuit element in which a semiconductor top mife
surface with / an oxidation treatment of this surface with a flat silicon oxide layer in the form of a layer-like pattern of silicon oxide, which only partially covers one surface, is provided / characterized in that first one surface is locally covered with a masking that prevents the silicon from oxidizing and then the sexton is applied by an oxidation treatment, with at least part of its thickness sunk, that then at least a part of the masking layer is removed in order to expose the underlying surface part of the semiconductor body and that a metal layer is applied which has an electrical connection with forms at least a part of the surface part of the semiconductor body thus exposed and which also extends over the recessed pattern. 2. The method of claim 1, gekennzeiohnet characterized in that silicon nitride is used as the oxidation of the silicon veihinderndes material. 3 »A method according to claim 1 or 2, dadu rch labeled in ζ ei chno t that a masking layer is used whose thickness is smaller than the thickness of the pattern. 4. The method according to at least one of the preceding claims, characterized nzeichnet geke n that the pattern is lowered by at least 0.5 / um its thickness in the silicon body. 309827/0500 BATH ORIGINAL 1789H4 5. Method according to at least one of the preceding claims, marked by the fact that to sink the pattern over at least a large [ceil of its thickness in the silicon, body before applying the pattern of the silicon body one Protection in the places intended for the design ■■ is subjected and / or the oxidation treatment at least is interrupted once and the oxide layer already obtained during the Unxerbrechung over at least one i'eil its thickness is removed again. 6. - The method according to claim 5-, characterized in that the Küster is sunk into the silicon body over approximately its entire thickness. ?. Method, 'd-adur eh geken nzei Ohnet that the masking layer is removed after at least one of the preceding claims after the application of the pattern part. 8. The method according to at least one of the preceding claims, characterized in that the masking layer is completely removed. 9. The method according to claim 7, characterized in that a "'part of the masking layer adjoining the pattern is removed. 10. The method according to at least one of the preceding claims, d_au ure h- - gek e η η · λ e i ο h n et that the masking layer, or the ivuster made of silicon oxide by the use of one or more chemical process steps at least partially removed - whereby the pattern or the masking layer is attacked less quickly. 11. Vc? rf "'s her to at least one of the preceding claims, characterized gekemiMel ohne.t that a Munter nit riinclesteriü a (jJTnuii -; ov / a'-u;, is first ^ - 26 309827/0500 12. The method according to at least one of the preceding claims, thereby gelcennz el chnet that the semiconductor body with a epitaxially grown silicon bar is provided and the pattern is sunk over the entire thickness of this layer. -1-3 · Method according to at least one of claims 7 to 12, characterized in that after the pattern has been applied, the masking layer is at least partially removed from the surface of the silicon body and at least one impurity is diffused into the exposed surface of the silicon body » 14. Method according to claim 13, characterized in that after the application of the pattern, the masking layer is at least partially removed from the surface of the silicon body and at least one pn junction is produced by impurity diffusion through the exposed surface in the silicon body. . 15. The method according to claim 14- » characterized in that a pn junction is generated, the depth of which, seen from the surface, is less than the countersunk depth of the pattern. ...._. 16. The method according to claim 14, characterized in that after applying the pattern, the entire masking layer in the opening of the pattern is removed, by diffusion into the silicon surface thus exposed in the opening pn transition. is generated, the depth of which, viewed from the surface, is less than the countersunk depth of the pattern a diffusion mask in a part of the silicon surface in the opening of the pattern, an impurity diffuses is used to create a pn junction at a shallower depth than the existing pn junction. —_ 27 ~. 30S827 / 0S00 BADORIQrNAi. 17. The method according to claim. 7 and at least one of claims 13 "HNET to 16, characterized ge Flag with that exposed to the diffusion of the masking layer portion of the surface versenk-- of the semiconductor body by means of an oxidation treatment with an, at least over part of their · thickness ¹ 'th Siliziumoxidachicht that is thinner than the pattern. 18. The method of claim 17 »dadurc h in that the remaining after application of the thinner Siliziuifioxidsehicht part of the masking layer is removed and is diffused an impurity in the resulting exposed surface of the Siliziuinkörpers to produce a pn junction which is located at the already generated pn-junction connects, as well as an impurity to generate a second pn-junction, which is at a shallower depth than the mentioned subsequent pn-junctions than the countersunk depth of the thinner SiIiziiamoxidschicht. In that the electrical connection forms Schottky contact 19. The process according to claim 1, characterized in that a. 20. A method for producing a monolithic semiconductor circuit according to at least one of the preceding claims, as marked by that the silicon body is provided with an insulating layer which consists of the recessed pattern and an adjoining thin part that circuit elements are attached, of which semiconductor zones border on the thin part, and that on the insulating layer a metal layer forming conductor tracks is applied, which also extends over the recessed pattern. - 28 - 3: 0 982 7'705O0- J Cf.ü Z 28 -. \ im \ kk 21 ". The method according to claim 1 and one of claims 18 to 20J d a ^ iä ⁱ eh - gek ^ KM ^ e3r & ii ^ e ⁱ t-> that the metal layer forms at least one contact flat with the 'one Ih'schlussleiter connected v / erdeii can and which lies on the surface of the recessed pattern. " 22. ' Method according to at least one of the preceding claims; dädijreii g Ekeh nzeic-HNET - \ that eiiie on a substrate silicon layer is applied and during the isrzeügung of the pattern on this Siolit the oxidation treatment as long as fortge-A sets is, until the pattern over .the entire DieVe the SiliziünischdiDlit extends üiid this iii divides a number of parts separated by "the pattern of the hand!" BATH ORIGINAL