DE1774836C - Memory arrangement for a multichannel pulse height analyzer - Google Patents

Description

The invention relates to a memory arrangement for a multi-channel Impui-height analyzer.

The task of the memory in a multi-channel pulse height analyzer is that in /; Addresses the numbers of the pulses with a positive or negative sign assigned by an amplitude classifier η amplitude intervals in a specific measuring time. Each address is uniquely assigned to an amplitude interval. The numbers accumulated in the memory represent the frequency distribution of the amplitudes (amplitude spectrum; at the input of the Kiassic device. It is of particular importance that the spoke; has auxiliary devices with which the memory contents on a cathode ray tube or in the middle! analog form can be represented as a curve or with which the stored numerical values can be output digitally Previous measurements recorded distributions are retained without being heard by the current measurement. This is possible if the memory has a number of addresses, d '"t is equal to an integral multiple of the amphtude intervals of the classifying device, with several addresses in each amplitude interval w are selectively assigned. Such a divisible memory also offers the possibility of displaying several recorded distributions at the same time, possibly one on top of the other with the same amplitude scale, in analog form on a display device or using arithmetic circuits to add or subtract a distribution from a second one.

It is known as a memory for multi-channel in-lulsiiölK'ii analyzers electromechanical counters. electronic counting devices, drum storage. Magnetic tape storage or ferrite core memory. The latter in particular will cry almost exclusively used. Furthermore, arrangements are known in which a magnetostrictive or ultrasonic delay lines can be used as storage. These go back to a principle given by Hutchinson and Scarrot (fl), and they are one A number of works are known which deal with the improvement of the method (2), (3), (4), (5), (6). Although the use of a delay line as a memory in a multi-channel pulse height analyzer compared to a ferrite core memory, a significantly lower circuit complexity requires, a number of serious disadvantages are the reason for its low prevalence. Essentially, they concern the following points:

|) u · purely serial storage in a delay, diversion has a relatively long access time zur it.lüe and thus limits the counting rate of the pulse sequence to be analyzed, line analog representation of the contents of the memory , si just imprecise or with '.crhähnismiiMu - large Schakungsauluand niünlidi "

The writing out of the spoke information mil- u Is Zilferndrucker or -1 Sireifeniocher requires complex,: i / ierte and complex circuits, which 'practical and raise the advantage of the simple memory'

The memory cannot be divided into subgroups, e.g. B. two distribution 'in nt - ,,, below spoke.-sip umerzubrineen. '} _Ll -finding IiCAt the task / uurunde, eme irherauordnunn for a vidkaual-pulse height-. ,, viator mt dynamically circulating memory:,, U, u shadow. ' who avoid the above.acceptable disadvantages: and thus with little circuit open -., u! .iiLM has few kigcnschafien such as Änah - ,,, _K n with static memories. '

I) ₁ , foundation means that a group of. that several bits are input and read out at the same time (par-UeI) and the!: ;;! ,, content is always given by a. Darzu ^ Eidl circumferential succession of groups from occurring bit .mpu.sen this time a bit pulse is to be written., o is via the 'rcihcrver * tarM.r ,, a short current or Spannuii mpuls au uiy and / ögerungsleitung VLO specified. After Artum u delay time 7 a voltage pulse appears at the output cili l Hing, which is amplified by ueni l driver amplifier LT _n to the tolgenüt ve. zooerungsleilung I'L'O given and to ^u ßJ ^clL - · ". returned to the arithmetic unit weü M>·"'-,.,. ic to after the Verzoi'.crungszcit / ersciiciii ι ^ output pulse of the line VL 0 at the ^l - " ^cwlN ^ ' L whose output is also connected to the arithmetic unit (H") . F.in pulse S " thus has a pulse A" after a time T and after a time. .5 a pulse B "- a result On the other hand erg l γ η from the fact that z * ei signals A," and ß "at same time, contact au if 'ν, -ι-S'HU signals and λ u; borrowed distance T consecutive. the ^νΟΓί · £ ^η ^ "said applies smagemäB Auji for the further KlIUI the memory array. ι 1 in b-

in connection with the. Arithmetic unit, among others ·. 11 l.annt, r way the output signals of the \, ro _f L-rungslinien are linked with each other and with one of control signals, cr ^ .m si storage arrangement, in which several bits η an example given are four) ff ^ J ^^ and each bit can be read out several times (in the example shown /we.mal) -ehrend emesSpueh r cycle can thus st .-

":), e. the device arrangement according to the guideline for multichannel ImnuK height analysts offer opposite Anahsators with slaüschen memories have the advantage. "I, much less switching on, and. as he , n Jen traditional multichannel pulse height analog • vsato.cn is necessary in for an analyzer crucial points, which are listed under 1 to above, to achieve equivalent properties

a ₅

have a time gap. Dam ^ addressing .11 a Scrienspe rather order of a bit to a Ze .ntc which a certain en * e. f ^ a »^ plspe.chcrukt, g

eir.en /e.tliehen distance ^ tm to Addresses of the memory Vo exposed

the distance greater ^ * ^c ^

j-sch.,.,

The memory content therefore consists of a continuously rotating role of groups of * Bils each. This means that the current time is smaller in the ratio Vk than with a memory unit, capacity and clock frequency in which the information is stored purely serially. Furthermore, in the arrangement 5c according to the specification, several groups of k delay lines or shift registers each are switched in such a way that each group of k bit pulses can be read out several times during a main memory cycle. _rf

The principle of a corresponding memory array can

Süeicher becomes w.-iierhin "Λα, UmSn" of the one. "Tung ^ ¹ CT ί ϊ Si

eie Eg ^ - _o CT _tr , e

the channels stored u ^ ^L
niings- or J ^ orn ^
abbreviated DAW) henut /

at the output ^d ^ ^s ^% ^^ let output variable (current or

gen the dem1 by d «Bu

.. · Sp.i \ _{V: indlc!}

Please no

B with binary Zahk-nd; ··

Men with read and write amplifiers, connected in series, so that four chains of the same kind are created ""< _output signal of the DAW is added for two K bit C-runpe. Since in a serial

Values are derived. At k = 4 this corresponds to a time k τ (τ = duration of the channel pulse) delayed

2 ⁸ = 256 values, which is a maximum relative device and its length is τ, then the

Corresponds to an error of about 0.4 ^{n / o.} An example of a capacitor C charging. There is a

corresponding DAW is shown in B i 1 d 2 . Equilibrium voltage U (see Fig. 4). is

The four bit signals with the values 2 °, 2 ', 2- 5 r' = RC > τ, then C is

and 2 ^:> , which are discharged at the same time at the output of the deceleration by a small amount, \ U and

power lines of the memory appear, are recharged. U results from the

a resistor-diode network (4 bit DAW) drawing

and fed via the amplifier Kl to a sum y U - k {U ■ U \

Miervcrkraftker K3 directly (via the resistor R ') io'->''

as well as via the delay line VL by one for k - ■ 0 [that is, the sampling pulse (2) begins

Bit clock delayed and through the resistor 2 * R ' simultaneously with the starting point for channel 11

rated fed. At the output of V 3 one thus obtains U --- LZ ₁ ; for it - 1 (i.e. sampling

So for the duration of a bit clock a voltage that is impulse at the same time as channel impulse 2) results

which by two successive bit groups 15 U = LZ ₂ . For intermediate values O <Ξ k <? 1 is U a

the number shown. So that this voltage is a linear function of k. But this means that that

e.g. for the representation on an oscilloscope screen, the scanning method described linearly between the

is available for a longer period of time, a memory content of two adjacent channels is interpolated,

capacitor C charged through a sampling gate. If one allows the use of the scanning pulse

At a suitably selected time ao the delay range of 0 is slow enough

score, synchronized with the bit clock, opened. to T , then the memory contents

The synchronization takes place in such a way that on a coordinate recorder or line recorder

each for the duration of an address, consisting of represent. Due to the scanning process

several bit groups (e.g. 4), the voltage on conditional interpolation becomes a smoother

the storage capacitor is held. The Aus »5 Kurvei./ug received.

ganj, - ..; _e .. "> ΰ, .5 '.VoIlik>.i!> V 4 thus consists of The example of a circuit for the recorder of a stepped sequence of voltage levels. Control is shown in Figure 5. The one with the Peri-Bei 4-Bit -Groups per address and a bit cycle or duration T recurring sequence of voltage frequency of 4MHz beirägi the duration of such a level existing output signal of the DAW is level 1. These signals can be used for control 30 via the resistor R and as a switch in an oscilloscope tube the FET 1 is applied to the capacitor C.

When coupling mechanical components which an amplifier with high input resistance (e.g. coordinate recorder) must stand with the memory (FET 2) follows. The FET 2 thereby receives a lower operating speed 35 for the gate, which is caused by the slow design speed of the masses that follow the bias voltage at C. This ensures that the mechanical components are adapted. The operating point for the gate voltage is always retained. The impulse to open the switch (overfold between the frequency zero and a measurement impulse) is generated by the comparator 1 and the upper frequency, typical for each core memory, can be changed to the desired one using a univibrator (L / V) so that it can be achieved , 4 ° length (e.g. 1 \ ts) . The temporal use of the output voltage of a post-switching point of the takeover pulse changes so slowly in the second DAW that the recorder determines that the comparator 1 can follow the voltage change modes Analogue frequency / of series memories with delayed Digilal converter (ADC) of the analyzer «to the ampli lines rigid and cannot be changed. 45 necessary tudenklassierung and synchronously with derr this difficulty / handle and, therefore the current in the Spcichcr master clock sawtooth Gcneratoi ι riindunusgemäßen Ano ^r dnung a sampling circuit with a fixed combines a · with the DAC by means of a potentiometer (P), via which the output voltage of the DAW compares the voltage (slow sawtooth) and is transferred to a storage capacitor during an adjustable or with a slowly increasing address cycle. 50 whenever the voltage on the non-inverting i

The principle of this circuit is shown in Figure 3. The input (+) becomes greater than the voltage at the inverse

the resistor R, a field effect transistor animal () input, an output signal appears

(FET) and a storage capacitor C. With the potentiometer, one can thus be fixed

Antasic circuit formed, the phase relationship to suitably selected to the main clock of the memory

Points in time, the instantaneous value of the output voltage and thus the interrogation pulse is only true

well! iks DAW transfers to the capacitor C , trigger a fixed, preselectable address. With the

.iff which they then up to / around the next interrogation pulse at slow sawtooth can be achieved that de

Pun ¹ -1 2 is retained. In B i 1 d 4, the dot takeover pulse is slowly running through all addresses

ten I. 2 and 3 Zugchörice voltage curve shown. The comparator 2 indicates the end of the run-through

sets the standard output voltage of the 60.

DAW. which has a period T (circulation) The memory arrangement according to the invention brsit;

/ cit ilcr delay line), there is still a facility for digital output d (

Point 1. In the normal state, the FET is locked. As with any other Series 1

and the capacitor C is decoupled from the DAW. If memory is used, it is necessary to select the appropriate «cselectc

joitifcli the FlT by also separating the information into one with the peri- 65 points in time

o ^ cndauer T recurring signal at gate (2) to take over gc memory device, where it is so lanj

ülTnet. this is kept at the beginning of a bc until the corresponding trigger

there is a channel impulse at the output of the DAw * handling ( e.g. azs A.islcsen a digit of a digit

druekcrs) is finished. This can be done with a very simple Verlahreti can be used when the memory consists of four parallel chains. In such an arrangement As described above, four hits can be read out at the same time. There four bits when storing binary coded decimal numbers (BCD-Codc) one digit of a decimal number, or with A purely binary number representation one digit of a hexa-div.imal number represent, the otherwise necessary series parallel converter can be dispensed with. In the device according to the invention, the 4-bit memory is formed from four capacitors, and the Takeover takes place in a similar way as in the device shown in Figures 3 and 5 analog output.

The mode of operation is as follows: As already described, the memory content consists of groups of k bits (/ .. B. four), each of which occurs simultaneously at the output of the arithmetic unit. The groups appear at a time interval of one bit cycle. The bit clock frequency is synchronized with the circular frequency of the memory (main clock). This means that a certain bit group appears to be delayed by the same fixed time compared to the main clock every time the disk is circulated. Multiple groups represent one number; together they form an address, the limits of which are determined by the channel clock. The value of the groups increases with the chronological sequence. If you connect each of the bit outputs of the memory arrangement (e.g. the outputs 5 ° to .S = ¹ in Figure 1) via a sampling circuit according to B i 1 d 3 with a storage capacitor C "and leave a sampling pulse slowly enough to open the delay range T to 0 compared to the main clock pulse (Γ period of the main clock), the individual bit groups can be queried in this way and their content transferred to the storage capacitors Overlap group as in B i 1 d 4

In the principle shown, the capacitor C is charged to the voltage of the applied bit pulse if the sampling pulse is narrower than the bit pulse. The encoded numerical values of the individual addresses (digit for digit one after the other) are thus available on the capacitors for a time which can easily be adapted to the operating speed of the printer. The printer is controlled in a known manner via a Umcodierur.g and electronic switches.

Bibliography:

(1) Hutchinson and Scarrolt,
Phil. Mag. 42, 792 (1951)

(2) Mc. Kibben, Gallagher and Lang,

* 5 IRE Convention Record 3, Pail 10.186 (1955

(3) Emmer, IRE Convention Record 3, Part 10,

211 (1955)

(4) Takaba, Nucl. lnstr. 58, 223 (1968)
(5) Bunacic.Nucl.Instr. 42, 154 (1966)

(6) Oslertag, Lauterjung, Gruhlc,
Nucl. lnstr. 16, 301 (1962)

For this purpose 2 sheets of drawings

309 63

Claims (5)

Patent claims: 1. Storage arrangement for a multichannel pulse height analyzer, characterized in that a group of several delay lines or shift registers a, are operated in parallel in such a way that each several bits are written and read out simultaneously (in parallel) and the memory content by a continuously revolving sequence of groups with a given period jus several simultaneously occurring bit pulses is shown. 2. Memory arrangement according to claim 1, da- ^ s marked by !, that several of the groups Min delay lines or shift registers are connected in series so that the memory information an address is read out several times during a period of the memory act. 3. Speiiii .ranordnung according to claim I or 2, characterized in that it comprises a hinrich-! Ung Ahlen values for display stored animal / voltage or current values has (Digital-to-analog Wandlei \ which the Aiialcig by a digital-converter i. 'r k simultaneously applied bit pulses output signal / u is added to the output signal of the same converter, delayed by a bif clock and suitably attenuated at the previous bit clock, and the analog value thus obtained is transferred to an analog memory device by a sampling circuit and for the duration a memory address is held and, with the simultaneous conversion of only 3; -, A: üits, an assignment to one of the levels represented by 2 A bits takes place. 4. Memory arrangement according to claim 1, 2 or 3, characterized in that it is in connection with a Digit'il to analog converter one Has sampling device, which the output signal of the digital-to-analog converter during each period of the storage cycle at a certain point in time, calculated from the beginning of the storage cycle, into an analog memory device via- +5 takes and holds there until the next scanning process, the time of the takeover by a DC voltage is determined, which automatically runs through a selectable range! writing out the memory information as a label on a writing registration device takes place, and that the scanning device automatically a linear interpolation between the makes step-shaped output levels of the digital-to-analog converter. 5. Memory arrangement according to claim 1 and 2, characterized in that a device is used for digitally writing out the memory information by means of a Zirferndrucker or strip punch in which the contents of the bit groups representing the memory contents are successively transmitted to storage capacitors via a scanning circuit by the gates the sampling circuit can be opened briefly with a delay ta compared to the main ^{clock pulse of the memory with the δ} 5 period T and / runs through the range t-T to f = 0 continuously and slowly enough so that the information is present on the storage capacitors as long as for Control of the printer or strip punch is required.