DE1774513C3 - Circuit arrangement for determining the priority ratio between several request signals for program-controlled data processing systems - Google Patents

Description

1 774 5 I 3

The other is in the ^{display lift I 26 1} J 394 Fig.

eim circuit arrangement for determining the upstream system,

Ratios according to priorities between several Fig, 2 a demolished diagram of the priorities Priority request signals by enabling control circuit and

a priority with a corresponding priority 5 Fig. 3 is a detailed circuit diagram of the in Fiel as

Start signal belonging to the request signal for the circuit symbol 20 shown per block.

Program-controlled computing systems have been proposed in the exemplary embodiment described

that is characterized by the fact that it is used to transmit four transmission channel control devices to a group

Mood of the priority ratio of priority of service or storage cycle request request signals from several levels of io signals and four processing elements into one

Circuit modules with locking and unlocking validity for the further group of storage cycle request

there is that inputs for the pre-signals are combined in the levels. It needs to be emphasized, however

Rank request signals and outputs for which the present invention is not in any

given start signals are present and that the manner in the particular configuration shown is electrically restricted to one another forwards and backwards and is suitable for any arrangement in

are tnsch coupled. the groups of operating signals on the basis

This circuit arrangement has a structure that is very homogeneous with a priority list and the timing of occurrence, which is to be evaluated in particular. The thick lines in Fig. I represent implementation with the help of the integrated circuit several parallel signal paths, while the thin lines are very well suited, but it has the disadvantage of basically simple signal paths and that they show the timely arrival of the request ,
signals not taken into account at all. Fig. 1 shows an overall block diagram of a pre

The invention is therefore the task of priority control according to the present invention,

reasons to set up a circuit arrangement for determining the number of processing elements or central

the priority ratio of request signals, 25 len processing units (PE) or more

which enables external units of a data processing transmission channel control units (CC)

management system can be supplied to create that is supposed to have access to memory cycles of a shared

both to maintain a predetermined priority ratio of the driven storage unit. According to the

incoming request signals as well as the representation in Fig. I represent the priority selection and

temporal arrival of the request signals continuously 30 control circuits according to the invention the priority for

taken into account, so that each request signal into the memory selection signals of up to eight users

within a certain time, even if there are concerns from both the PE group and the

Process request signals with higher priority CC group and generate control and data

let will. Transmission signals on the basis of an evaluative

The inventive solution to the problem is dialing signals. Each election signa is rated or

means that due to their priority of the one assigned to a storage cycle according to the priority

Priority control circuit selected requirement scheme of the priority selection and control circuit

signals are passed to a test circuit where gen. The priority scheme works on the principle

a second classification is made that the voting signals are based

Conductive arrival of the request signals on line 4 "1. on the arrival time of the request signal

Considerations taken into account that the test circuit one and

Distribution control and a time control connected downstream 2. on the relative importance of the requirement

which are responsible for the forwarding of the request signals with respect to the request signals of the

for storage unit control when there are several other users.

rer equal request signals serial 45 In addition, the priority scheme divides the memory controls and when the cycles arrive at staggered intervals, so that a maximum memory access er request signals on the lines this is possible.

The order of their time of arrival forward, the switching operations of the priority selection - and that the test circuit a test control circuit control circuits is assigned to the three main functions, depending on the memory status $ 0 , which are shown in Fi g. 1 are shown:
tus and emits a clear signal from the storage cycle to the 1st order of the request signals according to the priority test circuit, which indicates that the request is made
gna! the next storage cycle, the 2nd priority check and
on the basis of the classification and distribution 3. Storage cycle control.

the highest priority 55 The circuits for the first part of the selection are

has. giving each request signal a user priority

The circuit arrangement according to the invention to rities based on the type of user who

Determination of the priority ratio has the priority issues the request signal and dtm from this

part that although request signals with highest user received request signal. the

Priority are processed immediately, but that also 60 priority checking circuits examine the first

Request signals with low priority within voting schedule before the allocation of each memory cycle

can be processed in a definable time, without any clue and determining which user of this cycle

that pending request signals are to be assigned higher priority. At the end of a priority check

the processing of these lower-order instructions did the memory cycle control circuits

could interfere with demand signals. 65 storage cycle and generate during this whole

The following is an exemplary embodiment of the ore cycle control and data control signals.

Finding described in more detail on the basis of the drawings

ben. In the drawings, the PE request signal c and the appearing indicate

the lines II appearing CC request is present, these are done by the selection lock 12 signals through the selection lock 12 and divided, the then corresponding signals for the priority control circuit 18. Although the CC and PE units via the lines 16 and CC units assigned different classifications for the PE users via the lines 17 to the test systems and send a CC user request signal to the circuits 15. The priority control circuit can provide much higher priority, as will be determined in the following, which of the divided PE and subdivisions will be described in more detail, the overall CC requirements by the selection lock 12 on the allocation scheme for these divisions is similar. Lines 16 and 17 are allowed to run in order to wait for the allocation of the next storage cycle in the testers within the groups of CC and PE user circuits 15, that is, the priority control by the selection lock 12 for a specific circuit 18 ensures that the request signal also appearing during a user request signal from the setting period is transmitted. which was previously allowed to send the request signals to the lines 16 and 17 to which the rer user was allocated. Within a corresponding test circuit 15 for processing CC group must be switched on when allocating the first selection 15, and that all allocation received afterwards are also taken into account when a signal is stored so that a user will later allocate a request signal of high priority to them from storage cycle can be,
are. Since a request signal of high priority means that if several switches in the selection lock 12 have been switched on to a CC user anyway a great urgency and input signals to the request, other face test circuits 15 will have given the points, such as arrival time and status, Such an input distributor 20, to which this forward request signals up to this point have basically been ignored and the autogenous request signals the next memory enzymatically allocates the highest first selection division. klus is actually assigned. If, of course, a first selection signal always receives a relative memory cycle, no request signal is tiv low priority, and the following as approved. The circuit 22 for the .Speicherzu -evaluation of the division takes place at different levels, i.e. it generates an "allowed" output signal, and is mainly dependent on the comparatively if a storage cycle for the test control circuit sen status of other selection divisions, such as is available. Receipt of the "More specifically from the description of the shown in Fig. 1" signal generates the test control circuit 24 a th circuit shown. 30 "Test allowed" signal for test circuits 15,

The input signal assigned to the distributor 20 is then assigned to a request signal.

The first elective division let those on lines 16 ben.

and 17 generated output signals of the selection- If the distributor 20 fails, signals can

lock 12 via the test circuit 15 only the highest testifies, which indicate that more than one response

Allocation schedule for the next memory cycle 35 request signal is taken into account. A circuit

reach. The distributor 20 can be designed for multiple execution recognition

the. that recognizes that all divided CC request signals fall however and an input signal on the

processed before any scheduled storage device controller 28 gives that this

PE request signal is reached. The memory indicates such an error. Then everyone would

unit control 28 generates time-limited signals 40 test circuits 15 cleared and the signals ran

to control the flow of data between memory again up to distributor 20. If this

and the user assigned to the memory cycle a new attempt at determination by the circuit 25

and to prepare the first election schedule for multiple execution detection

and the selection lock 12 for the next priority multiple reception is removed is by a

check what a system error signal in connection with the time control 29 45 circuit, not shown

he follows. generated.

As already said, the processing element after selects a certain request signal ment PE, which was allocated a storage cycle to the system via the lines 10, gives the storage results Promotion signals. while the channel unit control 28 sends a clear signal for the control CC the request signal entered via the lines 11 to both the selects request signals. All of PE or test circuits 15 a.'s also on the selection lock CC input request signals are set to 12 so that other units are now involved Selection lock 12 given, which the requests. If after operating a request signal For processing and the subsequent signals, there is still a divided output signal divide the test cycles. The PE request 55 of line 16 or line 17 or both signals In addition, a new test is initiated on the lines 10 directly to the test circuits or test switches 15 to serve further open requirements. the give so that the processing elements at minima- circuits in the distributor 20 and in the Priifschal-Ier Line delay a memory cycle allocated to device 15 of the next served request signal can get if through the selection lock 60 are deleted, and the system determines whether further 12 no divided dial signals are generated, divided request signals on the lines d. h .. if only one processing element a 16 and 17 are pending. This process continues until Memory cycle requests and no other PE or all request signals are served. For this CC request signals are present, the allocation time can be all open requests that are in ment of a memory cycle via the test circuits 65 of the selection lock 12 were stored, but still 15 start immediately. do not get on the output lines 16 and 17

However, if at the entrance for the selection lock were allowed, divided and nod to the memory zy-12 a CC request or a PE request is distributed.

The control signals and dimming pulses that are emitted to control the control lines, and the request signal given to the memory together with the output signal of the time control 29 are only used for the usual control of the Spr ^ hercycles and are not described here in more detail, as they are well known.

. The circuit of Figure 2 is constructed so that Speichcrzyklen two groups are assigned by asynchronously requesting machine on the following basis: A group has priority over the other, priority of the machines within the Gri'-p ⁿ tid waiting time of machines within a group . The two main groups are referred to as users, also referred to below as users, with an even and an odd code. The users with the odd germ counts 1, 3, 5 and 7 are typically those associated with FIG. 1 mentioned channel control devices, which have priority over the users with an even number 2, 4, 6 and 8, which are the processing units mentioned in connection with FIG. In the group with an odd key figure, there is also a subgroup of users who have the option of choosing a high priority. The priority within the even and odd groups is hardwired on the basis of 1, 2, 3 etc., can be changed manually Obviously, if more than one high priority selection occurs at any point in time, the decision will then be based on the hardwired priority.

In addition, within the even-numbered and odd-numbered groups, dit; Storage cycles assigned to the base of the first arrival if the time difference between the storage requests is greater than three switching delays and is not a high priority for the odd-numbered B ^ user group is present.

The allocation of a storage cycle requires two levels of decision-making. The decision on the first level switches on the user's test circuits. and the decision on the second level leads to an output signal of the distributor 20.

F i g. 2 shows the special circuit that is used for an odd number and an even request signal is used. Although details of this Circuit for the odd-numbered users 3, S and 7 and the even-numbered users 4, 5 and 8 are not shown, their circuit connections are shown. Users 3, 5 and 7 have a special circuit analogous to that for user 1, while users 4, 6 and 8 have a Have circuit analogous to that shown for the user 2. First turn on the Test circuits for the odd-numbered users are considered. The one coming in on line 30 The request signal turns on the first selection circuit 31 (i.e., the selection circuit 31 on the first level). Assuming the AND circuit 32 is switched on, it is now through turning on the selector circuit 31 turns on the selector circuit 33 of the second level, d. H., the selection circuit 33 is switched on via the AND circuit 32 as long as no other request signal from an odd-numbered unit has its selection circuit the second level is switched on for at least three delay times before this point in time has.

If a request signal of high priority appears on line 35 together with a request signal on line 30, the dialing sound is activated 36 switched on with high priority because the request signal on line 30 and the

ίο Switching on the selector circuit 31 together the Switch on AND circuit 37 w.id so the switch-on enable the selection circuit 36 with the high priority.

The user who gives a request signal on the line 30 becomes one for the allocation; Memory cycle provided as soon as its test circuit 40 is switched on. The real control for the activation of the test circuit 40 success! by one of the three AND circuits 41, 42 or 43 via the OR circuit 44. The AND circuit 41 is activated by switching on the selection circuit on the first level 31 conductive, if no other selection circuit in the second level of an odd number User is turned on, no high

The high-priority selector is switched on and a "check time" signal from the OR circuit 47 and the inverter 49 is received. This means, any second level selector that is on within the odd-numbered users will switch the AND circuit 41 off, so that no selection circuit of the first level with a switched on Second level selection circuit within the user group can compete. It should be noted that the switching on of the selection circuit 36 with honet priority, which takes place via the OR circuit 45 must result in a sufficient time delay to keep the AND circuit 41 still switched on, if the selection circuit 31 is switched on, see that its test circuit 40 is only switched on.

if no other selection circuits are switched on. The AND circuit 42 is turned on by the Second level selection circuit 33 switched on if no high priority selection circuit is switched on and a permissible test time pulse

was received. If any other second level selector switch is made by one of the users, 5 or 7 is turned on, the AND circuit 32 is turned off, and the activation of the dei Selector circuit 31 does not lead to the activation of the

Selector circuit of the second level 33. The AND circuit 43 is activated by the selector circuit 36 with high priority and the permissible test time pulse switched on. This allows the user, the the request signal on the line

30 directly with the others for the allocation of a memory cycle that are switched on compete regardless of whether the Elective sound on the second level 33 switched on is or not, the OR circuit 46 switches the

similar AND circuits 32 for users 3, 5 and 7. So if that's on the line 30 generated signal has switched on the selector circuits 31 and 33 before one of the other users 3, 5 or 7 had time to switch on the corresponding second-level selection circuits the user who issued the request signal requests the allocation of a memory cycle and receive the priority in his group,

c 111 fΛ in the meantime no signal higher Priority aiillrill.

After the user 1 has been assigned a memory cycle a cancel signal for this user L! / eui: i, diis the circuits 31, 33 and 36 is echoed back. A similar deletion signa! is generated to switch the test circuit 40 back.

So control AND gates 41, 42 and 43 and their counterparts for users 3, 5 and 7 the setting of the test circuits for the respective User based on an existing high priority request, the activation of a test circuit the first or second level or just the first level. Which in a period of approximately three switching delay signals can be used to switch on more than one Lead test circuit, as a result of which a disconnection via the connection trunking circuit 50 is required will.

The soundings of the even-numbered users work similarly, with two exceptions, which are that there is no possibility of the high priority requirement exists, but there is a direct connection for the incoming request to the test circuit, i.e. when the user 2 receives a request signal on line 60 and no other request signal from another even-numbered User was received, the AND circuit 61 is switched on, which is then via the OR circuit 64 turns on test circuit 62. As a result, the user 2 can make an allocation directly of a memory cycle and give a quick answer in the event of a memory idle. The AND circuits 61, 65 and 66 control the activation of the test circuit 62 based on the level of the request signal, d. This means that the activation hangs within the even-numbered user group the circuit 62 depends on whether a second selection circuit is switched on, a selection sound the first level is switched on and no selection circuit of the second level or whether just an ordinary one Request signal was received. As before, request signals c lead to the activation of several test circuits, so that the allocation of a Memory cycle is decided again by the connection / disconnection circuit 50.

Each of users 4, 6 and 8 has first and second level selector circuits as indicated by the Circuits 68 and 70 for user 2 are shown. Also, every user has an odd number via a high priority circuit, which is not shown for the even-numbered users. A signal on line 60 activates the first level selection circuit 68 if no other user has already been used the selector circuit of the second level has switched on to the selector circuit of the second level 70, there the AND circuit 69 is turned on. If no other selection circuit of the second level is switched on is, the AND circuit 65 is conductive and the test circuit 62 is switched on. However, if a Another selection circuit of the second level is switched on, so that the AND circuits 61 and 65 are blocked are, but the AND circuit 66 has not yet been switched off, is activated by switching on the Second level selector circuit 70 also turns circuit 62 on so that user 2 turns around Can apply for allocation of a storage cycle. Thus, the input signals are for the OR circuit 71 the output signals of all selector circuits on the second level for users 2, 4, 6, or 8 and the input signals to the OR circuit 72 the output signals from all of the selection circuits first level for users 2, 4, 6 or 8.

The permissible test time signal is a time control signal for switching on the test circuits, which the various AND circuits 41, 43, 61, 65 and 66 can be switched on. The permissible The test timing signal through the OR circuit 47 and the inverter 49 is output when the memory control circuit signals that it is not busy and the signal is not given if there are three switching delays after switching on any test circuit. After the test circuits have disconnected, the connect / disconnect circuit 50 makes the final decision as to which user is the next to have access to a storage cycle. The only criterion on this Level is db priority of the odd user over the even user, and then the user with the highest priority is specified within the respective group. Thus, all of them become odd Users whose test circuits, e.g. 40, are switched on, from all even-numbered users operated, their test circuits, z. B. 62, are turned on. If it is assumed that the Test cycle activations of the second level are served, however, all test circuits of the second Level of both groups served before the selector circuits of the first level of a group select the second level and thus apply for the allocation of the next storage cycle. It should be noted that the setting of any test circuit in either of the two groups of in F i g. 2 only depends on factors within the respective group. Thus can z. B. test circuits of the second level switched on in the odd-numbered group (e.g. circuit 33) with the directly switched on test circuits in the even-numbered group (e.g. switching on of circuit 62 by an output signal through AND circuit 61).

After a request signal has been tested and operated, all test circuits and all selection circuits by the test circuit clear signal from the memory control unit for the user deleted, which is allocated the first memory cycle. This allows everyone to be switched on and still outstanding second-level test circuits and high priority circuits are served.

F i g. 3 shows a typical connection / separation process, Also called distributor in Fig. 1, in particular taking into account user 2, which is a request signal on line 60 in FIG. 2 outputs, which turns on the test circuit 62. Its output signal is applied to input terminal 80 in FIG. 3 and switches the AND circuit 81 a. As stated earlier, all of the odd users 1, 3, 5 and 7 are turned on Test circuits operated before those switched on for the even-numbered users. Thus, through switching on a test circuit, e.g. 40 in FIG. 3, for one of the odd-numbered users I, 3, 5 or 7, an input signal is given to the OR circuit 82, whereby the AND side 81 is switched off will. However, assuming that none

odd-numbered test circuits are switched on, give the other test circuits of the even group their input signals to the terminals 83, 84 and 85.

A permanent reverse voltage is applied to terminal 86 and a second turn-on voltage given to terminal 88. It is assumed that the user 2 is among the even-numbered Users has been given the highest priority. Then each of the AND circuits 90, 91 and 92 has a direct connection, e.g. B. 93, to the blocking line 86. Thus, switching on a test circuit generates for a user with a lower priority, in this case users 4, 6 or 8, no output signal from one of the AND circuits 91, 92, as a result, no output signal appears at the OR circuit 94 and AND circuit 81 remains on. So if no test circuits of the odd-numbered users are turned on and all lines to AND circuits 90 and

92 run as shown, the AND circuit 81 is switched on, so that the switched on Test circuit for the user 2 can emit a signal on the line 80, whereby at the terminal 95 an output signal appears. This output signal indicates to the memory control circuit that the User 2 is to be assumed and a memory cycle must be assigned to him. A similar dei-like one The circuit is the odd number for the test circuits User to use. If the user is 4 in the even group the highest priority is to receive, the connection 93 is placed on the terminal 88 and thereby an input of the AND circuit 90 is continuously switched on. If both test circuits for users 2 and 4 are turned on, the AND circuit 90 generates an output signal, whereby the AND circuit 81 is turned off and thus the allocation of a storage cycle to user 2 is blocked until a loading

ao service request from the user 4 is taken into account.

1 sheet of drawings

Claims (2)

ι ^ 2 Vorraiig circuit arrangement or by micropro- Patcntunspriichc: programs controlled so that the requirements do not the ability of the Di-ter.crariicitungssysteTiis to respond I. Circuit arrangement for determining the requirements to address exceed. Priority relationship between several requests 5 Namely, requests at the same time request signals, which from the various by an operator via a control panel, a Incorporation of a data processing system, such as a request by a tape unit, which data external storage devices or input and output supplies, a request by a tape unit, Begcrät for the purpose of controlling the connection which accepts data and a request setup between the requesting unit and a card punch, which is used to punch the next the central unit or the memory of the data card is ready. Some of these request processing facilities generated and the ordering signals must be processed immediately so that certain priority relationships are temporarily stored - the capacity of the computer system is fully utilized, can be cherted, with the request signals ent- and other request signals can in turn speaking the priority marker assigned to it 15 wait a certain time until your request is settled painting can be ordered, thereby being identified. indicates that due to their precedence of For the section-by-section processing of several the priority control circuit (18) selected grams with different priority is by the Request signals to a test circuit (15) German Auslegeschrift 1 202 034 a control switch where a second division has been made known, which is assigned a seniority which is characterized by the time of arrival of the tuners who received the input signals Request signals on lines (16, 17) are connected to priority channels, still through one takes into account that the test circuit (15) has a priority comparator to compare the priority of the and a time control (20, 29) following input data, switched by one of the priority are the forwarding of the breaker-controlled breaker and through request signals for memory unit control a read-only memory, from which the sub- (28) if there are several equal breakers, a command sequence to determine the after Control request signals serially and in case of interruption of the processed program staggered arrival of the request is called. This circuit arrangement has Signals on the lines (IG, 17) also show a waiting list register in the sequence in which the entry sequence forward their time of arrival, fende, a program interruption demanding si- and that the test circuit (IS) combines test control signals into a waiting list, circuit (24) is assigned, which takes into account this known circuit arrangement According to this, the assigned priority association takes one time from the, storage status and storage cycle Free signal to the test circuit (15) emits, 35 ratio of the individual programs and on the other that that request signal has the next priority, d. H. the time jr .. of a specific allocated memory cycle, which is based on the program or a request from an external Classification and selection of the device. has been assigned the highest priority. This circuit arrangement is not in the 2. Circuit arrangement according to claim 1, there- 40 position, request signals that have been a long time ago characterized in that the distributor (20) is to be taken into account when request signals a sensing circuit (25) for multiple reception of higher priority are present. is downstream, which responds to the fact that more through the German Auslegeschrift 1 189 294 isi as a request signal at the same time consider a further priority determination device for . is seen, whereby a repetition of the real-time system became known, the goal scarf entire process is initiated. controls the input and output Information about one or more of the single and Control output signals. She is also dadurri characterized as being a sub-priority facility 3 ° which includes signals from the Ein The invention relates to a circuit arrangement and output units that control the time to determine the priority ratio between borrowed succession of channels determined, üei several request signals that can take place from the various data transmissions, different units of a data processing system. Although this circuit arrangement reduces the time location, how external storage devices or input and 55 borrowed order of the channels is determined, is Output devices, however, this circuit arrangement is not able to control the connection structure between the requesting unit and the both certain specified priority criteria, di < Central unit or the memory of the data processing of the importance of the operator to be carried out generation system and which depend on the order of certain as well as the time sequence of the arrival Priority relationships are temporarily stored, 60 men of the request signals are taken into account, whereby the request signals according to him. B. happen that an An assigned priority features. Request signal with assigned lowest priority In a data processing system, time almost always has to wait because priority requirements occur At the moment there are different request signals with regard to information signals with a higher priority. this the data processing capability of the central unit 65 distribution of the priority relationships is not, however of the input and output devices and the external optimal, since for external devices or programs mi Devices on. These requirements will arise in the case of the lowest priority waiting times known data processing systems by one that is no longer justifiable.