DE1762007A1 - Pulse decoder - Google Patents

Description

J762007

Applicant: Stuttgart, March 1st, 1968 A.Cο Coseör Limited ¥ 1767 S / kg The Pinnacles Elizabeth Way Harlow, Essex, England Pulse decoder

The invention relates to a pulse decoder with a shift register, since it has a plurality of stages, a 'PaktBignalq, source ₉ which serves to increase a first input iinpul β in the register by a certain number of. Shifting stages and thereby delaying them by a predetermined interval, and means for determining a coincidence between the delayed output pulse and a second input pulse Sa Such pulse decoders are used, among other things, in Hadar response beacons.

009816/1561 _{# / #}

BATH ORIGINAL

The exact world position of the delayed signal is determined by the phase of the actual signal beatinat »velohee daa shift register. The onbeat belt represents the phase that the signals received, the clock proper can be large enough, among other things, that the disgruntled signal begins and ends at times, taking into account the required tolerances, including a second correct signal as the first correct time signal having su accept · Beiapielnteiae beaitat an aekundärar query · aender of a radar monitoring system a number of query modes, which distinguish through the Abatand eviaohen airei impulses, which is nominally 5 bsw · 5ι 8, 17, 21 or 25 / * e. Bine time -trarde demanded internationally that a eingeetellter a beetiitmten Mcdua.? Lcgseugempfänger anauflpreohäa has "wena of Iapulaabatand within + 0.2 ^ e dee rated value, he may appeal jedooh niohfc _f when the Abatand AEBR ala + 1 / la tob nominal value deviates. Dae means that ffennabatand in united / on S ^ e had ansuepreohen the Esipfängar when the Abatand awlaohen 7.0 and 8.2 ^ 3 was · If jedoob Tsrtiepalfle of 1 ^ a Tarwandat were able "to result; the approximation of the feraögaritng a Auagangasl ^ nul in the time interval of 6, d to 9.2 / & e (ie 7, H < to 6.2-t- 1 ^). Diraufc results in aioh that lapulse outside the world

009816 / 1SS1

the limit of 8 + 1 pA distance could be decoded; this was unacceptable.

The international requirements for such tolerances are now even stricter than before and it is now necessary to ensure that an interrogation property is always accepted willι if the distance between the received (| Signals H + 0.2 / ms, but is always rejected, if the distance is not within M + 0.8 / µs, where H the denomination is »

A known method of reducing the uncertainty of the delay is to use two shift registers and clock signals of the same period but opposite phase. This reduces the uncertainty to half of the clock period _s if the output signal is taken from an OR gate, which is connected to the outputs of the registers, the input pulses have a certain acidity with regard to the clock pulses and the first stage of each register is only set, if they overlap a clock pulse and an input pulse «This method has the main disadvantage; that it requires two registers "

009815/1561

»762007

The invention is based on the problem of “uniqueness able to use βineβ delayed pulsesβ only • ineβ registers all delay line of a yarn reduce to a part of a clock period su.

The object is achieved according to the invention in that the input level dee 8obiebiertere on one input - pulse and the clock signal responds in such a way that the set levels of the register form different patterns, if the input pulse different phases in Besug on the clock signal, and that a gate circuit so with a Number of register stages and the clock signal source connected are, that they are delayed depending on the various patterns formed by the set stages Output pulses during the different phases of the clock proper deliver".

The clock signal source preferably supplies a square-wave signal, which has a duty cycle of 1: 1 and whose half-periods have a duration which is essentially the duration of the input pulses equal to or an odd fraction of the duration of the input pulse 1st. The pattern formed is then as shown below will depend on the input pulse

009816/1561 * ^A

BATH

was received during the first or second half of each clock period. If, like UbIiOh _9, one state of the stages is denoted by "1" and the other state by "o", the pattern will ^{depend on the number of "1 H's} " which follow one another in the register.

In one embodiment of the invention, a Eingange- M circuit is provided which, when it is supplied with an input pulse, generates a first control pulse, which is compared with the clock period is short and is used for setting or setting of the first register stage. The input circuit generates a second control pulse when the input pulse is applied during the second half of the clock period ο The second control pulse is used to set the first level of the register again, after the "1" state caused by the first control pulse to | second stage has been transferred »

If a step in the state 1 is "1 ^M, one of a""appears corresponding output signal to a designated Q output whereas, one of a" appears 0 "corresponding Ausgangesignal to einsm other, designated by% output and vice versa _t when the level in the state "Ο" is »

009815/1561

BATH

If the half-waves of the Taktaignalee of the same Sour as the input impulses are and when aimed is that an input pulse that occurs during any Time of the clock property is created Output signal after a nominal delay v * n of an integer If the result is multiples η of the clock period with an uncertainty of one calving period, then the gate circuit can a first AND gate with inputs, the bits to the Q output of the (n + 1) th stage, the Q output of the nth Stage and the clock generator are connected, included, This first gate delivers an output signal when the »wide half-wave of the clock signal arrives. Also includes the circuit has a second AND gate with inputs, which sit the Q outputs of the (n + 1) th and the (n + 2) th stage are connected.

The delayed output pulse can be monostable by sine Flip-flop are stretched so that a delayed signal of the required length results. However, the use of this is monostable multivibrator undesirable, because the end of the stretched signal of the stability of the monostable multivibrator » level depends and is not determined by the clock signal.

009915/1561

BATH OWQINAL

In addition, even the beginning of the delayed signal Ton can be subject to certain uncertainties if one relies on the propagation delays in the circuit for the exact positioning. This Hangel can be overcome by, is formed as the gate circuit, which cooperates with the shift register "that it supplies an output signal whose period is an integer (^ multiple of half the clock period. Each of the delayed signal required adjustment of the phase or the duration is effected by using a synchronous signal with a frequency that is an integral multiple of the frequency of the clock signal.

Further details and embodiments of the invention can be found in the following description: in which the invention is described and explained in more detail with reference to the exemplary embodiments shown in the drawing. The features to be taken from the description and the drawing can be used in other embodiments of the invention individually or in any combination _o Ee show:

Fig. 1 is a block diagram of a Impulsdecodierers according to the invention _t

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ORIGINAL

Fig «2 the block diagram of a logic» which in a modified form of the "decoder" according to FIG can be applied, and

Fig. 3 is a block diagram of another pulse deodlerere according to the invention.

The decoder according to FIG. 1 contains a shift register the bistable stages 10 to 17 »in which cycle pulses P Tone consistent waveform, equal half-wave duration and a period of 1> * β input from a generator 16 will. Negative input pulses with a duration of 0.5A * are applied to terminal 19 and continue with the Kolneidsnftschalt 20 and au the first stage 10 of the register, where they set the Q output of the first stage to "1" · Let possible that a corresponding impulse is indicated with a Delay reaches the coincidence circuit 20 via the connection 21 in a way that will nooh be described. Every time the clock pulse train becomes positive, an "I" at the Q output of a stage to the corresponding output of the Transfer to the next stage. When the front edge of an input pulse during the first half wave of the laktiapuleee

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BATH

is applied to stage 10, the back edge of the pulse will arrive before the clock pulse train goes positive "and the Q output is only set to" 1 ^M once. If the leading edge of an input pulse arrives during the second half-wave of the clock pulse; Trailing edge only arrives after a "1" has been transmitted to the second stage 11, and the Q output of the first stage 10 is set to "1" again. This "1" will be transmitted ₅ when the clock pulse train is positive the next time will ο

In this way, input pulses arriving during the first half of the clock pulse will be entered into the register information entered as "1" followed by a "0" encode »pulses occurring during the second half of the Clock pulse arriving ^ will enter the code "1,1"

The arrangement shown in FIG. 1 has a nominal delay of 4 μs to the outputs of AND gates 23 and 25 o when an input pulse arrives in the first half of a clock pulse; then the Q output of stage H is set to ^H 1 after the clock pulse train has become positive four times

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BATH

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Stage 13 to ¹ M ^M α Accordingly, the AND gate 23 swtl receives its required input signals 3 »5 big 4 / Ui after applying the input signal“ The third input of the TOD gate 23 is the opposite or inverted clock signal P, dae from the clock generator 18 and applied to terminal 24, “This is why the third input signal is present when the clock pulse becomes negative, that is 0.5Ae after the other two inputs have been connected to voltage. The AND gate therefore gives an output signal with an exacerbation of 4 to

With an input signal in the second half of a clock pulse, the Q outputs of stages 14 and 15 are each "1" after the clock pulse train has been positive five times ο Therefore, after a delay of 4 to 4 _v 5 ^ s, an output signal at the AND gate 25 appear «The clock pulse train P can be applied to a terminal 22 in order, if necessary,« to limit the duration of the output signal of the gate 25 su »

The uncertainty of the delay of the AND gates and 25 signals supplied is 0.5yu, s, but one can Input signal su at any time during a Tuktimpulse period

00981S / 1S61

BATH ORIGINAL

of 1/4 / β duration can be created ο

In the arrangement according to FIG. 1, the setting of the coding of the information which is in the register arrives, dependent delay in two ways * Once the output signals are different stages uses «namely stages 13 and 14 for signals that ^

in the first half-wave the clock pulses arrive, and stages H and 15 for signals that arrive in the second half of the clock pulse. Ea it is obvious that any delay equivalent to an integer number of periods of the clock pulse can be provided, as long as there are enough bistable stages and logic circuits such as the gate 23 or 25 _{9 are} connected to the matching stages Delay caused thereby; that the AND gate 23 is caused to emit an output signal j after it has waited a certain part of the clock signal ο delays of fractions of the clock signal period or larger delays can be obtained in another way, r, .B. by adding another delay circuit after an AND gate _:

The AND gates 23 and 25 are connected to a monostable circuit, for example with a monoflop ₅ of 1 _f 3yU / S after

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BATH ORIGINAL

emits a signal to the coinside circuit after triggering · If nominally 5 μ », but actually 4.5 to 5» 3> * · (ie 4 + 1.3 / 4 *) after the first pulse has been applied to stage 10 If further impulses pass through connection 27 to the Koinside hold, the Koinside hold will generate an output signal. The impulse which is drawn through connection 21 can also appear between 4 and 4.5 ^ e and between 5.3 and 5.8 / * e depending on the point at which it occurs. Output signals are obtained from the cointegration circuit under the same conditions as from the above-mentioned known decoder, which has two registers, which means that the single register has one step more than each of the two registers nominal distance of f ftf ·. It is obvious how the circuit according to flg. 1 can be applied to pulse intervals of e.g. 8.17, 21 and 25 yfce ₍ which represents values used in civil traffic ·

If the duration of the input pulses corresponded to three half-waves of the clock signal, ie 1 _t 5 / fce in this example, a code would again be entered in the register which could be used to vary the etherification. S «B. an input pulse that occurs during the first half of a clock cycle

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BADOWGiNAL

Ϊ762007

impulses, ^{enter two W} 1 * s, since its trailing edge would only occur after the clock signal became positive once. An input pulse that begins during the long half of a clock pulse would ^{enter three M} 1 ^ns , because its edge would only appear after the clock signal became positive twice. Eb would various AND gates forming a gate array, are ₉ to produce output signals at the appropriate times but _t in view of the explanation given is easily seen, would like to build this logic circuit ο

Likewise if the pawn of the input pulses would would be any odd multiple of half cycles of the clock signal input to the register Cods allow delay as needed ο

In practice it is expected ₉ that with a period of the clock signal of 1 / frs the input pulses must have a pawn between G, 5 and 0 ₉ 6 / * 6. In any case, the duration of the input pulse in the application form according to FIG. 1 must be precise

arrangement

be Baltic, Figo 2 shows a / sua supplying pulses to the first Stife 10, wherein the application of the A ~ gangeiatpulee not precisely be Bauer buses _o

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ο / β

BATH ORIGINAL

Sin input pulse 3? we “eof” in “gaskle—” If given that the dl · dl «forms a starting point for the decoder. All · AND-öatter of fig · 2 llsfera «in negative · beginning» - signal, if all your messages are poeitive, vogagen »si Let all other Bingangakoablnatlonen their output poeitiTiT.

Ee eel now the state of UlHMJatter 2B ₉ 29 and 50 is considered _{ if no input terminal is applied, "Di · gates 28 and 29 asked" in a negative bit, nanlioh those not connected to terminal 19, so that * inre Attaging · poeltlT a, Deanaoh eepfttngt daa gate 30 "white poeitiv · Blngangaelgnale and an output is negative. If a poeltlven input input is bought at the UeaM« 19 the state of the gate 2Θ is changed and a negative Iapole appears at one start, which shows the Q output Begleteretufe IO to "1" setetα Dae gate 30 delivers when receiving the negative bingangimpulssee «Inen poeitlren Auegengalapule _t eo ing dae gate 29 a negative output and the getter releases a positive input vni dadnrob ends the negative Xspulse reaches the Öttife t0. Se irlrd an Iajrnle, which is linked to the period of the clock proposition, on the request of the stage 10 gsgsBsn * of the stage

009115/1501

BATH ORIGINAL

Π62007

in dtn "1" state o If the regeneration » since the gate 29 and 30 is dimensioned such that the gate 29 does not gate the termination of the input pulses If it delivers a negative output impulse, it becomes dae Gate 2Θ not reopened during the input pulses.

Now the gates 32 and 35 are considered o Before the gill 19 an input pulse is supplied, is the gate 32 that acts as a legator? a positive β input signal, so that the gate 33 is supplied with a negative input signal that makes the output of the gate 33 positive? The gate 35 has a negative input and so it also carries a positive signal su to the gate 34, so that the gate 34 applies a negative input signal to the data input of the stage 10. The data input requires a positive pulse in the presence of a clock pulse in order to bring the jQ output to the position "1 * ^1. Therefore, the gate 34 does not ^{input any" i n} into the stage IC at the point in time dealt with. As has been described, _s appear if a positive Eingangeimpuls is applied to the terminal 19, a negative pulse at the output of gate 28, and therefore also at the input of the gate 32. During the

009815/1561

Y / O

BATH ORIGINAL

«Wide half · of each clock pulse period, a positive input pulse of the signal · F reaches a small one 36, which forms the second input of gate 33 Gate 34 is closed and a positive pulse is sent to the data input of stage 10, including a wide "1 * elnsugeben" in the register. Gate 35 now receives two positive input pulses and also sends a negative singangeinpulse to gate 34. Kurs Impulse tön gate 28 is finished, gate 34 remains open until the end of the singing pulse. Therefore, as long as the input pulse is longer than half the factor period, the Q output of stage 10 is again divided to "1", and it will be From Regietsr wis bsi the arrangement according to flg. 1 swel ^N 1 "en only passed on if the input pulse falls in the second half of the clock period.

Although the input pulses must now be longer than half a fold period, there is no limit to their length as long as they do not overlap with the next input coil. The output logic of this execution form can be similar to the gate arrangement according to ₀ 1.

009815/1561

ORIGINAL

The Ausführungaform of the invention, the anband now is beeohrieben of FIG. 3 "is auegebildet that ate the more accurate the above-mentioned international requirements with steady rejection at M ± Ο, β ^ μ, β satisfy wlrd ₀ This Auaführungsform uses a 1-MHa ^ Clock signal P, which is obtained in a generator 18 from a 4-MHe oscillation and two 1s2-subsetBer stages. The 2-MHs oscillation 2P is present as well as the negated oscillations 7 and 2P. The shift register is required to generate a precisely positioned output pulse of duration 1 / ve with an uncertainty due to the position of 0.5 ^ · ia βο to meet the strict tolerances mentioned above.

The coded entry of the information into the register 10, 11, UeWo is carried out by the Kieftne 19 * ue as can be ascertained from FIG. 1, although the arrangement is necessary. 2 could just as well be used _o Ah one beeti * öt "n Stillt along the d * i tie ^ iettte beöteh" n four e, üfeine.iuie * £ olgeh <ie stages η - 1, n _s h + 1 and a + έ ait ata dishonored Xuegä & gen A ₄ B ₅ Ö uftd Ϊ) something the negated AuegafttflA t , I, f and ff. It * der & ifig & fi £ e @ & äe ^H i, i ^h , * lfeo 4er «titt Impult ta« er Kltüt ier last half of a bar ^ ttiodft

BATH ORIGINAL

1782007

- 1β -

wordtn, if d · * i-Me-AuÄenatilapul · simply wftnr «nd d · * clock period is derived, the · 1 <Λ 41 · t * ld * tt Μ * · η are in dtn levels & and a + 1. Β1 ··· γ lu »t * nd ▼ on« in · «tWlMlÄtt ·» 40 feet set. let der ¹¹ O (I ¹¹ , aleo der erete Iapul »ta d · * KlwiM 19 vüitttti d« r ereten half · · 1η · * teJtti ^ riod · · 1 & ι · § · Ηϋ novtfM »mi da · AuftgaagÄeifiud iron d * r Stuf · η vtthr »nd d» r gw «lt« n half-period · nhgenoatttn w * i ^ «a, wiÜiMnd d» t »loh dl · | 1 ^{M is} in η, and wa d ·» Stuf · η ♦ 1 « tthr * nd u% t ititift Hilft · d · * ntoh »twi ^ riod ·, nmohdMi di ·» 1 »in dl · Btuf · η + 1, dWith di ···! ^ · becomes, nMalioh (η - i} 8 + ^, VdMi * d · * BruoAt »il» on ewuohen the Yord * rfluut · d ·· «advise Iopul · ·· and d · * afc · rising or falling fluüte ton f Ut, wi» ·· g ** Ü · The case is »B · Ut lei ·· t« Mlöhtlloh »dai di ··· lutttiad · duroa di · ttmtt ·» 41 and 4 * * u »tfttHlBlt, whose siafiaf · wi · la d» r lelohnuttf darit »* t» lit een iind »DU Bintnnt« »* dlnittnc« n ftüf · 11 · three ttatt · ^ • eali »ften iioh sweep ··! tlf an ·» Dl · Au «gt & nf · d» r eiftd nil · La a · »OMÄ-» Ätt «r 43 tereinift,

• it «la ·« takt? · »! · * · Df ^ itt or · * β · ϋ * 1.βη · ϋ · 1 bar» • vi «d« a ttb ^ rlÄfftt. ta i «iü Kill lit d · * ι-μ · ~

00llU / Ut1

To delay exactly 0,25yU * BU early and he will, among other things, it _t a einetufigen shift register 44 supplied the 2? o The output pulse is given to the coincidence circuit 20 as in the embodiment according to Fig. 1,

* The actual delay is 0.25 / "/ β minus the Laufseit swieohen the 1-MHE Taktleitimg and the output of the OR Oattere 43" This is because the signal 2P, although it su P _s is synchronous to the signal F is advanced by its transit time, which is caught up again by the single-stage shift register 44. Therefore, the end result is that the effects of all propagation delays are eliminated and the delayed signal that is fed to the coincidence circuit 20 is kept exactly in time with the clock pulse

00981S / 15B1

BATH ORIGINAL

Claims (1)

Claims ι, JlmpvXsdeood.ierer with a shift register, the "having plurality ν η step, a Takteignalquelle, CAE serves" a &lr; s move first input pulse in the register to eir.e certain number of stages and zv äadvrch ura "in ν rbestimmtes Interval zuveriugern * and a device to determine a Kolniidens between the delayed output pulse and a xwide input pulse characterized in that the input stage G of the shift register (10 to 17) to an input pulse and the clock signal (PJ responds in such a way that He geeet stages of the register form different types of muht-jr if the input pulse has different phases: .n in addition to the clock signal, and that a "gate * scta'turg <ίΊ- 25 cder 40 4i. 42) se old one Aneahl d «; ^ egi Bt ei stages (13 U and 15) -ma the clock signalq el e Θ) connected aird that they depend on the * delivery-like; ^{formed by} the approved steps! Mean :: β?. · Πβη -ersscfeertOTj Aaegangeimpuls deliver during which ei f ^ h each phase of the clock signal * = Impi 3ce · diexer according to claim, characterized in that _} 2eQ ·: .. '. Β clocks; gna ".quelle" i8 «1η Reohtecksignal supplies _t 009815/1561 BATH ORIGINAL which has a duty cycle of 1: 1 and its
Half periods have a duration that is essentially
the value of the input pulse is equal to or an odd fraction of the duration of the singing pulse, and that this pike-square signal influences the change in state of the input stage (10) of the shift register derr.rt »that depending on» whether the first input * nipuis during a first or a second HaA> :: welle the right signal begins, in the kegist he * ne - different number of "1" s is written 3 · pulse decoder according to claim 1, characterized in that it has an input gate arrangement (28 to 30 and 32 to 35) which responds to input pulses beginning during different phases of the clock signal in such a way that it outputs a different number of control pulses _; Enter the ¹ M "s in the input stage (10; of the shift register, Leash decoder according to one of the preceding claims; hg "k" nnzeißhnat · that the gate circuit (2? and a tiii yarzb'gerWrt delivers the output pulse: the βλ /.
a - -3 ei 009815/1561 ORIGINAL BATHROOM discriminated Pbaaen ersöger ~. Aüfsgangaimpulaae is provided the Taktelgnalee equal 1st, and that an arrangement (26 dea for stretching? tan. 5- Trapuled deactivator after one of the tests 3, aadurrh germinated * ihne *: that the oattereoha.ltung (40, 4 '; 42 i except for the clock signal (P;' auah on s5n syn.hrcr.üa signal 2P. , leeean Frequent a very "afaxigeo V .a if act: a β der? requ * A2 ·" iee Tak ^ elgnalee 'P ie I. ar.apri hi, ^ Jn delayed Auagangeimpuiss the demanded I'auer "u deliver, - whose Vordef and Rttokflanke beiü ^ are due to the clock signal beetiaur / c 009815/1561