GB1153386A - Improvements in Electrical Pulse Decoders. - Google Patents

Abstract

1,153,386. Electric selective signalling. A. C. COSSOR Ltd. 15 Feb., 1968 [24 April, 1967; 27 Oct., 1967], Nos. 18826/67 and 48989/67. Heading G4H. To detect whether a first pulse is followed after a predetermined interval by a second pulse the first pulse is entered into a shift register (shifted under the control of clock pulses) either one or two stages being set to their "one" state by the first pulse in accordance with its time of arrival relative to the clock pulses, gates connected to some of the register stages passing the first pulse after a predetermined delay to coincidence circuits to which is fed the second pulse. In one embodiment (Fig. 1), to determine whether a second pulse arrives 4 Ás after the first, if the first pulse arrives during the first half P of a clock pulse cycle, after 4 Ás the pulse is in stage 14 of the shift register and during the second half cycle P of the next clock pulse cycle, i.e. after 4 to 4À5 Ás delay, AND gate 23 gives an output to trigger one shot multivibrator 26 the output of which is connected to the coincidence circuits 20. If the pulse arrives during a second half P of a clock pulse cycle the "1" state of the circuit stage 10 is transferred to the next stage 11 during the first half P of the next clock pulse cycle and since the trailing edge of the input pulse occurs during this first half cycle stage 10 is again set to "1". In this case during the first half of the fifth cycle of the clock pulses stages 14, 15 are set to their "1" state and via AND gate 25 trigger the one shot multivibrator 26 as before. In the embodiment of Fig. 2 (not shown), in which the input pulses are not of precise duration the shift register stages are preceded by logic circuitry which, as in the embodiment of Fig. 1, controls the setting of either one or two stages to the "1" state in accordance with the time of arrival of the input pulses relative to the clock pulses. In the embodiment of Fig. 3, the outputs of the n - 1, n, n + 1 and n + 2 stages of the shift register are selectively coupled to AND gates 40, 41 and 42 to give an output via an OR gate 43 and one stage shift register 34 to the coincidence circuit 20. The apparatus may be used in secondary radar transponders.