DE1474479C - Circuit arrangement for evaluating read signals - Google Patents

Description

If a normal read signal L (FIG. 4, line d) is now fed via the rectifier 303 to the threshold value elements 307, 308 for evaluation, a pulse arises at the output of the threshold value element 308, as shown in line b, FIG this only responds when threshold H is exceeded. The signal at the output of the threshold value element 307 has the form according to line c, since the threshold is lower. Since the read signals are to be stored in the storage register in a clock-synchronized manner, an arrangement for clock generation is provided which, in a known manner, consists of a differentiating amplifier 304, a flip-flop 305 and a clock shaper stage 306. This arrangement supplies clock pulses synchronously with the read signals (line d, FIG. 4), which are each fed to a further input of the coincidence gate and the blocking gate. In the event of an error-free read signal, these clock pulses then open the coincidence gate 309, while the blocking gate is blocked by the signal appearing at the output of the threshold value element 308. The read signal recognized as faultless now appears at output 310 and is made available for further processing.

If, however, an interference signal (F, F i g. 4) occurs, this does not reach the threshold if. As a result, no signal occurs at the output of the threshold value element 308, the coincidence gate 309 therefore remains blocked and the blocking gate 311 is opened. At the output 312, a signal that indicates an error occurs synchronously with a clock pulse.

In Fig. 5 is a special circuit implementation of the in FIG. 3 shown block diagram shown.

1 sheet of drawings

Claims (3)

1 2 evaluation can be added. Fig. 1 shows a patent claim: such an arrangement for 3 recording tracks. The read heads 101, 108, 115 are with read amplifiers 1. Evaluation circuit for read signals connected to 102, 109, 116, which in turn strengthens the information stored on the moved magnetic layers Wertglieder, 104, 111, .118 with high responsiveness that deliver the read and evaluated signals in response to a threshold. The higher threshold is now registered in such a way that the peak value of an error-free read indicates that the output of the threshold signal is definitely greater, while the peak value of a value element with the low threshold with an interference signal is definitely smaller than the entrance of a coincidence gate and the north threshold. The lower threshold is set so that the male input of a blocking gate is connected so that it is smaller than the peak value of an interfering signal.
If an error-free read signal occurs, the threshold elements 103, 110, 117 or 104, 111, incidence circuit and the blocking input of the 118 signals, which with the help of of a clock pulse is connected to the blocking gate and that the output of storage elements 105, 112, 119 and 106, 113, 120 of the coincidence gate are stored with the input of one of two read registers. The storage element of a storage register is connected to reading the information stored in these registers. · 30 mations are both inputs of the locking gate 2. Circuit arrangement according to claim 1, driven 107, 114, 121 as a sign that characterized in that one clock cycle has occurred per track, no error has occurred at output 122 encoder is provided and that emit the coincidence signal. And only on one of the reading gates and the blocking gate every one further single heads an interference signal occurs, gives the corresponding one Have gang that is connected to the clock 25 evaluation element 104, 111 or 118 from no signal. are. As a result, storage elements 106, 3. Circuit arrangement according to claim 1 and 2, 113, 112 no information is stored, so that characterized in that the clock from the query of these memory elements at the output queried information is obtained. 122 a signal appears as a criterion for a 4. Circuit arrangement according to claim I, that 30 error has occurred. A disadvantage of this known characterized in that the threshold value element is a circuit that two storage devices per read head are dimensioned so that the peak value of a moment is required for the read register. For the Occurring read signal is certainly greater than storage in the memory elements of the reader The higher threshold and the peak value of a register are also two clock pulse sources Interference signal certainly smaller than the higher 35 required. Threshold, but greater than the lower threshold. The invention is based on the object to create an arrangement that achieves the same thing with less effort: this is achieved by that the output of the threshold value element with 40 of the low threshold with an input of a coincidence gate and with the normal input of a The present invention relates to a locking gate that is connected to the output of the Circuit arrangement for evaluating on threshold value element with the higher threshold with Information stored away from magnetic layers - another input of the coincidence circuit nen. When reading such information, it can be connected in front of 45 and the blocking input of the blocking gate come that interfering signals or erroneous readsesi- and that the output of the coincidence gate with Signals occur which are evaluated as a read signal when reading the input of a memory element of a memory and is thus linked in the connected data register. Processing plant cause failure. Therefore it is The invention will now be based on an execution necessary to provide a device, the error example for three recording tracks in free and faulty read signals or interference signals F i g. 2 to 5 explained. can differ from each other. A known The arrangement according to FIG. 2 has three reading measure for the detection of faulty signals, heads 201, 205, 209, each with an understanding therein, the written signal immediately after stronger 202, 206, 210 are connected. To the Verdem Writing for control with the aid of 55 are stronger evaluation circuits 203, 207, 211 on one combined read / write head to read. The closed. These evaluation circuits have a Control read signals are a Schwellwertan- structure according to FIG. 3. They essentially consist Order supplied, the threshold is so high that from a rectifier 303, which the read signals despite the one threshold value element 307 with a low response amplitude decrease caused by repeated reading the information is always at low levels and a threshold element 308 with a high antig be recognized. The faulty reading signals supply speech level. The output of the threshold value (drop out) lie below this threshold and element 307 is with an input of a coincidence not recognized as such. If you were to link the threshold gate 309, the second input of which with the lower, would possibly be connected to the Kon output of the threshold value element 308. trollread the interfering signals over it. A known 65 The output of the threshold value element 308 is out of action To recognize such signals, there is one with the blocking input of a blocking gate 311 mm in providing two threshold value elements, which are connected, one of which is a normal input with the the signals picked up by the read head are connected to the output of the threshold value element 307.