DE2064255B2 - CIRCUIT ARRANGEMENT FOR TIMED INFORMATION EVALUATION, IN PARTICULAR WHEN READING BIT RECORDS - Google Patents

Description

In particular, it is provided that when the bistable trigger circuit is set the proper time of a second monostable multivibrator is also reduced, the is tilted into the unstable state by main and auxiliary clock pulses, a proper time has the is shorter than the time interval between clock pulses and for fading out or recording of a recorded by intermediate jumps Signal generated read signals is used.

The invention also provides that the proper times of the monostable Trigger circuit or trigger circuits by a control circuit in addition to one known setting according to the main clock frequency. this will for multi-track reading with each track's own clock preferably achieved in the way, that the master clock recording of a track control circuit by supplying a Auxiliary clock pulse is switched so that it clock pulses of another, in particular adjacent track.

For a clocked recording of bit signals, e.g. B.

of a recording medium in which the bits are successively converted into a Bit memory are included, the invention also provides that a failure of a main clock pulse that replaces it, preferably of the aforementioned type Automatically generated auxiliary clock pulse as an address switching signal for the bit memory is made effective.

For multi-track reading it is provided that the auxiliary clock pulse sets a marker memory to mark the track for which the auxiliary clock pulse was generated.

It can then also be provided that the marker memory by a parity-checking circuit for the purpose of error location detection and, if necessary Error correction can be queried.

It can be useful here that each bit storage element of the Bit memory assigned to a marker memory element of the marker memory is.

An embodiment of the invention is explained in more detail below on the basis of the drawings, of which F i g. 1 shows a circuit arrangement according to the invention and F i g. 2 shows associated timing diagrams.

In Fig. 2 the line inf represents a processed read signal, read over seven recorded in "directional clock script" on a magnetic tape Bits.

When reading the directional clock script, those marked with "1" or "0" are used Jumps in line t, th marked with t, in the following again as "main clock pulse" designated clock pulses and converted into information pulses, with a jump in one direction (in line inf in the positive direction) means the bit value »1« and a positive pulse is generated in the line il, while a jump in the opposite Direction means the bit value »0« and generates a positive pulse in line 10.

If the same bit values follow one another, then there must, as between the two first values »1« of the line inf, an intermediate jump takes place that does not have a clock and To generate information impulse and is therefore to be faded out during the evaluation.

For this purpose, a monostable multivibrator B (Fig. 1) is provided, which is tilted into its unstable position by each clock pulse t and a proper time which is smaller than the time interval between two clocks t, e.g. B. 750 / o of this is.

The output of the monostable multivibrator B in the unstable state prevents during its duration that a jump in the read signal a pulse il or OK.

In detail, this happens as follows: Every positive jump in the read signal after line inf produces a positive pulse after line dl, and each negative Jump generates a positive pulse after line dO.

These impulses arrive at the appropriately labeled inputs in Fig. 1. dl is at an input of a NAND gate 1 and dO at an input of a NAND gate 2. The second inputs of both NAND gates are connected to the output b the monostable multivibrator B connected. The output of the NAND gate 1 goes to one input and the output signal of NAND gate 2 goes to the other input one. NAND gate 3, whose output signal, inverted in an inverter 4, a Input of a NAND gate 5 is fed. The NAND gate 1 or 2 is a negated Information signal il or OK only if a positive signal dl or dO at one Input and at the other input there is also a positive signalb. The NAND gate 3 gives a negative signal via the downstream inverter 4 if at one of its Inputs a signal Fi or Fo is present. NAND gate 5 gives a positive clock signal at terminal 6 if a negative signal appears at one of its inputs. The clock signal the monostable multivibrator B toggles into the unstable state. Your output signal b is in the correspondingly designated line of FIG. 2 shown.

Each clock signal at the output of the NAND gate 5 also toggles one monostable multivibrator A in the unstable position in which it is during a proper time lingers longer than the time interval between master clock pulses t, e.g. B. 125 0 / o of this.

As long as main clock pulses t in the regular time interval (mutual Distance between the first three main clock pulses t in line t, th of FIG. 2) successive, the monostable multivibrator A cannot flip back into the stable state, since it is designed to be «extendable» or)> retriggerable «in a known manner, so that a tilting pulse arriving during its unstable state has the duration this state is extended by the proper time.

In the line inf of FIG. 2 are two consecutive with a Points in time at which an information state jump is read would have to be, but as a result of z. B. "drop-out" caused by a speck of dust is not read. As a result, there is also no pulse dl or dO, t, il or iO generated. Since the F i g in line t, th. 2 after the third master clock pulse t no main clock pulse appears at the target time, the unstable state becomes the monostable Toggle switch A is not extended, this rather toggles after its own time has elapsed back to the stable position. The outputs a and a of the monostable multivibrator A are each connected to one input of a NAND gate 7, namely the output a via a delay element V. As long as the monostable multivibrator A in the unstable Position, positive potential appears at the output of NAND gate 7 (terminal 8). When A falls back, a becomes positive, the change to negative at the other output However, a has a delayed effect by the delay element V, so that up to Appearance of the output signal av of the delay element V at both inputs of the NAND gate 7 is a positive signal and the NAND gate 7 is a negative Outputs pulse to terminal 8. This pulse becomes the second input of the NAND gate 5 fed, which thereby emits a positive pulse that appears at terminal 6 as an auxiliary clock pulse th (cf.

in this regard F i g. 2, lines a, av, th and r, th).

The output pulse at terminal 8 also sets a bistable multivibrator C. The output signal c of the set multivibrator C becomes the monostable multivibrator A and B supplied with the effect that their proper time by z. B. 25010 reduced will.

In addition, the mentioned auxiliary clock pulse generated at terminal 6 flips the monostable multivibrator A returns to the unstable position, and it also flips the monostable multivibrator B into the unstable position.

If at the second point in time a according to line inf of FIG. 2 again no main clock pulse is generated, the monostable multivibrator A drops after expiration their proper time, which is now equal to the time interval between those that appeared before Main clock pulses are back to their unstable position and generated in the described Way at terminal 6 another auxiliary clock pulse th, which the monostable flip-flops A and B tilts again into the unstable position. This process continues as long as none Main clock pulse appears, continuing for any time, using the one-shot multivibrator A auxiliary clock pulses th generated at the target interval between the main clock pulses t and the monostable Flip-flop B in the manner described, the masking to be eliminated Causes intermediate pulses. As from the previous description and the line t, th the f i g. 2 can be seen, a first auxiliary clock pulse appears with a Phase delay of z. B. 2501o of the main clock interval, and all auxiliary clock pulses th therefore appear with this non-interfering phase shift compared to the Main cycle target times.

In the example it is assumed that after the second target time a again an information signal (> 1 «) is read with the result that in the described Way again a main clock pulse t appears at terminal 6, with a simultaneous one negative pulse at the output of inverter 4 corresponds. This impulse arrives (like each such pulse) to the reset input of the bistable multivibrator C and resets these with the effect that the proper times of the monostable multivibrators A and B can be extended back to the original "regular" value. There at Appearance of a first skin clock pulse t following an auxiliary clock pulse th because of the aforementioned phase shift of the auxiliary clock pulses th the proper time of the monostable multivibrator A has not yet expired, it no longer falls rather, the unstable state is again in that for the main clock mode described way, and also the proper time of the monostable multivibrator B is adapted to this main clock operation again.

Bits are usually recorded in several tracks on magnetic tapes, being recorded in a line perpendicular to the direction of tape travel in the individual tracks Corresponding bits form a rung ((. A circuit arrangement according to F i G. 1, as described above, is provided for each track. It is known, the operating time of evaluation switching elements such as the monostable ones described above To adapt flip-flops A, B to the tape speed. According to FIG. 1 is for this purpose a control circuit ST is provided which is designed so that she one Clock frequency is converted into one of these proportional control voltages. These is fed to the monostable multivibrators A and B in order to follow their proper times Set the requirements of the respective belt speed. It is intended that from a track, in particular a middle track of the tape, to the assigned Terminal 6 generated clock pulses are fed to the control unit ST, while the result developed control voltage ust the monostable multivibrators A, B of all tracks is fed. An auxiliary clock pulse generated for said individual track is also fed to the control circuit ST in the form of the pulse generated at terminal 8 and has the effect that the terminals 6, 8 of this track from the control circuit ST switched off and instead the corresponding terminals 6 ', 8' of another, preferably adjacent track can be connected to the control circuit ST. One in this Auxiliary clock pulse appearing on the other track causes terminals 6, 8 the first-mentioned track can be connected to the control circuit ST. This return and downshifts can e.g. B. by a set by an auxiliary clock pulse or resettable bistable flip-flop are effected which goals for the Controls signals of terminals 6, 8 and 6 ', 8'.

With Rn in FIG. 1 denotes a four-digit register, in the bits read one after the other are temporarily stored. this happens with the assistance of a counter Z, which counts from 1 to 4 with cyclical repetition and through successive and also cyclically repeating activation each one of the AND gates 9 addresses the register position in which a bit value 1 (= 0 or 1) should be entered. This usually happens in the way that a bit value previously contained in the position is "overwritten", i. H. through the new bit value is replaced. At the counter input z of the counter Z, from terminal 6 coming, both main clock pulses t and auxiliary clock pulses th as counting pulses effective, d. This means that the location address is also forwarded if to a Target time a no information pulse was generated. This makes it possible to on which no new bit was written, but the "old bit" remained is to discriminate in the further evaluation. In addition, it is achieved that, if a register Rn is provided for each n tracks and these registers as a de-skewing buffer is operated, the mutual mapping of the Bits of a rung are not lost when they are stored. The possibly The necessary correction of an "old bit" can then be carried out subsequently by a parity checker P of a known type, the "cross parity" (rung parity) in a known way. checks. To do this, the track must be known in which an "Altbit" stopped. To mark such a track, there is a bistable for each track Flip-flop D is provided, which rit by an auxiliary clock pulse forming Pulse is set at terminal 8 and in this state via its output d the Parity checker P transmits a signal which marks the error track. The inputs of the parity check device P shown in dashed lines come from outputs further bistable flip-flops D, at least that of the other tracks.

The timing of the reset of the bistable Flip-flops D via the reset input r depends on the type of further evaluation of the Register Rn stored bits. For a z. B.

Block-by-block evaluation can bistable multivibrators D only once provided for each track and deleted at the end of the evaluation of the block.

However, a flowing evaluation can also be provided in the Kind that at the same times positions of the register Rn for evaluating bit value extraction and other locations for bit value storage are addressed. In this case can it can be provided that a set of bistable flip-flops D is provided, in particular one for each digit of the register Rn, as in F i g. 1 is drawn in dashed lines above register Rn. Under control by the counter Z then not only becomes the bit value write-in address for the register Rn determined, but also an auxiliary clock pulse as the setting pulse of those bistable Toggle circuit D supplied, which is assigned to a register position in which an "Altbit" stop. This bistable flip-flop is then reset immediately after the one associated with the parity check and, if necessary, bit value correction Bit value extraction.

Claims (8)

Claims: 1. Circuit arrangement for clocked information evaluation, especially when reading bit recordings, thus g e k e n n n -z e i c h n e t that a one-shot multivibrator (A) that is triggered by master clock pulses when they regularly follow one another, held in their unstable position in a manner known per se because their proper time is longer than the time interval between such impulses, when tilting back into the stable position, an auxiliary clock pulse is generated, which it repeats tilts into the unstable position and at the same time sets a bistable trigger circuit (C), whose output signal in this state is the proper time of the monostable multivibrator (A) on the size of the time interval between regularly successive main clock pulses reduced, and that the bistable multivibrator (C) is reset by a master clock pulse will. 2. Circuit arrangement according to claim 1, characterized in that if the bistable trigger circuit (C) is set, also the proper time of a second monostable Flip-flop (B) is reduced by the main and auxiliary clock pulses in the unstable State is flipped, has a proper time that is shorter than the time interval between Clock pulses and for fading out or capturing by intermediate jumps of a recorded signal generated read signals is used. 3. Circuit arrangement according to claim 1 or 2, characterized in that that the proper times of the monostable trigger circuit (A) or trigger circuits (A, B) an additional setting known per se by a control circuit (ST) according to the main clock frequency. 4. Circuit arrangement according to claim 3 for multi-track reading with each track's own beat, characterized in that the main bars of a track The receiving control circuit (ST) is switched over by supplying an auxiliary clock pulse is that it picks up clock pulses from another, in particular adjacent, track. 5. Circuit arrangement in particular according to claim 1 for a clocked Evaluation of bit signals in which the bits are successively recorded in a bit memory are, characterized in that a failure of a main clock pulse this Replacing, automatically generated auxiliary clock pulse as an address switching signal for the bit memory (Rn) is made effective. 6. Circuit arrangement according to claim 5 for multi-track reading, characterized characterized in that the auxiliary clock pulse has a marker memory (D) for marking of the track for which the auxiliary clock pulse was generated. 7. Circuit arrangement according to claim 6, characterized in that the marker memory (D) by a parity-checking circuit (P) for the purpose of error location detection and, if necessary, error correction can be queried. 8. Circuit arrangement according to claim 6 or 7, characterized in that that each bit memory element of the bit memory (Rn) has a marker memory element (D) of the marker memory is assigned. Information signals are often generated with the help of clock pulses evaluated, the clock pulses either from a special clock pulse source or from the information signals themselves, if they are used for "self-timing" appropriately designed can be obtained. In particular, is a clocked Evaluation common when reading bit records from a z. B. magnetizable Carrier for which the present invention is primarily, but not exclusively, is intended. State jumps occur from such a carrier during the passage scanned and converted into pulses as information and / or bit clock pulses to serve. Magnetic recordings are known in which between successive jumps that generate clock pulses There are intermediate jumps which, when reading, either, so with the »directional clock script +, hidden or, so with the» alternating clock script, must be recorded as bit value information between two clock pulses. With the clocked evaluation of signals that the value of consecutive Specify bits, the clock pulses are often used for successive addressing used by storage locations in which the bits are to be put, which gets in the way individual addressing of these memory locations as well as by way of a shift process can be carried out. When reading a multi-track tape-shaped recording medium, the skew effects, it is known to have such a bit memory, the can hold a certain number of bits from each track, as a "de-skewing" (- intermediate buffer to operate, the bits belonging together from the different tracks that form a "rung" form simultaneously recorded values, can be extracted synchronously. With this extraction can be linked to a parity check, which is carried out in a known manner enables error location determination and, if necessary, error correction. The invention relates to a circuit arrangement for clocked Evaluating information, particularly when reading bit records, and deals with the task of avoiding disruptions to the evaluation that arise as a result, that evaluation clock pulses that are generated in the manner mentioned above and in the following are called "main clock pulses" due to interference, such as z. B. »drop-outs«, when reading magnetic text, do not follow one another regularly, but rather fail at times. According to the invention it is provided that a monostable multivibrator, that by main clock pulses, if they follow one another regularly, in per se known Wise is kept in its unstable position because its own time is longer than the time interval between such pulses when tilting back into the stable position an auxiliary clock pulse is generated, which tilts it again into the unstable position and at the same time a bistable multivibrator sets whose output signal in this state the proper time the monostable multivibrator to the size of the time interval between regular successive master clock pulses reduced, and that the bistable multivibrator is reset by a master clock pulse.