DE1424728A1 - Logical circuit - Google Patents

Description

DlpWng. Au ~ u5t Boshart ? ·} (..Ti! QM

Diph-Ino. V-er Jacklich 23 July 1968

Katentonwält · . _Λ Λ LO ί, Π OQ

r |. »<Μ« *! «* · * SA 25 221 » * »* H / ^ O

HZPPON Telegraph, and Telephone Public Corporation, Tokyo, Japan.

LOGICAL SCHAIiIOHQ

The invention relates to a logic circuit, in electrical digital computers that operate at high speed, it is desirable to have all of the numerical information stored in each of the resistors as a printout dtr Number of an arithmetic unit in the form of an information group consisting of an expression unit transfer another resistor group or another circuit su. If a normal logic circuit with Diodes as a selective transmission element for this purpose Is used, the number of elements increases considerably and the efficiency is very low because a long chain of tone uses stages of logical operations and amplifiers Need to become. This circuit therefore has the disadvantage that a relatively large amount of time is required for the selective transmission will"

Although a logical "no" operation is a logical puncture the various controls of arithmetic circuits

809806/0649

■ »Mr t San 3 that

₈ igt the degree of efficiency that can be achieved with normal diode circuit * not unsatisfactory, so that the planning of the circuit for logisch® Höofmeaoperationen is difficult «. In the arithmetic of a ^ tatements Gleitkomraabetrieb is generally of superior fsstkoiamabetrieb * _s of v stopped at each overflow. Ground must * The Gleitkommabetrieb can the numbers b there sos, · evaluate than the Pestkoiaoiabetrieb " On the other hand, however, the floating point operation, when using ordinary logic circuits, requires a greater amount of time for the operation ala the pest point operation.

is intended for Eeeheiioperationen in Grleitkoiamabetrieb has the number in a Siffernteil and in & sntoil analyzed werderij whereby the Binärpimlct "Duröh addition oäer Stibtrslctiön sweier numbers werdoa siiaächst di-3 indexes and dami the Siffernteile miteijiander compared $ then the steps" Kahl ds ^ Siffereas! transferred to the absolute Y / ert and both figure parts are added or subtrahiertf then the teroh addition or subtraction is erlialiei? .e Sumie © _e bsw difference wieäesf tibet wear "so that an exact Biasrptmkt Strootman. can be seen © Xsaexfeeil @rkaltea *

Bsi & φά laislisr sekasitta arit & ffictigehen. liahslten we g CMS ¹ Sh aisfeiasB the following repetition © ^. Jeäes

Ksig®s © ti3ten ts eraaltasg * johzl ei® 2 <siteln! Ieitea ύϊ3Τΰϊι & e? I

, 2 ©? 5s ^: üfl ^: vjsr & m. «Is wise fl & iisr öia S ^ ii Qiaos

is required for the operation

The invention is intended to remedy these considerable drawbacks of the normal logic circuit and the logic system and represents ^{a new circuit with regard to a selective transmission line, a logic "No 1} * circuit and a high-speed conversion circuit. The operation according to the invention can with high Speed and a high degree of efficiency and therefore represents a considerable advance in logical circuits of calculating machines »

The various representations of the circuits according to the invention are based on the same simple principle and have a wide range of applications · The invention has the advantage that, when connected logically, the to the correct Input terminals induced current flows into a branch line of the circuit and acts as an output atom to that in a part the mentioned pointing line existing load impedance, wherein the gate elements are connected to one another and the openings of which are monitored by the input / impulse, and wherein the supply of the induced voltage is controlled by one of the input pulses.

The invention is explained in detail below with reference to the drawings described. There are shown int

1 shows a basic circuit according to the invention, Pig · 2 shows a logic circuit of an embodiment example below Using the principle shown in Fig. 1,

809806/0649 ~ ² ~

PIg ₄ 3 a circuit corresponding to your left 2? _e il the circuit according to Pig «2

Fig »4 selective transmission lines, the resistors and the arithmetic circuits interconnect "Fig", 5 a further basic circuit according to the invention. Pig «6 a logic circuit of an embodiment, using the principle illustrated in Pig * 5. 7 shows a further basic circuit with the same function as the previous circuits according to the invention " "Pig * 8 a logic circuit of an embodiment using the principle shown in Pig * 7 » Pig 9 is another embodiment of a logic circuit according to the principle used in Pig * 7 * Fig * 10 is a block diagram of an exemplary embodiment logic circuit «

Pig «11 a wiring tone logic circuits according to the implementation example! from Pig 10
Pig * 12 © ine! Gate circuit according to Pig · 11 Pig »13 a block diagram of a further embodiment 8 example | the circuit shown in Fig · 10 * Pig · 14 dia color & img of the circuits according to the one shown in Pig »15

In flg. 1, H "inen! ^{Most banal shows the 1} , Ii Einsa impulse transformer, B ät ^ ezi B ^ lastungewidsretaiad, χ and y the input terminals, which" .to && m signal is sent, and the logical lüing & ngswtrfcilä Z and 7 t2itsprtol $ # n} u represents the Auagangeklean · ä & Vf «si dtr 3oglso! It 797t IT Äbgenoaman becomes ·

•. -5-

809806/0649.

The symbols in the figures are chosen to be the same Symbols indicate the part or ropes that have the same puncture however chosen if several and identical ropes are available, which, however, have to be differentiated from each otherY denotes unknown numbers, but does not contain zero

If a current source is connected to the input χ in Pig 1, an emitter current flows into the Trasistor H, this assumes the conductive state, but only for the duration of the input pulse * If none at the collector If voltage is connected, no current flows, but if it is the negative voltage that is induced across the transformer L when a signal is applied to y is fed to the collector becomes, a collector atom flows »

If an input pulse is applied to χ and y at the same time, (both singing pulses should be present at least partially at the same time) the current flows in the direction of the arrow and u a positive output pulse is generated · If the input pulse is only applied to χ or y, nothing appears for u Output pulse because the collector current is not flowing can if only an emitter current and no collector voltage present 1st It is a logical function for this circuit

U X T. (1)

logical P _r oduct (AND)

Pig 2 shows an embodiment of the circuit according to FIG of the invention, which is based on the above-mentioned principle "

809806/0649

If the input pulse is applied to an input terminal χ _γ , z »B» at x-, the point M is applied via cf <sn transistor EL to Er where "hot! Transistor If has its emitter current" the jSingansimpulg auiii . οι ^ ₂ applied, the tension in Efeilrlchtung to ^ olnindärwicklung Lg indusiert * If the! performance of Singasigsimpulses at _J2 strong enough flows of Kollekto ^ ötrsLioC · Ie ((X of Yerstärkungsfaktor) is generated over path ρ pad at Ug an output pulse to avoid that the current flows through paths p ¹ and p ^M , if no input pulse has been applied to any of the Kleamea π ^ , but only to y ^> sioden d1 and d ~ are inserted "· diode dg serves the gleieiitn Sweok when SI® is connected to '8g." at the output terminals is therefore no output current ®xzg-a.gt _f * if keia to the inhibiting y ^ _f ^ _Ρ γ y "is placed Eiiigangsimpuls , even if the terminal χ an input pulse is applied anyway «
You logiselie puncture this circuit is ι

U _r «(X ₁ ^ X ₂₊ X ₃ ) Y _T ....... (2)

logical Snaia © (OSSB)

If the · input pulse for Χ. «Ϊ́ £ * 1 is selected, the current flows in the path p ^{f in} accordance with the Tos-mentioned principle · If the forward resistance of the diode d is less than

of the! transistor H ₁ H vszid the emltterstroic Ie is aa strong, di® is given to y Kslle & torstross Xe dätapfung f ^ öi in äea Weg p _e Demaufelge has this attitude.-theor3-tisek den hSshstesa. Efficiency »If oil © nor-aale Bingaaga-

809806 / 06-4 9

The impedance at the terminals y and the resistance of the loading resistor are balanced and the emitter current is sufficiently strong, you get a circuit with a higher efficiency for the pulse applied to y «The input impedance of this. Circuit increases at y if none of the input terminals X ^. an input pulse is applied "because then the collector current cannot flow into the secondary winding L" If other similar circuits are operated in parallel to the common terminal u _y and the output pulses do not reach two terminals U ₇ , Y can generate the small input power required by itself if several elements connected to terminals y_ are controlled at the same time «

If synchronization and Eegenerationsimpulse at y _T are applied, and low time and power level difference is present the Auagaqg ^ _t pulse extinguished, ie, "the puncturing of y also duroh x ^. can be exercised, and the input pulse of χ can be used as a synchronization and regeneration factor «In this embodiment the transistors are used in base hold, but emitter circuits can also be used, the result being almost the same«

In Fig. 3 a different gate circuit is dargesta.lt in weloher the transistors instead of FIG. 2 diodes are used · d The diodes are used as a gate element ·, 0 are capacitors, R 1 represents a Ablet! Resistant, E ₀ a Überbrüokungswideretand A positive or negative bias voltage according to the binary values of the output pulse of the breakover

BATH 809806/0649

circuit Έ _γ is applied to the diodes d, which have a (pore function) «.

Fig. 4 shows a circuit arrangement in which logical holding a have been used as selective transmission lines which connect the resistance and arithmetic circuits to form an arithmetic unit. Q ₁ , Q ₂ , Q * .... are the resistors or arithmetic circuits the ^Fuei: the € 53tanseigebit (LSB) are used Mind "Mf and M ₂ are · if Q ^ Qg and resistors are nnä Q ^ igt distributor for the Mindestanzeigebits a Additioasschaltung, and when. All information won, met resistors Q ₁ and Q g simultaneously au Ääditionssashaliung the transfer dea wi ^ are the Inforaa »i © a FITP reaches every Bii in the small 2ell # of Widerstandet gens" ^ m Ίβϊ · "ntepreohenden Zeil®

25er Dinfaölalitit liÄber is treated here aar äas Mineatanzeigabit * You Xctdrsation ittr da® ISänAeetanzeigefeit in Q ^ is by ^ h of the W # g; P ^ äü the Ä-sine cell of the minimum sake * - bite in d «ff Alditloaouefealtung transmitted @ a ₉ sad di® laformation ftlr dan LSB i »Qg arrives over d & a Hireg- P _g der thin«. P ^ and ^ ₂ are shown in '' TIg * α 5ιΐί; ο *, dotted "Aiinlsii *

M and Ä «nSspi'te ^ R der 7trblsdv2ig M from M $ * 3 and the

Ubertraguageleitimgett svl imae of de ??. Distributors consist "of the" left ^ && £ 9Qh% 9m. ä% il the one shown in Jig * 2

Since all information is a number that consists of η Bite and When an expression is treated, it can also be translated into the arithmetic unit of a parallel expression must, must have the selective transference attitudes with high efficiency from a pulse rod carrier with a Primary winding and some secondary windings consist of «They transformers have the same function as Xi in Pig · 2«

Another basic circuit according to the invention is shown in 71g «5, in which -E represents a negative DC voltage source, H a transistor, L a pulse transformer, R a load spring, B- a resistor, C a capacitor, d the diode, χ and y the input terminals and u an output terminals The base direct current flows more and more into the Iransietor H, and this is selected in such a way that a collector current flows when the collector voltage is negative. If, therefore, a long pulse is excited at y and the voltage is induced in the direction of the arrow, the collector current flows only for the duration of the pulse and an output pulse is obtained at u.But if you apply a positive input pulse to χ, the base voltage of the transistor H for positive for a short time and due to the storage function of the capacitor "0 maintained for some time" The transistor H is blocked and no output pulse can be received, even if an input pulse is applied to y "The positive base voltage discharges with the time constant that Tone 0 and E1 is determined, and the back-up current then flows back into the translator H. The capacitor can also be connected to this sohs & ung. *

-10-,. 809806/06 * 9 BATHROOM -

The logical punctuation for this circuit is:

t logical negation If Y is the constant input pulse value, then »

U- f. ♦ (4)

If a sufficiently strong base current flows, as long as no input pulse is applied to χ, and if the input impedance of y and the load resistance are balanced »results in a high frequency ^tt ITeia ^ff circuit in accordance with the principle shown in Pig« 2 «

β shows an embodiment of a logic circuit using a circuit according to Pig · 5 »If the logic signal pulse is selected according to Σ« «X» »Ϊ2« while all others are lull, the current flows via path ρ and the output pulse arrives after the mentioned irinaip after U ₂ #

logisch® puncture for this switching is consequently

_u yyy ^ * · (5)

7 30 another disagreement arundeo attitude “In her _s x · a paa? liagangskleames ^ fienes the logosohe We3Pt % suge £ üh? t will «5! is © ia ^ output-Zmpulstt ^ srtr & gery- and ß ^ 8i &, & svi © i PrdaäärwiekltsageH and a ^ represents elm © Sekuadär wieklus3'To **. f ^ -r # Wezsa. The Staitteretrom ie from s, x · to E flictsst? jfid au y min singing impulses placed iet ₉ receives

808806/0649

to u via an output pulse and the collector current flows not.

If the input pulse is then applied to x, x ¹ and y, the currents ie and io flow simultaneously and the two currents cancel each other out in Baaiakreia, and no output pulse is obtained If, among other things, this disadvantage is to be eliminated, the number of windings through which Tones ie and io flow, Tones nj and (n ^ + ng) », is determined as can be seen from Pig.7. If the input pulse is only applied to y, ie and ioht are not induced and consequently do not flow »Pie logical function ist

U '- X. T ♦ ♦. . . . ♦ ( If X is the constant input pulse, slipped

U-T. . ♦ (7)

An embodiment of the basic circuit of FIG. 7 is illustrated in Figure * β dargeetllt · The collector of Iranaistore H _ connected to three output terminals · Die.Kollektorspannung is duroh passed the current applied to y _T Eingangsimpule to all branches ^ what the logical values τοη T ₁ , Y ₂ , Y, corresponds to "-Yyy

The logic function for this circuit is ^

UX (T ₁ HT ₂ + !,) ..... (8) «>

The diode introduced into the branch causes the flow of the Oegenatroma Terhemmen · Sin execution example of the logical The circuit according to the basic circuit from FIG. 7 is shown in FIG shown * The circuit (transmission circuit) increases there Ausmasa dfr external activity with an addition and is aua A Beihe Ton franaiatorenTerbindunÄen mufiro skin. di * ·

BATH

Orelements serve «In this circuit, Τ _{γ is} the output pulse transmitter and corresponds to the transmitter T from Pig * 7

The part surrounded by a dotted line in Pig.9 denotes a circuit unit for one bit. The transmission circuit for a number of bits is formed from the step connection of this circuit. The singing pulses for 0 _v and 3 _γ and S _v are applied to the terminals cj _y (s _r * A _Y ) and ev · Γ _ν / and

_r * A _Y

the corresponding transistors become conductive or blocked

The logical function for the output pulse obtained at i ^ is expressed in a logical value Z _y as follows

V ₁ - Co.

V ₂ - V ₁ ^ S ₁ + O ₁

Dit SOsktion disssr S ^ haltusg fird aachatthtad im © inzelaesx explained*

With this S

got

jO and Sg "1 £ -a ^ l" gt

TJ ^. Wis? D Jedoöli only *

lag impulses α

Way ^, and

flight® ia

dasig iat la 3rig «10

Binary saw! of η bite, expressed by 3> ⁿ

convert, and ewar τοη 0 to η Bite »G (X _y ) is the Xor element, which each bit X ^. corresponds to «Here G represents the gate element and means part 1, 2. ·· n. H ^ is the distributor that is controlled τοη β (X ^)« V (yu), where / u 0,1,2 .. .m means, if the voltage supplier, which corresponds to the bits in the conversion τοη X · T ₁ is the 1-output transformer, where 1 equals T + / uiat. The two ends of the primary winding of the output transformer, which is inserted into the branch line V (tai), are connected at tai and (tal) to the voltage feeder T (yAi), which is connected to the distributor M ^ rer. The upper end of the tai Primary winding is bundled with the lower end tai of branch line B (τai) τ, while the lower end (tai) of the primary winding with the upper end (y / U) of branch line B (τ ja) in Pig. 10 connected is »Even if T (yyu) is sucked and every branch line that

V (y / 0 connects, old negative voltage is seen, flows the current la none of the branch lines, provided that all gates are locked. But if Q (χ _γ ) an incoming pulse is introduced and becomes conductive »becomes U ^. grounded and the current flows into the branch lines B (τ μ) , and ewar τοη IE ^ to

V (τ Ai) * The output pulse is received via the output transformer T (t + / u), which is located in the branch line B (tai). When all · Tor · are applied, the output pulse is received via the corresponding output transformer T (2+ m) ... T (n + yu). In no case does the current flow through more than two primary windings of the same transformer, since there are never more than «knows, number parts corresponding to the bit to be converted at the same time, a V (γ Ai) is only determined la

809806 / 06A9 -H-

Instants fed. Since the presence or absence of the input pulse to which dtm ν-Τοτ is supplied determines the presence or absence of the (v + / u) output pulse, the input information chain with the sequence appears when V (y / u) is supplied (X *, X ₂ * ·· * _n ) at the output terminals, implemented duroh / uBits (Uj + Ja ₉ IT ₂ + M ·? · H _n + / u).

Pig * 11, another Ausführungsbdispiel shows a conversion circuit of the circuit in Fig gemäsa · 10, wherein Ξ is the SJorelement and G (X _T), ^a j ^and ^ o ^^ ^ers ^ ^ä walls are, E _fe is the positiT * Glelchforspannung «If aa x ^ and y _u are applied simultaneously, the emitter current flows into the upper transistor H and the Baäüstrom flows into the äenyu translator H · and M ₁ receives EM potential, where fii © terminals (n ^ u) ¹ * · (τ al) * ... (2 ßx} ' · «(1 äs.) ¹ ' ^ t: Potential -E received« In this way the connection between M ^ and one of the named terminals is excluded «- borrowed via branch line B (lyu), which leads into the Isipula transmitter T (1 + ytt), via which Auagangeiispals is received at the exit acleEinea u (1 + ya) cw * Ba dies © Klemaie also as liagangskle-mmeia for the other "iorea ^ (X_ .) inflicted

vs ± zkt _t eraöhsiat the starting impulse allgessia

(τ * a: K £ * s3? lcgisih® Eiagangimpula wi

gg Bits umgssetst »Bisdea for prevention

ätz IM & sxmi® nasty Segtastroa® sia.ä in the Iweigleiti ^

oi

803606/0648

Distributor ± ei low negative voltages held by -E ₂ , and the circuits R ₁ , -S ₂ block the small secondary current that flows into the branch lines eu of the non-fed voltage supply «M ^., Which is also connected to the conductive gate, reaches earth potential and supports the flow of the small side currents in the branch lines, which lead to the unpowered voltage supply lines »

These unexpected unsolicited statements are eliminated by the introduction of tone B ₂ for a low resistance between the gates and the distributors, because this is also conductive is held at a potential slightly lower than ground potential

Pig · 12 represents a circuit fcemäes the left cable of the circuit from Fig. 11 «In this circuit the tilting positions t _y ^{% are used as} all Xor elements α (Xy) according to Fig. 10. The external terminal of! F _y ^f either receives the potential 0 or the potential -e, corresponding to the input pulse values 1 or · 0 for X..

If ^ E ₁ , I ^ is conductive for O, and diode d is blocked for -e duroh. Zn Pig, 10 can also be used as KJ> ppcircuits ale V (y Ai) * In this case the output terminal of the trigger circuit receives either the potential -e odv * - the potential O according to the logical input pulse values 1 or O for Y au Der! Transistor H can also be used in emitter circuit and the Iraneittor E * in basic circuit «

⁴ Btf) ov- ^ i ^ · - ¹⁶ -809806 / 06A9

1424778

A further embodiment of the block holding according to the invention is shown in Pig. 13 · This circuit has the same puncture as the circuit from Pig · 10, but the arrangement of the voltage supply is different than in Pig »10 and no pulse transformers are required as output pulse elements, with the exception of the voltage supply (V (y / i) , Pas lower end vyu of V Cyyu) and the upper end VyU of output terminal U ₁ (l «v + yu) must be connected to one another. If the input pulse for 2L. «1 and Y *

() please

"G (Χ _γ ) becomes conductive as a result of its connection with and a voltage is induced between the two ends of V (yyu)" A current flows into the branch line that connects ML ait V (y ai) and at the Output terminal U ^ (l «v + m) an output pulse is received · IUh ,, the arrangements of V (y Ai) and the load resistor are interchanged in the Pig · 10 and 13»

Another embodiment of the converter circuit according to the block circuit from Pig 15 is in Pig *. H "In! This ** circuit, L Ai is a pulse transformer that is used as * Spa * imingssufUhrerV (yyu)" Pa H * feeds the primary winding of 1λ through the input pulse at y / U, the voltage in different secondary windings induces _t the all distributor M ^. connect to each other «Puroh the diode d, the counter current in the branch lines is blocked and have the OR puncture · Through it all branch lines leading to the same output terminal are connected to each other«

These tariffs can in principle not only be binary, but.

-17-

809806 / 06AQ '

-17-. U24728

can also be used with decimal or other number systems »which are to be represented as Sode τοη η bits · If ζ · Β · a decimal number is represented by a Drefer code, the value of each decimal level X ^ through the bits X ^ t X _& 2 » ^X d3 and X44 are expressed * If the circuit according to Pig» 14 is used, the distributors for X ^, X ^, - the circles M _d , M _d2 , M ^. ,, M ^, ^ a ₊ -J * ^M ^ ₊ 2 arranged, where four distributors are to be provided for each decimal level d, with the four ropes of the Selcundärwioklungen of the same transformer

LyVi are connected · These four branches become the corresponding ones Output terminals tu, vho 'u ·, - and u ,. fed, wherein

1 «ν / tt · This way the converter for the decimal sahl educated

These two converters can also be used as UHD presentations for each Two bits of the binary number are used · Using ζ 2 · Β · the circuit according to 3? Ig · 14 all diodes connecting the output terminals are disconnected and connected to the different ones The outputs are connected »This means that n2 ropes of the UBDr outputs obtained from the two numbers of η bits

The advantages of the invention are mentioned again in the following

amount of beef; ti ... ·. :. - - 1 * Di · logic circuit can be stable and cheap with

. Switching elements are constructed, such as diodes, transistors . and B ^ pttlsttbertragern *

2 »Ss köan * Ä complex logisical functions with smaller ones S * h * l% «lt« ducks are processed as with known ones

8Ö980 6/0 649 BAD C "

Circuits and transformers with several partial windings can be used be used.

3 »The efficiency is greater and there is less time for the regeneration reinforcement is required for complicated logical punctures, which means a higher working speed is achieved *

4 · The circuits can also be used for high frequencies · 5m For the main applications of the circuits, results

a) In arithmetic calculators the selective transfer circles are easy to set up for information of a certain size «'

b) Logisohe high-efficiency negative circuits such as they have to be used for many logical operations can, using the principle of the invention easily constructed wtrdtn *

o) The addition or subtraction in floating point mode as well as multiplication and division can be performed at high speed using the dtr converter *

809806/0649

Claims (2)

—19— -w »» / ψυΐιιΗ IQfift • • - fc «X. wUll! www Claims 1 »Logical circuit with at least two pairs of input terminals and at least one pair of output terminals, daduroh characterized in that a load impedance is inserted in a current branch of the circuit, to which a current generated by the input pulses is fed, and that with the Branches of the circuit are connected to gate circuits, the opening of which is controlled by the input pulses 2 »Logical circuit according to Claim 1, characterized in that that the outputs of the gates that are preferably consist of transistors, over windings separated transducers and over separate non-linear elements with the Auegangeklemmen are connected and connected in parallel there, such that an input pulse, the at least one of the Gate circuits opens when one is created at the same time Entrance iaapuliee to one or more of the carriers one Output coil generated 3 · Logisohe circuit according to claims 1 and 2, characterized in that each gate circuit has pairs of terminals for supply contains two input pulses, and that the outputs of the Gate circuits via windings of input pulse transformers and non-linear switching elements with the output terminals connected to the circuit and connected in parallel there in such a way that the output pulses are received at one of the pairs of output terminals » -20-809806 / 0649 Documents (Art. 7 § I Para. 2 no. 1 coaming 3 of the amendment guideline. v. 4. <■■. ^ A 4 «Logic circuit according to claims 1 and 2, characterized in that the output signal of each Iranaistor gate holding is determined by the counteraction of the emitter ·» and _{: of} the collector current, and that one input pulse is the base and the other input pulse is the. Collector of the transistor and the output pulse is derived from the Eraitterstrom » . 9U logical Sohaltung according to claim 1 and one or more of Other claims. daduroh marked that as Tor-Bohaltungon serving transistors over to voltage equipments leading branch lines and windings lying in some of these branch lines are connected in parallel and that these Branch lines connect the common output transformers, be in such a way that the corresponding Gyöss »corresponding to each bit, pulses applied to the transistors at the 'output transformers Output pulse ο that corresponds to the range of ι correspond to the converted number, 1st 6 «A logic circuit according to claim 1 and 2, gekex characterized. ^ .-» records, the output daaa each Transistorn via branch lines to a number of output terminals connected so that in agree "of the branch pipes windings are inserted, common, as SpannungsGLuelle iU" serving Connect the transformers, and that some of the two-wire lines lead to the common output terminals, so that when j ·, one . Bit corresponding singangclmpuleen to the Sraneistorsn output • ■ ■ * gangaiiapulses are obtained, which escape from the frozen rushes BAD QRiGiMAL ₁ 'COPY,