DE1266805B - Arrangement for phase comparison of two signals, especially in regenerating amplifier units of PCM systems - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

H 03 k

German class: 21 al - 36/12

Number:
File number:
Registration date:
Display day:

J 30688 VIII a / 21 al
April 27, 1966
April 25, 1968

When transmitting messages in digital form, especially when transmitting signals by means of Pulse-Code-Modulation (PCM) occurs with the pulses from which the coded signal is formed statistical probability. When you receive a message, you have to talk to a Calculate fluctuations in the point of use and the duration of the transmitted impulses.

In such a system, the information is transmitted one after the other in the form of numbers, which are expressed in a binary code, with each digit of the number being a for transmission Time interval is set. In general, a digit 1 is represented by the transmission of a Message signal, and with the digit 0 there is no transmission.

In certain systems, the transmission of a message signal is done by sends out a current of a given polarity on the line for a fraction of a time (generally half of the time reserved for the message signal). These systems are under known as the "return to zero" system. Sometimes you also change the polarity of the successive ones Message signals so that one can have a system with unipolar and alternating pulses Has polarity. This system is known under the name "alternate polarity return to zero system".

In other systems, a message signal is transmitted by throughout for the signal For a certain period of time, two currents of opposite polarities are transmitted one after the other via the line will. These systems have bipolar impulses and are called "no return to zero system" known.

In an analogous manner, a message signal that is in the form of a pulse (generally, but not necessarily, of the form factor |) and has an amplitude of V with respect to earth is referred to as unipolar. When consecutive, but not necessarily adjacent, signals have alternating polarity, these signals are said to be unipolar with alternating polarity. Finally, when a communications signal consists of a pulse of one polarity followed by a pulse of the opposite polarity, it is called bipolar.

During the transmission, the time intervals for the signal elements that are assigned to the various digits are generated by a clock with very high stability. During the transmission, the message signals are subject to weakening in an arrangement for the phase comparison of two signals,
especially in regenerating amplifier points of PCM systems

Applicant:

International Standard Elektric Corporation,
New York, NY (V. St. A.)

Representative:

Dipl.-Ing. H. Ciaessen, patent attorney,

7000 Stuttgart W, Rotebühlstr. 70

Named as inventor:

Michel Louis Avignon,

Neuilly-sur-Seine, Hauts-de-Seine (France)

Claimed priority:

France of April 30, 1965 (15 270)

the amplitude and disturbances in the phase so that it becomes necessary to recreate them in an amplifier to regenerate. This amplifier contains a simplified central clock generator, which is e.g. Message signals is synchronized.

To synchronize the central clock, it is necessary to know the phase differences, those between the message signals defined above and those generated by this clock Signals, d. H. to generate a voltage, the amplitude of which is a function of this phase difference and to use it to determine the frequency of the oscillator of the central clock to control. This phase comparison circuit is generally known under the name phase discriminator.

Since the signal is usually sampled in its center during regeneration, it is at one "Return to zero" code is advantageous, one between the received signal and the local signal To select a phase shift of 90 ° and to scan it with the corresponding pulse edge.

The principle of measuring the phase difference between two signals of the same nominal frequency is well known and consists in the fact that the position of the leading or trailing edge of the signal pulses with z. B. the leading edge of the corresponding

809 540/371

3 4

compares the clock pulses and a voltage from the leading and trailing edges of a unipolar

conducts whose amplitude is the phase difference propor- pulse of the message signal B compared to the

is tional. Leading edge of a corresponding pulse of the

The implementation of this principle generally results in reference signal A, which is unipolar (FIG. 3). It will

nen to complex circuits, which among other things 5 thereby assumed that the signals have a positive

balanced differential amplifiers included. Amplitude V compared to the potential 0 V at ground

The invention has for its object to have one.

Arrangement for phase comparison of a coded, In the F i g. 1 and 2 represent the with the reference from unipolar pulses with alternating characters 3, 4, 13 and 14 designated circles electro-polarity existing signal with statistical ver io nical AND gates, which at their distribution of the occurrence and with fluctuations of the on - Gangs emit a positive signal if at the set point and the duration of the impulses with one of their inputs, which are represented by the periodic bipolar signal of the same frequency, the arrows, which touch the circle, at the same time a positive signal at their output is one of the phase deviation pro- obtain. The duration of the output signal corresponds to the proportional size emitted, in particular for the comparison of the coincidence of the positive input signals. If, like the received pulses with locally generated, the clock pulses present at the two inputs are designated signals A and B in regenerating amplifier points, these are implemented by pulse code modulation systems in which the circles meet the logical condition AB.
output size for readjusting the local In the same F i g. 1 and 2 represent the circles used with the clock to create the simpler 20 reference numerals 5 and 15, respectively, which one is constructed. Number 1 contain OR gates that

According to the invention, this is achieved by emitting a positive signal at their output when two branches with three transistors (51, 52, 53) each have a positive signal applied to at least one of the inputs which are the same but different from the other branch. If the pre-conductivity type inputs are provided, so that each branch 25 is denoted by C and D signals, that of two emitter followers (51, 52) with a common logic function is denoted by C + D.
Emitter resistor (Rl) and a downstream die rectangle, 2 or 11, 12 represent inverter transistor stage (53) in a base circuit, their base, which give a + V at the output when fixed at potential by a voltage divider (RR) Input a signal with the potential 0 V is applied, the emitter potential of which is applied by the 30, and a signal with 0 V if a signal with the potential + Fön is present at the input emitter sequences common emitter resistance combined with a signal with the potential + Fön. If you change with E and its collector is denoted by that of the respective input signal, you denote the speaking stage of the other branch and with which the output signal with Έ, which is connected to the complementary output, is that in itself is valued shown for E.

known way in the branches of conductivity type 35 It can be seen that the circuit according to FIG

corresponding potentials are switched on, that the logical function

unipolar and bipolar pulse sequences each have a C = ΑΉ -l · ~ ÄB
Control electrode of an emitter follower stage in each

Branch (51, 61) is supplied, which represents these stages in Ab-, while the circuit according to FIG. 2 the

dependence on the polarity of the applied pulses 40 logical function

and the conductivity type of the transistor by- D = AB + A ~ E
control or lock, and that over one in the

Output switched on capacitor is shown in itself. It can also be seen that C = B

known way by integration is the output signal. So the two circuits give a similar one,

is formed. 45, however, is an inverted signal and you can therefore use the

The invention will now use one or the other on the basis of the

In certain circuits, such as, for example, in the

purifies. It shows French patent specification 1 379 675 (German ex

F i g. 1 and 2 schematic implementation examples are described in Legeschrift 1 221 278)

of a circuit to compare the phase of the two 50 signal C passed through a low-pass filter whose output

Signals applied to the inputs, output voltage M with the mean voltage M ₀

F i g. 3 diagrams of signals, of which the phase of the clock signal via a differential amplifier with the aid of the circles in FIG. 1 and 2, whose two outputs R and Q are to be compared with, are connected to an integrating circuit. A positive one

Fig. 4 diagrams of signals that appear in an er 55 signal at the output R, if M ^> M ₀ and

inventive circuit compared in phase a negative signal appears at output Q when

as well as diagrams of signals that are located at M <CM _Q is. The output 5 of the integrating circuit

result from this comparison, and thus produces a voltage that is the integral as a function

F i g. 5 represents an exemplary embodiment for the time of the differential voltage (M - M ₀ ) according to the invention,

proper arrangement. 60 For various purposes, the unipolar

Figs. 1 and 2 represent two by the French message signals B (Fig. 3) for reasons that

see patent 1,379,675 which is post-published outside the scope of the present invention

clear German Auslegeschrift 1 221 278 corresponds, lie, in unipolar signals with alternating PoIa-

known schematic examples of the implementation rity reshaped, as shown in line 2 of FIG. 4th

of a circle for comparing the phases of the two shown in 65 and identified by the reference character Bb .

Fig. 3 represented signals ^ and B , which are drawn to the. These signals Bb can be used directly for

can be applied to both inputs of these circuits. The phase comparison with the clock signals A (Fig. 3)

Phase comparison takes place by comparing the used by the invention

Circuit is used after the signaled are converted to bipolar signals as shown in line 1 of FIG. 4 and are provided with the reference symbol Ab .

One possible implementation of this circuit according to the invention is shown in FIG. 5, in which transistors 51, 52 and 53 are like transistors of the PNP type, while transistors 61, 62 and 63 are like transistors of the NPN type. If the inputs E1 and E 2 are not connected to one another or if they receive signals whose amplitude is between + ~ y- and

- w · lies without reaching these limits are those

²

Transistors 51 and 52 are conductive and transistor 53 is blocked because the potential at its emitter is through the base potential of one or the other switched transistor 51 and 52 is determined, the

has a value between + -y- and - ψ , while

its base is on a potential of + -γ . The transistor 63 is blocked in the same way, since the transistors 61 and 62 are conductive. So there is no current flowing that can charge the capacitor 50, and the voltage VS at the terminals of the capacitor does not change.

If a negative signal with the amplitude at the input EX a positive signal with the amplitude + V and the input E 2 - V is applied, the transistor 51, the transistor 52 is blocked, however, conductive, so that the transistor is blocked 53rd In the other way, the transistor 62 is blocked, while the transistor 61 is conductive and the transistor 63 blocks. The transistors 53 and 63 are thus locked, and no charging current flows to the capacitor 50. A corresponding consideration shows that capacitor 50 also does not charge when the input El is a negative signal with the amplitude - V and the input E 2 a positive signal with the amplitude + V is present. If 2 simultaneously positive signals applied to the inputs El and E of amplitude V, the transistors 51 and 52 off and the transistor 53 conductive and acts as a constant current generator, so that a current / 1, the value of

is about, the capacitor during a

Time loads which is equal to the duration of the coincidence of the positive signals at the inputs E1 and E2 . This period of coincidence is shown in line 3 of FIG. 4 for the signals Ab and Bb of lines 1 and 2 of the same figure. During this time, the current / 2 is equal to zero, since the transistors 61 and 62 are conductive and consequently the transistor 63 is blocked.

If on the other hand to the inputs El and E2 simultaneously negative signals with amplitude - V applied, the transistors 51 and 52 are conductive, and the current / 1 as a result of the disabling of transistor 53 equal to zero. The transistors 61 and 62 are blocked, however, so that the transistor 63 is conductive

and emits a constant current / 2 = γηγ, the Il mes 12 shown as a function of the pulses in lines 1 and 2. Line 5 shows the signal resulting from the sum of the currents / 1 and / 2. The equality of the currents / 1 and / 2 is obtained by mutually symmetrical transistors 53 and 63, which are mounted in the same way, with the same resistors R1 in the emitter circuit and the same resistance voltage divider between the supply voltage and ground, which have the same resistors /? are constructed. The effect of an imbalance between the values of the currents / 1 and / 2 will be explained later.

It can be seen from this that the current 71 charges the capacitor 50 in such a way that the charging voltage VS, which occurs at the point S , becomes more positive, while the current 72 charges the capacitor negatively, ie discharges it when VS is positive.

With each charging current pulse, the change is d VS

the voltage VS given by d VS = \ - ~ \ dt, where 7 denotes the intensity of the pulse current which is emitted by the current generator and can be positive or negative, C is the capacitance of the capacitor 50 and di is the duration of this pulse.

It can be seen that when 7 and C are constant values, the change in voltage VS during a current pulse is proportional to di. Or in other words, di is for successive message signals Bb alternately equal to the duration of the coincidence of the positive and negative input pulses of these signals with the pulses of the same sign of the clock signals Ab, so that the change in voltage dVS is proportional to the duration of the coincidence and alternating from the sign "plus" or "minus" is influenced, depending on whether one carries out a coincidence of the positive impulses, ie whether one measures the position of the trailing edge or a coincidence of the negative impulses, ie whether one measures the position of the leading edge. For two consecutive pulses of the signal Bb in which two changes in the voltage result in the opposite sense, their algebraic sum, implemented by the capacitor 50, results in a change in the voltage d VS2 proportional to the difference in the measured phase for these two pulses.

If one denotes the absolute mean value - expressed in natural angular measure - of the position of the leading edge of the signal Bb opposite the leading edge of the corresponding pulses of the signal Ab and am denotes the absolute mean value, expressed in the same way in natural angular measure, the position of the trailing edge in With reference to the same leading edge of the signal Ab (diagram 2 of FIG. 4), the result is:

7 , _n , T

is the same but flows in the opposite direction. The duration of the occurrence of this current / 2 is equal to the duration of the coincidence of the negative input signals. In line 4 the duration of the occurrence of the Stro C is 2%

In this formula, T denotes the duration of one bit of the clock signal sequence A b.

If <xm + βm = π , that is, if the clock pulses have the same duration as the pulses of the signal Bb , the charge voltage VS of the capacitor 50 after N pulses is equal to the sum of the elementary changes dVS2, namely

VS = (\ (2 <xm - π) ;

all parameters of this formula have already been explained above.

Lines 5 and 6 of FIG. 4 express in a very simple way that the electrical charge by which the capacitor 50 is charged in the positive direction is proportional to am , while the electrical charge which discharges it is proportional to ßm so that the capacitor assumes a charging voltage VS (line 6) which is proportional to am - ßm , ie the phase difference based on a 90 ° phase shift.

In line 2 of FIG. 4, the leading and trailing edges of the signal Bb are dashed to indicate that their position can oscillate around the above-mentioned mean values βm and am. These broken lines are also found again in lines 3, 4 and 5. Line 6 in FIG. 4 gives the shape of the voltage VS under the assumption that the capacitor 50 is ideal.

If one denotes the mean number of pulses per unit of time with P and the time with t , one obtains: N = Pt, and the formula then reads:

P · Τ · Τ

VS = (2am ~ π) t.

AnC

This formula shows that the change in the voltage or the charge of the capacitor 50 is a linear function of t over a sufficiently long time, the slope of which depends on the two parameters am and P.

This voltage VS can be used to control the frequency of the clock oscillator which emits the signal A b , so that its phase is set to that of the message signal Bb . A feedback path is thus implemented which changes the function which indicates the change in the charging voltage VS of the capacitor 50 as a function of time. At the start of such a closed loop circuit, the capacitor 50 is not charged and, in general, the signals Ab and and Bb are out of phase, so that the capacitor charges in such a way that it increases the frequency of the Clock oscillator, which outputs the signal Ab , changes in such a way that the phase shift between the signals A b and Bb is reduced. After a more or less long time, the phase angle between the signals Ab and Bb has the value am = - | -. At this value, the capacitor 50 charges and discharges by the same values, so that the charging voltage VS of the capacitor fluctuates slightly around a mean value. This voltage VS can, for. B. applied to a "Varicap" diode, which is arranged in the oscillator's resonant circuit. This diode is characterized by a capacitance, the value of which fluctuates with the voltage applied to it.

If the two paths are not symmetrical with one another, especially if the transistors 63 and 63 do not emit currents with the same absolute amplitude, the mean position of the signals is Ab

and Bb among each other no longer am = -, but am = -γ + a, where α is a constant value, but for a given circuit, the greater the asymmetry between the two paths.

Such a circuit with identical transistors in each path that are built symmetrically, can be set up as an integrated circuit.

Claims (1)

Claim: Arrangement for phase comparison of a coded signal consisting of unipolar pulses with alternating polarity with statistical distribution of the occurrence and with fluctuations in the point of use and the duration of the pulses with a periodic bipolar signal of the same frequency, which emits a quantity proportional to the phase deviation at its output, in particular to compare the received pulses with locally generated clock pulses in regenerating amplifier points of pulse-code modulation systems, in which the output variable is used to readjust the local clock, characterized in that two branches with three transistors (51, 52, 53) each are the same , but on the other branch of different conductivity types are provided that each branch consists of two emitter followers (51,52) with a common emitter resistor (Rl) and a downstream transistor stage (53) in a base circuit, the base potential of which is determined by a voltage divider (RR) n emitter potential is changed by the emitter resistance common to the emitter followers and the collector of which is connected to that of the corresponding stage of the other branch and to the output and the bipolar pulse sequence is fed to a respective control electrode of an emitter follower stage in each branch (51, 61), which control or block these stages depending on the polarity of the applied pulses and the conductivity type of the transistor and that via a capacitor connected to the output In a known manner, the output signal is formed by integration. Considered publications:
French patent specification No. 1379 675. 1 sheet of drawings 809 540/371 4.68 © Bundesdruckerei Berlin