DE1250533A1 - - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE *

EDITORIAL

Int. Cl .:

G05b

G05f

German class: 21c-46/50

Number:
File number:
Registration date:
Display day:

L 53020 VIII b / 21 c
March 5, 1966 ^
September 21, 1967

The invention relates to an arrangement for monitoring or regulating with means for a signed comparison of two pulse frequencies and for outputting output pulses when a Schjn ^ chjj ^ i ^^ vojOE ^

Time. ~ *

"Such an arrangement is already known in which the pulse frequencies with an up-down counter can be compared with two inputs. Run into the two inputs of the up / down counter If the number of pulses per unit of time is not the same, it is switched on according to the difference between the pulses. When exceeded a switching threshold of +2 differential pulses controls an actuator and the up / down counter reset to its original state.

In the up / down counter, however, the two pulse frequencies can be counted in almost simultaneously disturbing, scattered errors occur. During a certain switching time from , No pulses may be fed in forwards or backwards operation. There is also an up / down counter relatively expensive, since gate circuits are required to switch the counting direction.

Another known arrangement works with two presettable counters, one before and one downward-counting differential counter and a control unit. The two pulse rates to be compared are fed into one meter each. After a measuring time, which is due to the full counting of the a counter is given, a difference number with the correct sign is in the difference counter counted integrating. Then both counters are reset and the process is repeated himself.

In this case, no unsystematic error can occur in the differential counter, since the pulse frequencies not output immediately, but as numbers from the counters at the end of longer measuring periods will. However, with very high demands on the control dynamics, it can be disadvantageous that the counting time appears in the control loop as dead time. The effort of the arrangement is with two counters, a difference counter and a control part are quite high.

The state of the art also includes a device for monitoring or control in which the The signal of the controlled variable is a pulse frequency. This pulse frequency is applied to a monostable multivibrator with adjustable tilt length. The initial

Arrangement for monitoring or regulation with means for signed-weighted comparison
two pulse rates

Applicant:

Licentia Patent-Verwaltungs-G. mb H.,
Frankfurt / M., Theodor-Stern-Kai 1

Named as inventor:

Dipl.-Ing. Hermann Ragnar Eggers,

Klaus Schlömer, Heiligenhaus

size of the flip-flop and the half-cycle duration of the pulse frequency are compared in AND gates, the Generate actuating pulses that are dependent on the size and direction of the difference.

Since with this device only the signal of the controlled variable is fed in as a pulse frequency, while the reference variable is to be set by the tilting length of the monostable tilting stage, are the Uses limited. For example, a ratio control with a second pulse frequency can be used do not perform as a reference variable. Apart from that, with the influence of errors Fluctuations in the adjustable tilt length of the monostable multivibrator can be expected so that the high accuracy aimed for with digital technology cannot easily be achieved.

The invention is based on the object of an arrangement for monitoring or regulation to create the two pulse frequencies without disturbing errors even with critical frequency conditions and compares phase positions. The time units for carrying out a comparison should be possible be short. In addition, the arrangement with these properties should be easy to use distinguish.

The invention consists in that two pulse memories are provided for three memory states each, each of which has an input input counting in one direction, a priority clear input and have an output emitting an output pulse in the third memory state, and that the Input input of one pulse memory as well as the delete input of the other pulse memory with the a pulse frequency and the delete input of one pulse memory as well as the input input of the other

709 648/257

ren pulse memory are acted upon with the other pulse frequency.

This has the particular advantage that when switching from up-down counters for certain frequency and phase relationships occurring difficulties and the resulting the following possible errors are avoided. In the arrangement according to the invention is namely for each sign of the pulse frequency difference provided a pulse memory that is independent of the other pulse memory works.

The total cost of the arrangement is relatively low, since each pulse memory is only in counting in one direction needs to assume three memory states and only through deletion a memory state can be reset, so it is uncomplicated. A special Control device is omitted, because the pulse memory are designed so that in a pulse memory automatically between two pulses of the lower pulse frequency the comparison with the higher pulse rate expires.

Because with frequency deviations in one sense and in the other only a certain pulse memory emits an output pulse, the output pulses are signed. You can in the simplest way, e.g. B. in a limit monitor or an interlocking for a servomotor, processed will.

If the difference frequency falls below a certain value, arise as a result of the priority Delete inputs and the duration of the delete no disruptive output pulses with undefined changing Sign.

To specify the duration of the deletion, the arrangement according to the invention is expediently designed so that the pulses at the input input only switch dynamically with one edge and the pulses at the Extinguishing input are statically effective for a longer period.

The effort for the arrangement according to the invention is to be kept particularly low in that each pulse memory using a bistable multivibrator with a dynamic input to the Saving and a static input for deletion as well as another bistable multivibrator is constructed, which apart from a dynamic input for storing and a static input for Delete a preparatory input connected to the output of the other flip-flop Storing has, and that the dynamic inputs and the static inputs with each other are connected.

Cheap, commercially available flip-flops can be used for the two pulse memories if their inputs be trained and linked as required.

In the case of the arrangement according to the invention, for a ratio of the pulse frequencies from 1: 1 to 2: 1 is the number of output pulses over a longer section directly the difference between the pulse frequencies. For higher pulse frequency ratios, it may be desirable to have additional output pulses with a certain reduction ratio to spend. This is achieved by the further measure that in each pulse memory the second flip-flop is also equipped with a dynamic input for deletion, which with the

other dynamic inputs is connected. The additional dynamic input usually available per se, so that the desired characteristic does not require additional expenditure limited to components.

As already mentioned, in the subject matter of the invention, the reliable erasure of the pulse memory during a defined erasure period is essential in order to achieve the advantageous effects. This ίο is made easier by two pulse amplifiers to amplify the two pulse frequencies, which are fed into the static delete inputs of the pulse memory.

Embodiments of the invention are shown in the drawing and are described below described in more detail. It shows

F i g. 1 an arrangement for regulation with comparison of two pulse frequencies Z ₁ and Z ₂ >

F i g. 2 an essential part of the arrangement in ao detailed representation,

F i g. 3 timing diagrams of the course of action for Z ₁ greater than Z ₂ and

F i g. 4 time diagrams of the course of action for Z ₁ less than f _t .

Corresponding parts have in FIGS. 1 and 2 have the same reference numerals.

In Fig. 1, lfl, 11 denote two pulse memories for three memory states "0", "1", "2" each. Each pulse memory has an input input 12 or 13 that counts in one direction, a priority clear input 14 or 15 and an output 16 or 17, which emits an output pulse in the third memory state "2". The input 12 of the pulse memory Ifl is connected to the output of a pulse shaper 18 to which a frequency Z _{1 is} applied. In addition, the output of the pulse shaper 18 is connected to the delete input 15 of the pulse memory U. Similarly, another pulse shaper 19 for the frequency Z ₂ feeds the memory input 13 of the pulse memory 11 and the delete input 14 of the pulse memory Iii. Connections lead from the two outputs 16 and 17 of the pulse memory to an interlocking 20 of a stepping motor 21 serving as a servomotor.

The mode of operation of this arrangement is as follows:

Each pulse of the pulse frequency Z _t switches the pulse memory 10 to the next higher memory state and at the same time deletes the pulse memory 11. In a similar way, a pulse of the pulse frequency / _{2 influences} the pulse memory U to set the next higher memory state and the pulse memory 10 to delete it to "0" .

An output pulse is now generated at the output of that pulse memory, which, as a result of the pulses at the input input counting in one direction, reaches memory status "2", which has not previously been reset to its reset input by a pulse. In principle, two pulses must therefore occur at the input input for an output pulse during a time unit which is given by two consecutive pulses at the clear input. Output 16 or 17 then emits an output pulse between the second signal at the input input and the following pulse at the reset input. It is easy to see that an output pulse can only arise at output 16 if Z _{1 is} larger

than J ₂ , and that, conversely, the output pulse will appear at terminal 17 if Z _{1 is} less than Z ₂ . The output pulses are therefore signed.

By the structure of the interlocking 20 can be achieved that for the stepper motor 21 z. B. corresponds to an output pulse at the output 16 one step clockwise and an output pulse at the output 17 one step counterclockwise.

In addition, instead of the signal box or to it a monitoring device can be connected in other embodiments, to the terminals 16,17, which signals the undershooting of a limit value for an output pulse at terminal 16, the exceeding of a limit value and an output pulse at terminal 17th

The effect of the priority erasure of the pulse memories 10 , 11 will be explained in connection with the explanation of FIG. 2 described.

From Fig. 2 shows in particular the structure of the pulse memories 10 and 11 :

Both pulse memories have two bistable flip-flops 22, 23 and 24, 25 , respectively. Each flip-flop is equipped with a dynamic input for storing, a static input for deleting and an output, marked with a tip. In connection with the output 26 or 27 of the flip-flop 22 or 24 there is a preparatory input of the flip-flop 23 or 25. The outputs 16, 17 of the flip-flops 23, 25 also represent the outputs of the entire pulse memory 10, 11. The dynamic Inputs of the flip-flops 22, 23 are combined to the input input 12 of the pulse memory 10 and the dynamic inputs of the flip-flops 24, 25 to the input input 13 of the pulse memory 11 . The static inputs for erasing the flip-flops 22, 23 are led to the erasing input 14 of the pulse memory 10 and the static inputs for erasing the flip-flops 24, 25 are led to the erasing input 15. While the dynamic input inputs are fed directly by the pulse shapers 18, 19 assigned to them, pulse amplifiers 28, 29 are arranged between the static canceling inputs and the pulse shapers.

The pulse amplifiers give an amplified pulse for each pulse at their dynamic input constant length. The bistable multivibrators in the pulse memories can have two switching states accept:

An L signal appears at the outputs under consideration when the flip-flop has been deleted, and a 0 signal when it saves a value. The static inputs for deleting the multivibrators are effective for the entire duration of a positive pulse, whereas the dynamic inputs only respond to the edges of the pulses during the LO transition.

The signed comparison of two pulse frequencies in the arrangement according to FIG. 2 is on Hand of fig. 3 and 4 explained. At the beginning of the observation, all pulse memories or flip-flops should be be deleted.

In Fig. 3 it is assumed that the pulse frequency Z _{1 is} higher than the pulse frequency / ₂ .

First, a pulse of the pulse frequency / _{2 is} stored at the input input 13 in the flip-flop 24.

chert, so that the output 27 switches from L to 0 with a short switching delay. In contrast, this pulse is not stored in flip-flop 25 , because its preparatory input for storing is only at the required zero potential due to the switching delay when the LO edge of the pulse at the dynamic input for storing has already decayed. The amplified positive pulse at the static clear input 14

ίο has no effect because the flip-flops 22 and 23 have already been deleted.

With the subsequent pulse of the pulse frequency Z ₁ , which occurs as a positive pulse at the extinguishing input 15 , the flip-flop 24 with the output 27 is reset. The edge of the pulse switches the flip-flop 22 with the output 26 and thereby prepares the flip-flop 23 for storage.

The next pulse of the pulse frequency Z _{1 has} no effect in the completely erased pulse memory. In the pulse memory 10, however, the prepared flip-flop 23 flips and its signal at the output 16 changes from L to 0. The output pulse thus produced indicates that two differential pulses occurred in one time unit and that Z _{1 is} greater than Z ₂ . The second amplified, positive pulse of the pulse frequency Z ₂ at the static erase input 14 restores the original state of the pulse memory 10 .

In FIG. 4, in contrast to FIG. 3, the pulse frequency Z _{1 is} smaller than the pulse frequency Z ₂ J ^and the LO edges of the first pulse of both frequencies are in phase. Since these pulses are increasingly applied to the priority clearing inputs 14, 15, all flip-flops of the two pulse memories 10, 11 remain in the original, cleared state.

If the pulse of the pulse frequency Z ₂ lags behind the pulse frequency Z ₁ within the duration of the amplified pulse, it also has no effect in the pulse memory 10 because of the priority of the static delete input 14 . If the momentum of the PulsfrequenzZo other hand, before the LO-edge of the pulse of the pulse frequency Z ₁ on, then the output switches the flip-flop circuit 27, although for a short time until the arrival of the pulse of PulsfrequenzZ ₁ from L to 0; but there is no output pulse because the flip-flop 25 maintains its extinguished state.

If, however, the next pulse of the pulse frequency Z ₂ comes after the amplified, positive pulse of the pulse _{frequency Z 1 has} decayed, the flip-flop 24 in the pulse memory ll flips and prepares the flip-flop 25 . The following pulse of the pulse frequency Z ₂ switches the flip-flop 25 , and an output signal is produced at the output 17 which indicates that the switching threshold of two differential pulses for Z ₂ greater than Z _{1 is exceeded.}

The trigger stage 25 is reset dynamically by a further pulse at the pulse frequency Z ₂ , so that the signal at the output 17 becomes L again.

If a further pulse of pulse frequency Z ₉ comes before a pulse of pulse frequency Z ₁ , the flip-flop switches back to the storage position, since the preparatory input for storage is still subjected to a zero signal. Accordingly, after the first output pulse, after two additional pulses at the pulse frequency Z _2, a second output pulse is produced at the output 17.

Claims (5)

The flip-flops 24, 25 in the pulse memories are statically reset only by a further positive pulse at the pulse frequency Z1 at the reset input 15. Patent claims: 1. An arrangement for monitoring or control with means for the signed comparison of two pulse frequencies and for the output of output pulses when a switching threshold of + 2 differential pulses per unit of time is exceeded, characterized in that two pulse memories (10,11) are provided for three memory states each, each an input input (12 or 13) counting in one direction, a priority clear input (14 or 15) and an output (16 or 17) that emits an output pulse in the third memory state, and that the input input (12) of the one pulse memory and the delete input (15) of the other pulse memory with one pulse frequency (Z ₁ ) and the delete input (14) of the »one pulse memory and the input input (13) of the other pulse memory as with the other pulse frequency (f ₂ ) are applied. 2. Arrangement according to claim 1, characterized by pulse memory with input and clearing inputs designed in such a way that the pulses at the input input only switch dynamically with one edge and the pulses on Extinguishing input are statically effective for a longer period (Fig. 2). 3. Arrangement according to claim 2, characterized in that each pulse memory (10 or 11 ) using a bistable flip-flop (22 or 24) with a dynamic input for storing and a static input for erasing and another bistable flip-flop (23 or . 25) is constructed, which has, in addition to a dynamic input for storing and a static input for erasing, a preparatory input for storing connected to the output (26 or 27) of the other flip-flop, and that the dynamic inputs and the static inputs are interconnected are (Fig. 2). 4. Arrangement according to claim 3, characterized in that in each pulse memory the second flip-flop (23 or 25) is additionally equipped with a dynamic input for deletion, which is connected to the other dynamic inputs (Fig. 2). 5. Arrangement according to one of claims 1 to 4, characterized by two pulse amplifiers (28, 29) for amplifying the two pulse frequencies (F i g. 2) fed into the static erase inputs (15, 14) of the pulse memory. Publications considered: German Auslegeschriften No. 1 077 307,
861; "ETZ-Α", Vol. 82, H. 18, 1961, p. 575. For this purpose, 1 sheet of drawings 709 648/257 9. 67 Q Bundesdruckerei Berlin