DE1240961B - Method for attaching semiconductor chips to an insulating substrate and for producing an insulating substrate that can be used therefor - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY Int. Cl .:

HOSk

GERMAN

PATENT OFFICE

EDITORIAL

German class: 21 a4 - 75

Number: 1 240 961

Filing date: J 28815 IX d / 21 a4

Opening day: August 19, 1965

Case number: May 24, 1967

The invention relates to a method for securing semiconductor wafers on an insulating substrate for the purpose of producing a single-layer integrated to be provided with several semiconductor wafers Circuit, in which in a plane on the semiconductor die arranged, coated with solder Contacts are soldered to metallic connecting conductors arranged on the insulating substrate.

In a known method for producing integrated circuits of the type mentioned Semiconductor components made of silicon are made in such a way that all electrodes are in one plane on one surface are arranged. Such components have become known as "planar components". Relatively large-area contacts are made on the electrodes by vapor deposition with well-adhering and Soft solderable contact material is formed, which extends over the protective oxide layer on the semiconductor wafer extend. These contacts are made by dipping the semiconductor wafer in which the individual Components formed together were coated in a solder bath with the solder.

After dividing the disc into the individual plates 1, the plates are turned around and accordingly F i g. 1 is soldered to the thin-layer copper conductor 2, which is arranged on an insulating pad 3 are. One of the problems with this procedure ;; is that the solder 4 to the edge of the Semiconductor wafer and can flow around the passivating oxide layer 6 and thereby the semiconductor body 7 and the associated electrode 8 short-circuits.

The object of the invention is to avoid this disadvantage. This is done in a method of the above Type achieved according to the invention in that the thickness of the metallic connecting conductor in the area the solder contacts are larger than near the edge of the semiconductor die.

In an embodiment of the invention, silicon is the preferred material for the semiconductor wafers used. A method of making one useful in the method of the invention Isolierunterlagc consists in that the applied metal layer is initially reduced to about half the thickness Except for the contact zones is etched off and then the line pattern is etched out. Advantageous is used as a material for the metallic connecting liters Copper used.

The invention is now based on the in the Zcichiiuii!> illustrated figures described.

Fi g. 1 shows an arrangement such as that described by the above well-known process has arisen:

Method of securing semiconductor wafers to an insulating substrate and of manufacturing
an insulating pad that can be used for this purpose

Applicant:

German ITT Industries G. m. B. H.,

Freiburg (Breisgau), Hans-Bunte-Str. 19th

Named as inventor:

Geoffrey Arthur Leonard King, London

Claimed priority:

Great Britain September 15, 1964 (37 615)

F i g. 2 shows a process stage in the etching of an insulating substrate according to the invention;

F i g. FIG. 3 shows the position of a semiconductor die in relation to an etched line pattern according to FIG Invention.

According to FIG. 2 a pre-etching is carried out during the etching of the line pattern on the insulating substrate 3, in which about half the thickness of all conductors is removed, except for the places that later under the contact surfaces of the semiconductor wafers come to rest and the in Fi g. 2 are denoted by 9. Then the line pattern becomes that too in Fig. 1 is used, formed as shown in FIG. 3 is shown.

The contact surfaces 8 of the semiconductor wafer are thereupon with the copper conductors 2 on the thicker ones Places 9 connected. The solder 4 with which the contacts 8 of the semiconductor die are coated, and that in FIG. 3 is designated by 10, has the tendency to the step-like paragraph in the course of the conductor 2 and is not pressed around the edge of the plate as in Fig. 1.

The example shows three-terminal semiconductor wafers, but the invention is not limited to this. The double etching of the conductor can be anywhere on the insulating pad and can be made for any number of contacts.

A typical transistor chip has e.g. B. a page length of 0.625 mm, and the contacts have a length of about 0.125 mm. The dimensions of the However, the plate and the contacts can also be larger or smaller.

709 587/212

The line pattern can be masked using screen printing or photolithographic processes or by any other known method.

The advantage of the method according to the invention is that in the mass production of such integrated circuits of the scrap of unusable copies in contrast to the known The process is extremely low because short circuits through the solder are practically impossible are.

Claims (4)

Patent claims: 1. Method for attaching semiconductor, wafers on an insulating substrate for the purpose of production a single-layer integrated circuit to be provided with several semiconductor wafers, wherein in a plane on the semiconductor die arranged, coated with solder Contacts are soldered to metallic connecting conductors arranged on the insulating base, characterized in that the thickness the metallic connecting conductor (2) in the area of the solder contacts (9) is selected to be larger than in near the edge of the semiconductor die (1). 2. The method according to claim 1, characterized in that silicon platelets with through Diffusion generated planar components are used. 3. A method for producing a in the method according to claims 1 and 2 usable Insulating pad, characterized in that the applied metal layer initially is etched to about half the thickness with the exception of the contact zones (9) and then the line pattern is etched out. 4. The method according to claims 1 to 3, characterized in that metallic connecting conductors 2. Made of copper can be used. 1 sheet of drawings 709 587/212 ö. 67 © Bundesdruckeiei Berlin