DE1226643B - Circuit arrangement for the synchronization of pulse trains with a clock pulse frequency with simultaneous additive linking of the pulse trains of several channels - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

H 03 k

German class: 21 al - 36/22

Number:
File number:
Registration date:
Display day:

P 36594 VIII a / 21 al
April 23, 1965
October 13, 1966

The invention relates to a circuit arrangement for the synchronization of pulse trains with a clock pulse frequency with simultaneous additive Linking the pulse trains of several channels, in other words on one circuit arrangement for the summation of uncorrelated pulse trains.

For simple arithmetic operations within frequency-analog controls one uses known Way frequency-modulated, uncorrelated pulse trains, which are processed with advantage in counting devices will. With any series of impulses, impulses from different channels can coincide in time appear. If the channels are linked to the summation of the pulse series via an OR function, then appears at their output and thus at the input of a downstream counter instead of the number of coincident ones Impulse just an impulse. In known devices for summing uncorrelated pulse series Therefore, the signals of the individual channels are fed to buffers, which are cycled be queried. The required buffer time is determined by the requirement that a Pulse of the clock frequency will certainly take effect during this time; it must therefore be greater than that Period of the clock frequency. With the appropriate phase position of the input signals the clock pulses also fall two clock pulses in the buffer time. To suppress the second clock pulse another memory is required. In this way one achieves that the impulses of the individual channels have a minimum time interval from one another, so that the pulse series OR-linked can be added up in a counter without loss of information.

The disadvantage of the known devices is particularly in the case of more than two series of pulses to be summed the high cost of generating a number corresponding to the number of channels clock pulses phase-shifted from one another, as well as those from the asynchronous mode of operation of the known Facilities resulting susceptibility to failure.

The purpose of the invention is to avoid the disadvantages described. This is done according to the invention in that the pulse series are synchronized with only one clock pulse frequency regardless of the number of channels to be additively linked and that means are provided for delaying the switching back of a flip-flop that determines the duration of the synchronized pulses of a channel according to the number simultaneously in the respective Channel influencing channels formed synchronized pulses and means for Ver-circuit arrangement for synchronization of
Pulse trains with a clock pulse frequency at
simultaneous additive linking of the pulse trains of several channels

Applicant:

Philips Patent Administration G. m. B. H.,

Hamburg 1, Mönckebergstr. 7th

Named as inventor:

Dipl.-Ing. Gerhard Kaps, Hamburg-Lokstedt - -

Linking the output signals of all channels to control a synchronous technology Counter.

An optimal utilization of the arrangement is obtained when the series of pulses of the size of their Repetition frequencies are assigned to the individual channels in such a way that the first of all channels affected channel receives the pulse series with the lowest repetition frequency.

The invention is described with reference to the embodiments shown in the drawings. In it shows

F i g. 1 a summing synchronization stage with three stable multivibrators for two channels,

F i g. 2 a summing synchronization stage with bistable multivibrators for two channels,

F i g. 3 a block diagram of the summing synchronization levels for «channels,

F i g. 4 a summation stage for η channels with separate synchronization stages.

In Fig. 1 shows the logic diagram of a summing synchronization stage for two channels, in which three-stable multivibrators are used to synchronize the pulse series offered to the inputs ^ and E ₂ with the clock pulse frequency.

A synchronization stage known per se is provided in the second channel. The hibernation,

609 670/361

if there is no signal at the input, this is indicated by the L potential at the output C _{23 of} the switching stage T ₂₃ . The input signals are sent to the preparation input of switching stage T ₂₂ . Depending on the phase position between the start of an input signal and the clock pulses, the first or the second clock pulse that coincides with the input signal switches the tri-stable multivibrator. The resulting L potential at the output C ₂₂ prepares the AND gate G ₂ . After the input signal has disappeared, the inverter stage N ₂ and the AND gate G ₂ enable the next clock pulse to switch on the tri-stable multivibrator. The resulting L potential at output C ₂₁ is only retained for the period between two clock pulses; because via the preparation _{input of the switching stage T 23} it causes the three-stable flip-flop to switch back to the rest position with the next clock pulse .: The synchronized pulse of the second channel can be picked up _{at C 21.} The synchronization stage of the first channel differs from that described above in that an AND gate G _{81 is connected} upstream of _{the preparation input of the switching stage T 13.} The synchronized output pulses of the second channel can be effective via an inverter stage N _s2 and this AND gate at the preparation input of the switching stage T _{13 of} the first channel when the switching stage T ₁₁ shows low potential at its output C _11. This means that an output pulse of the second channel influences the timing of the synchronization in the first channel only if a pulse coincident with the pulse of the second channel _{occurs at output C 11 of the first channel.} Then it is effected that not the first with the;: L potential; at. C ₁₁ coincident clock pulse but only the clock pulse following the end of the output pulse of the second channel switches the three-stable multivibrator of the first channel to its rest position. At output C ₁₁ , and thus also at output A via the OR gate O ₀ , a pulse of twice the clock pulse period appears, which is processed by a counter working in synchronous technology like two separate pulses.

FIG. 2 shows the logic diagram of a summing stage in which synchronization stages made up of bistable multivibrators are used. The second channel will be considered first. As long as no signal is offered at the input JS ₂ , the outputs U ₂₁ and C _{22 of} the bistable flip-flops FF ₂₁ and FF _{22 are at} L potential. An input signal arrives at the preparation input S _{21 of} the bistable flip-flop FF ₂₁ . Depending on the phase position of the input signal to the clock pulses, the first or the second clock pulse coincident with the input signal switches the stage FF ₂₁ so that its output C ₂₁ receives L potential. Since the outputs of stage FF _{21 control} the preparation _{inputs of stage FF 22} , this always switches one clock pulse later than stage FF ₂₁ . After the end of the input signal, the two bistable multivibrators are switched back to their rest position one after the other by the clock pulse. By forming the coincidence O ₂₁ · C ₂₂ in the AND gate G ₂ , the synchronized output pulse of the second channel is obtained after the inadvertent loss of the input signal, which also appears at the output _{via the OR gate O 0.}

The synchronization stage of the first differs from that of the second channel through the AND gate G ₅₁ . The synchronized output pulses of the second channel at the preparation input S _{12 of} the bistable flip-flop FF _{12 can become} effective via an inverter stage N _S2 and this AND gate when the outputs C ₁₁ and C ₁₂ show low potential. This means that the switch back will only be activated if a synchronized pulse occurs in the first channel

ίο Stage FF ₁₂ delayed by the duration of the synchronized pulse of the second channel. At the output of the AND gate G ₁ and thus via the OR gate O ₀ at the output A , a pulse of twice the clock pulse period appears.

F i g. 3 shows a basic circuit for expanding the two arrangements described to η channels. Here, the synchronized output pulse of the n-th channel may be coincident with .Ausgangsimpulsen of channels 1 to -nfr 1 .. therefore must

ao the channels 1 to n-1 AND gates G ₅₁ to G _{5n-1 are} provided, the synchronization stage outputs a ₂ \> \% fl _n . of the channels. Jj.bis. «Inverted (N ₅₂ to A / 's ,,) and the output -a; / inverter stage N _sl with one input each, the AND gate G ₅₁ to G ^ _-1

be linked ^ The OR gate O ₀ . links the synchronization level outputs ^ to a _n and delivers at its output ^ the pulse sequence corresponding to the sum of the input pulse series.
The in Fig. 4 for channels differs from the previously described arrangement in that the pulse series offered at the inputs ^ to E _n are initially synchronized independently of one another with the clock pulse frequency and that: for channels 1 to n-1 separate bistable flip-flops FF ₁ to FF _{n-1 are} provided. These flip-flops determine the duration of the synchronized pulses of a. Channel depends on the number of coincident pulses, the channels that influence the respective · .channel. In the idle state, when there is no input signal, the outputs O ₁ to a _{n of} the synchronization stages SyI to Sy η O-potential, the outputs C ₁ to U _{n-1 of} the bistable. Flip-flops FF ₁ to FF _n _ _v and thus the outputs dec AND gate G _sl to G _sn . ₂ , L-potential

tial. The first channel will be considered. A synchronized pulse at the output U _{1 of} the synchronization stage SyI switches the bistable KiPpStUfCFF ₁ via a static input so that. its output _{receives C 1} L potential. The one with the synchronous

ized pulse coincident clock pulse switches the stage FF _{1 back} to its rest position, provided that the preparation _{input S 1 is} L-potential. The synchronized pulse appears practically unchanged at output C _1. The inverted pulses of the other channels can cancel the L potential at the preparation input S ₁ via the AND gate G ₅₁ and thus delay the switching back of stage FF _1. The inverted synchronized pulses are taken from channels 2 to n-1 at the outputs U ₂ to U _{n-1 of} the bistable flip-flops FF ₂ to FF _n-1 , in the last channel at the output of the inverter stage N.

No AND gate is required before the preparation input S _n _ _{t of} the bistable flip-flop FF _n ^ _1,

since this is only influenced by the last channel.

The OR gate O ₀ links the outputs C ₁ WsC _{n-1 of} the bistable multivibrator FF ₁ . to FF _n- j and

the outputs of the synchronization stage of the nth Canal. A counter operating in synchronous technology can be controlled from the output ^ of the OR gate will.

Claims (6)

5 claims: 1. Circuit arrangement for the synchronization of pulse trains with a clock pulse frequency Simultaneous additive linking of the pulse trains of several channels, characterized in that that the pulse series is independent of the number of channels to be additively linked be synchronized with only one clock pulse frequency and that means are provided to delay switching back one the duration of the synchronized pulses of a channel determining trigger level according to the number simultaneously in the influencing the respective channel Channels of formed synchronized pulses and means for linking the output signals all channels for controlling a counter working in synchronous technology. 2. Circuit arrangement according to claim 1, characterized in that the first, of all Channels influenced channel the pulse series with the lowest repetition frequency is fed. 3. Circuit arrangement according to claim 1 or 2, characterized in that the means to delay the switching back of the flip-flops that determine the pulse duration from the inverted ones Output signals of the channels influencing the respective channel controlled and the preparation inputs of the flip-flops are controlled by AND gates. 4. Circuit arrangement according to claim 1 or 2, characterized in that the means to link the output signals of all channels is an OR gate. 5. Circuit arrangement according to claim 1 to 3, characterized in that the duration of the synchronized output pulses of the channels determining flip-flops part of the used Synchronization levels are. 6. Circuit arrangement according to claim 1 to 3, characterized in that the duration of the synchronized output pulses of the channels determining flip-flops from separate synchronization stages controlled bistable multivibrators are. 1 sheet of drawings 609 670/361 10.65 © Bundesdruckerei Berlin