DE1222724B - Method and circuit arrangement for the automatic recognition of characters - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. Cl .:

G 06k

German KL: 43 a - 41/03

'" ^: \ 31. VS -2.2.

Number:

File number: S 93416IX c / 43 a

Filing date: September 29, 1964

Opening day: August 11, 1966

The operation of telecommunications systems and message processing systems brings often the task with itself, characters, ζ. Β. Letters or numbers on suitable recording media may be included, automatically 5 by means of a scanning device, for example a photoelectric scanning device to scan and then process. A processing of the Characters can be that the characters are identified in order to be dependent of these characters a control of subsequent telecommunications or message processing To enable facilities with the help of suitable signals. Often not just a single character or a To scan the text line and then to process it, but there will often be the task of To scan an entire text field or the like, so that one contained in it, arranged in cells Text can be read and processed.

Such a task can occur, for example, in connection with the reading of call counters in telecommunications technology and the like. It is well known that such counters have to be read at regular intervals. In order to speed up the regular reading of the counters, which are generally grouped together in counter fields, the procedure has already been followed (see, for example, GEC Telecommunications No. 30, July 1960, pp. 16 to 20) that each such a field of, for example, 100 call counters is photographed in order to at least reduce the time and personnel expenditure for the direct reading of the call counters. The digits contained in the photographic image of such a call counter field, which indicate the status of the individual call counters, can then be evaluated by automatic scanning and processing devices. For this purpose (preferably with an immovable original image and only continuous movements within a scanning device), an image original containing, for example, a text or the like consisting of several lines of writing can be carried out along certain scanning tracks, which essentially each have a line of writing or in the previously specified line Example may contain a number of call counter front panels, with the aid of a line scanner a column-by-column scanning of the original image along the scanning tracks is made possible. To recognize the characters, the procedure can expediently be such that in the course of the column processes and circuit arrangement for
machine recognition of characters

Applicant:

Siemens & Halske Aktiengesellschaft,

Berlin and Munich,

Munich 2, Witteisbacherplatz 2

Named as inventor:

Rolf Jurk,

Karl-Heinz Busch, Munich

When scanning the characters, suitable form elements are determined and stored in the correct position and that after determining the rear boundary of a character, the form elements of this character are evaluated for its recognition.

When the recording medium is scanned column-by-column, it is, so to speak, in columns divided by surface elements, and there is in each case a degree of brightness of the surface element concerned corresponding scanning signal element generated. Here it is only between two signal values distinguished: A scanning signal element referred to below as signal element 0 corresponds to the Non-impingement and a scanning signal element referred to below as signal element 1 dem Occurrence of the scanning point on a surface element, which in its degree of brightness is an element of a corresponds to the character to be processed. Is it how this z. B. with a machine reading of call counter photographs in the manner indicated above is the case to the scanning of machine-recognizable characters, which - if necessary, in groups from Z. B. four or five digits - in a section of the recording medium that contrasts with its surroundings are contained, for example in the counter window of a call counter front panel, thus not only become a character when the scanning point strikes belonging surface elements, but also when scanning the environment (front panel) of the Character containing section (counter window) scanning signal elements 1 are generated.

With the machine recognition of characters that are in such a way to its environment contrasting section of a recording

609 609/166

3 4

are contained in the carrier is now four times not to be given away. In the case of the counting device, it is possible to exclude the fact that a character at the boundary passes over to the respective at the moment of activation of the section directly in its vicinity of a further AND gate of the comparison device. This can be marked in the cited example of the counting steps achieved, and machine call counter evaluation can then be used in the new case, on the one hand, in the too wide tolerances of the supply of the projection signal elements in the case of Er-digit roles of the call counters and, on the other hand, in one such a marked counting step in the when taking a picture of the conversation counter on signal 1 at the one input of a fourth AND-occurring parallax error. Such a gate, the other input of which is connected to the direct transition of a character into the io output of the cut-out environment mentioned in the above second place, can, however, interfere with the recognition of the AND gate mentioned and affect the character in question, and sen output thus a reaching the rear may even falsify it. It is possible to limit a scanned character, namely the character itself, in addition to the form elements of the character end signal, which at the same time indicates their position, precisely because the 15 occurs. The counting device has in the known black line of this character direct circuit arrangement on an up counting register, bar merges into the black cutout environment, the input of which is formed with the input of the circulating register further form elements that are connected to it; it also has an intermediate combination with the actual form elements storage register, which can falsify or at least make difficult the recognition of the first-mentioned AND gate of the comparison by activating the relevant character. The facility marked. Counting steps of the invention described below is now based on the counting registers and, at the beginning of the next task, the automatic recognition of a scanning column is transferred to a counting down register to enable characters even if the character's control input with the output of the circulating character is in such an output register is connected and at the first stage cut is contained in such a way that it is connected to the one input of the AND gate mentioned in the foregoing second front limit of the cutout immediately place. passes into its surroundings. If necessary, the counting device also has a further intermediate storage register for defining the rear buffer register, which automatically limits the number of scanned by a scanning device by activating the third-key AND gate of the comparison mentioned above and named by a processing device Characters to be processed are stored by device marked counting steps of the forward comparison of corresponding signal counting registers and at the beginning of the next elements, which result from column-by-column scanning, scanning column in a further downward counting register of the characters, is transferred in the manner of its control input with the output of the drive that is connected by a comparison of the projection of the circulation register and at the first stage of the already scanned part of the scanning area the one input of the Pro representing with its other crossing to the scanning direction The detection output is connected to the output of the second AND gate and signal elements with the corresponding closed fourth AND gate. A very similar counting device will also be described in the following column in the sequence of from one another in connection with the corresponding projection signal elements and the description of the invention,
Furthermore, there is a circuit arrangement for detecting the occurrence of a number of signal averaging of the end of a machine-recognized element pair 10, each of which is known from 45 characters, in which the end of a signal is emitted from a projection signal element 1 and a scanning signal will, if the Absignalelement 0 exist since the beginning and the immediately between the keying of the relevant character or since seeing two pairs of signal elements 00 are, which consist of two such signal elements 0 at each point in time when a sufficient because of two such signal elements. Correlation between the character and a predefined number of scanning columns containing black sections via a counting device for counting the numbers in the pro-run or if there is no black ejection of the one that has already been scanned Part of the sample column containing the section is overflowed. The known circuit arrangement is able to provide the adjacent signal elements 1, 55 based on the invention described below, but does not solve the task at hand at the moment of activation, which, as already said, an AND gate of a comparison device is included exists, the machine recognition of a sufficient counting steps are marked, and the characters are also made possible if the characters in question in a section of signal elements each time when such a 60 is reached in a black environment in the manner in which the projection-related characters are fed in again contain a marked counting step a signal to one is that it emits an AND gate at the front boundary of the output input, the other section of which merges directly into its vicinity. The invention thus relates to a method for and which at its output thus a machine recognition of a section of a recorded character that contrasts with the reaching of the rear boundary of the scanned area and at the same time its position indicating, voltage carrier contained characters, whose Heli-for erasing the projection of this character in the degree of ligkeitsgrad that of the circumferential register referred to the surrounding register, usable delete signal 1 and which at the front boundary of the

5 6

To infer the cutout directly in its surroundings over the front boundary and thus can go, in particular from the counter reading such form elements, which only by a bump indicating digits of call counters for long-distance characters to the front boundary of the alarm systems. The method is formed according to the invention, the extract containing the characters dung characterized in that they become from the 5 and possibly in combination Column-by-column scanning of the recording medium with the characters themselves Scanning signal elements originating first in a form element contained in another font delay memory stored, whose characters can pretend before the actual Storage capacity to eliminate the storage of at least character recognition, so that the one of the maximum width of a character ent- ίο perfect recognition also such at the front speaking number of scanning columns resulting from excerpt boundary still abutting writing scanning signal elements allows the characters to be enabled at the same time.

The scanning columns overflowing the section are counted. An expedient and advantageous further development and that according to one of the requirements of the invention is that at the same time as that Character not covered surface elements of the 15 during the column-by-column scanning of the recording section made determination of the scanning signal elements received from the recess carrier overflowing first scanning column, which is stored behind next in the delay memory one at the front border of the cutout, the scanning signal elements 0 per characters originating from the scanning of white areas directly into the area surrounding the cutout runs, the delay memory for the 20 Weil to the line-individually stored sum Scanning signal elements of a scanning column which are added to those scanning signal elements 0, called the scanning column in one of the counting gaps from the scanning of the area in question Scanning columns overflowing the section create a series of in one and the other contained in the element Counting result corresponding distance same, running perpendicular to the column direction preceding, and the following scanning columns 25 lines to mutually adjacent white areas Passing on to the actual recognition device originate, and that after the determination of the device is unlocked. The first scanning column overflowing the cutout, the method according to the invention makes it possible to limit those behind a cutout at the front Form elements that are not directly in the characters in the area surrounding themselves are contained, but only runs through the 30 character, the delay initiation of the character to the front storage for the scanning signal elements of a scanning section delimitation are also formed, in front of the column, the said scanning column in one of the the further processing of the scanning signal elements for one and the same extending over the section the actual recognition device to be eliminated line stored maximum sum of kidneys. Thus, the distance corresponding to the 35 scanning signal elements 0 is impaired Recognition of the character in question, which precedes it, and the subsequent scanning columns Certain circumstances even lead to a false recognition for the passing on to the actual recognizer, thereby avoided that device is unlocked by a bump. Such a method of a digit at the front part of a conversation makes it possible to limit the limits with a high degree of certainty counter front panel or the like generated incorrect information 40 between characters, cut-out and cut-out in good time, d. H. before processing, discerning the environment and opening it up at the same time the will. It should be noted here that it is known the possibility of defining it in its implementation for the automatic recognition of crossed-out parts or circuit parts, as shown in this figure characters written one inside the other can still be seen using the following description a font scanning and evaluation arrangement in which 45 will be.

from the blackening points, form elements or the like. A first scanning mark overflowing the section each sign digital signal or column that matches behind one at the front cutout Characteristic groups are derived and, to a limited extent, directly in the area surrounding the area clear character recognition are checked and the passing character runs, the result is more expedient is evaluated in the way to proceed with the occurrence of at least one one ren that from the digital feature groups a measure of the width of a machine to be recognized Character a group of affirmative and a group of characters over-negative given minimum sum Characteristics by means of corresponding incremental sum of line-specific summing directions are derived and from these if th scanning signal elements 0 in the course of the for unambiguous character recognition no coincidence of the overflowing part of the first within indication is displayed, the affirmative group of characteristics of the excerpt does not overflow any characters it is checked whether it determines the fully affirmative sample column.

Feature group of one or more of the possible Particularly expedient and advantageous is that Contains characters, and that this correspondence, according to a further invention, the number of the first or matches at outputs for scanning gaps running through behind the character that you Streaked or interwritten characters mar- in one of the stored maximum sums of Abbreviated will or will be. This method has touch signal elements 0 in front of them at a corresponding distance no points of contact with the scanning column according to the invention and the intervening gaps in accordance with the path taken, in accordance with the scanning gaps comprising the scanning gaps at least Character not covered surface elements of the 65 by 1 smaller than those in the course of the first behind the Excerpt, as it were, from the scanning column running at the back of the characters of a character on which the time sum of scanning signal elements is 0. this has the front edge of the cutout has the advantage that at the same time such

7 8

signal elements 0 which may impair the character recognition, if necessary within predetermined ones

Incorrect information, which deviates from its limits, is determined by indicating signals

The reason for this is that the digitization and, if necessary, are stored in the correct position,

of the scanning signal an indeterminacy of the position of the. It is useful that before the comparison for

the front edge of the cutout is blackened by the lines extending over the cutout

zen surface elements by at least 1 bit in rows - their respective sum of scanning signal elements 0

direction is caused. is increased by at least 1; this enables

In order to clarify the security of the character recognition, in the above comparison between

heights and if possible such scanning signal see the position signals and the occurrence of a

. elements that do not reach or exceed the maximum sum from the scanning of a machine character to be recognized and its un- the sum of scanning signal elements 0 can be displayed Environment, not even from the signals in any case already directly at the To feed the detection device, the upper edge and / or the lower edge of one to the Moderately the delay memory depending on the front cut-out boundary adjoining writing from the fact that in said first scanning column 15 characters a disappearance of each of the Aufdie rear limitation of a front exit of such a sum of scanning signal element intersection limitation signal that is displayed directly in the sections 0 or the new occurrence of a Character passing through the environment determines such a signal within the relevant scanning

. is unlocked. column and thus the position of the written

; A further increase in the detection reliability 20 characters in the direction of the scanning columns also then

by early elimination of to detect correctly determine when the anterior. Limitation

of the character in question contributing nothing of the section obliquely to the direction of the scanning

. Sampling signal elements can thereby be reached, split or if of an indeterminacy

that the delay memory is only used for the position of the front section boundary.

. within the black surface elements given by the character position by more than 1 bit

Limits occurring scanning signal elements which must be assumed in the line direction.

Question coming scanning columns is unlocked. The invention is closer to the drawings

according to a further invention, the achievement of the can be explained.

. rear limit of one at the front exit F i g. 1 first clarifies the length of the scanning

.cut delimitation directly into the cutout 30 columns ... h-1, ... k + 3 ... carried out column area passing characters with the ten-by-ten scanning of a character, namely the appearance of a surface element of at least one digit 9, which in a to its surroundings Γ from the front edge of the cutout to a contrasting cutout F of a recording according to the width of a character presenter and at the front given minimum length of z. B. 15 bits exceeding 35 border of the section F is directly adjacent to its tendency not covered by the characters. Line segment and characters 9 consisting of the area surrounding the area T and surface elements correspond to one another in terms of their brightness only to a degree in accordance with the level of a degree of flexibility. The cut-out environment T and the cut-out F , which adheres to predetermined limits, can, for example, by a Ge-spacing therefrom surface element occurring at least 40 speech counter front panel and the provided therein at least one further such line section counter window or by a photograph of the same in the course of the first within the cut-out be formed; the in F i g. The digit 9 shown in 1 would not represent a scanning column overflowing a character and then the first digit of the digits indicating the current, if applicable, the occurrence of the upper or counter reading,
lower section border in place of one of the 45 the inFig. The number 9 shown in FIG. 1 abuts, as stated, the surface elements mentioned and immediately adjoins the front boundary of the Ausdie position of the character with the position of the intersection. The line line that is normally open to the left at a number 9 in the mentioned surface elements or between their lower part see the one such surface element and is therefore the area of the cutout area forming the front cutout boundary that forms the front cutout area Sampling column can be determined. keitsgrad corresponds to that of the number, closed-In a further embodiment of the invention can after sen. With the column-by-column scanning, the position of the section is determined in its therefore conditions that are at least very similar to the first scanning column that is behind one at the similar to those conditions that are immediately included in the scanning of a section when delimiting the section characters that do not go over to the boundary of the cutout area would find the abutting digit 8. In both overflowing parts the reaching of the rear case is in fact two interconnected, boundaries of a character and at the same time its superimposed, completely enclosed white layer in the direction of the scanning gaps by a surface, which, on the other hand, indicates the same between the cut-out position on all sides 60 free number 9 would not be the case. Under the

Xage signals. and the synchronous to this within a in Fi g. 1 could therefore

Sampling column, the occurrence of such a column when the digit 9 is sampled into a column

Sum of line-individually summed up scanning signal false detection, namely in that the detection

elements 0, which determines a form elements according to the width of an identification device, as they do

Character specified minimum sum of z. B. 65 can only be expected with a digit 8, and

Exceeds 15 bits and, at the same time, the scanned character also as

number of the scanning digit 8 overflowing the character evaluates. By touching number 9

. split corresponding maximum sum of scanning the front boundary of the section F will be

9 10

So in addition to the counting input α of the adder Add which is otherwise contained in the number 9, the form elements generate incorrect information, which can lead to a false detection from the scanning of a black surface element, if one mentes the scanning signal element 1, so no special measures are taken . This causes the deletion of the memory space of the method according to the invention that was previously associated with the incorrect identification, but is prevented by the specified 5 relevant line. ZS stored sum of scanning signal

A circuit arrangement for implementing the element 0, which is shown in FIG. 2 by a method according to the invention, is shown in FIG. 2 shown negator NR to reset input r of the addition value. The circuit arrangement shown in Fig. 2 kes Add leading connection is indicated. initially has a memory ZS for storing the io at the individual memory locations Zl S .. .ZZS in the column-wise scanning of the recording of the memory ZS, which are each assigned to a transverse to the Abträger resulting sums of such scanning scanning columns Signal elements 0 that result from the scanning of in each case only a sum of such scanning signals one and the same, perpendicular to the column direction ver elements 0, which originate from the scanning of a current line, adjacent white 15 from the scanning column just reached over-surface elements . For this purpose, the memory ZS encompassing the row of lying in the relevant line expediently contains an area element corresponding to the length of the directly adjoining white area scanning column (for example h in FIG. 1).

number of one line each (e.g. m in Fig. 1) trains- With the output of the adder A dd is further arranged storage locations ZlS ... ZmS ... ZZS. ao towards the input input of a memory register. These memory locations Z1 S ... ZZS are connected via a WM ; to the laying output of this. Memory distribution device, which is in the circuit arrangement register WM , the one input of one with its according to FIG. 2 other by the two distribution circuits input is also formed at the output of the ad-Vl and V2, in turn, namely exploding work Add connected comparator Cf. synchronously connected to scan within each exhaust 25th As explained in more detail below, value branch column, connected to an adding unit Add . is is in the storage register WM during such a distribution circuit. V1, V2 can, in this case, each white section (eg k, m; ...; k, p-1; in without this being shown in more detail in FIG. 2, in FIG. 1) a scanning column (k In Fig. 1) the maximum mode of play is stored by a row of a respective stored sum of scanning signal elements 0, the gates assigned to cherplatz (ZmS) being formed, 30 for one of the gates extending over the white section which extend synchronously with the scanning within each of the lines the comparator are held capable (m ... p-l in Fig. 1) sequentially pulsed transmission at the output of adder Add scan column has occurred, for which the control inputs of each See compares the output of the Addiergenannten gate at each stage of a work Add pending sum of scanning signal shift registers of the length of a scanning column elements 0 with which can be closed in the storage register WM to the sum stored over a point in time relating to a line; occurs at tang T the clock pulses, which in a known adder output a larger signal than the respectively stored in the way the scanning memory register WM generated by the scanning device in a finite number of scanning signal sum of scanning signal elements 0, so the elements subdivide , supplied as shift pulses 40 output line gr of the comparator Vgl an evaluating, input signal 1, while if the co-input

The adder Add adds the sampling signal elements 0 occurring in the course of another compared sums to the sampling column (z. B. k in FIG. 1) on the line η of the further output line gl of the comparator Vgl to whichever occurs. Gr to the output line of the Signaleinan the memory location (Z 15. .ZZS) 45 passage of a locking gate GOgr connected to the Abtastsignalelemente and in the presence deletes one Abtastsignalelemen- carrying line η is that with the stored sum of Abtastsignalelementen 6 an inhibit input. A second input with the Sperrtes 1 gespei- on the associated space said inhibit gate is connected to a line sgf cherten sums of Abtastsignalelementen 0. made after determining the first

If one puts the in F i g. If the relationships shown in FIG. 1 are 5 ° within the excerpt / * ¹ no characters overlap, for example, with the occurrence of a running scanning column (k in FIG. 1), a blocking signal of that scanning signal element 0 which leads from the discharge is generated. On the output side, the blocking gate GOgr controls the scanning of the determined by the coordinates (k, m) via a control line g the storage of a pending on the white surface element, this scanning output of the adder Add pending size signal element 0 in the circuit arrangement after 55 ren sum of scanning signal elements 0 in the Spei-F ig. 2 by the adder Λ cta to the sum cherregister WM.

of scanning signal elements 0 added, from which a further blocking gate Gl is with its signal

Scanning of the surface elements (h, m), (h + 1, m) ... input to the (k-1, m) leading to the scanning signal elements, so far from that of the line m line and with a blocking input to the allocated memory location ZmS of the memory ZS 60 connected line sgf , which is stored according to determination and which is currently being fed to the adder Add via the distribution of the first within the section F no circuit V1; Characters overflowing scanning column a blocking leads the new sum of signal 1 formed in the adder Add; As FIG. 2 shows, the above-mentioned scanning signal elements 0 can then have an additional blocking circuit V 2 again at the input of the line m via the distribution gate Gl, the memory location ZmS of the memory ZS connected to a line gf as sen, which already with the determination of the first new internal sum of scanning signal elements 0 fed into the section F does not overlook any characters. If, on the other hand, line n occurs, with which the fenden scanning column carries a blocking signal 1. The end-

11 12

On the output side, the further blocking gate Gl controls via the first sampling column (Ic in FIG. 1), the one behind

a control line m the deletion of one in the memory one at the front border of the

register WM while at the same time going over indirectly to the area of the cutout

ger resetting of the memory register WM. Character runs through which in the memory register WM

The above-mentioned line gf, the maximum sum stored with Er- 5 is preset and no blocking script is switched on during each scanning column by one counting character. Which carries the full counting signal 1, forms an output line of a device FY which emits speaking signals corresponding to a volume of, for example, 26 bits; The output of the counter Zxza is connected to a 1-bit storage line called sgf, on which XZ is more likely to be connected after determination, on whose output line xz the first scanning column within the section does not overflow the control input of an unlocking gate Gnx an characters closed is; this unlocking gate Gnx is blocking signal 1 occurs, represents a further output to the above-mentioned delay memory RR following this device FY . In F i g. 2 is connected, which is indicated in the circuit arrangement according to that the line gf to the output of a 15 F i g. 2 between the line n, which can be connected to the coincidence gate GF , for (in FIG. 2 not shown) scanning device - .which with the detection of the first within the possibly overflowing smoothing section no characters overflows - emitted Abtastsignalelemente tastspalte the coincidence condition is fulfilled and leads, and to the (also not g in F i 2 Dardas the control input of a 1-bit memory SGF Toggle 20 provided.) recognition means line leading geschlössen, by the first is inserted on the gf nx-nxy line.

Occurring signal Ϊ is activated and its output The circuit part of the arrangement line described so far forms the said line sgf . . Further drying of Figure 2 operates thus to zuEinzelheiten again sammenzufassen on the circuit design, in the following manner: The out of such a device FY be column-wise on hand 25 downward scanning a record carrier of the F i g. 6 are described in more detail; Here it is sufficient to first know from the scanning occurring on the line η that this device FY of signal elements are initially stored in the delayed output lines gf and sgf with or after the rungs memory RR . Simultaneously with this determination of the first within the section F, the scanning column Si 30 elements originating from the scanning of white areas are able to emit scanning signal elements 0 and 1, so that from this time to the line-individually stored sum point to the two blocking gates GO gr and Gl ge of those scanning signal elements 0 that are kept locked out are added. the scanning of the surface element in question

The two blocking gates GO gr and Gl control, as already mentioned in one and the same row, the storage of a larger sum of elements coming from the adder row adjacent to one another. At the beginning of each scanning signal elements 0 in the memory register WM white section of a scanning column, the memory or the deletion of a sum register stored therein is initially reset, namely preferential and resetting of the memory register WM, and according to the minimum width so that Minimum sum specified in the memory register WM up to the first 40 of a character within the section F, no character of, for example, 15 bits; During each white overflow scanning column during each white section of a scanning column, the sums obtained for one of the line sections extending over the line-specific addition of scanning signals at element 0 with the maximum sum of Ab- 45 occurring in the memory adder output are then used WM saved sum compared, and key signal elements 0 is stored. The storage it is appropriate, the larger sum in the register WM now comprises another shift register output memory WM stored, so that in the on wm; At this shift output wm , according to the storage register WM, during each white section the determination of a first of a scanning column overflowing the section can be used to directly convert the section limit for one of the lines extending over the scanning column behind a front 5 ° white section into the section maximum sum of Scanning signal elements 0 runs surrounding lines, one of which is stored in the. After determining a sum just stored in the section F memory register WM (see FIG. 1) overflowing the first scanning column (Ic in number of scanning signal elements 0 corresponding to FIG. 1), which are picked up after one at the front Ausvon control pulses. This 55-sectional boundary in the cutout control pulses arrive directly in the circuit configuration surrounding passes over continuous characters, is then shown in Fig. 2 via the one input of an OR under the influence of the two gate Gwm and Gsp gate OGzx to the counting input of a counter, the counter Zxza by the in the memory register WM Zxza; Maximum OGzx stored via the other input of the OR gate at the relevant point in time is then preset at the beginning of each total and then a counting pulse is sent to the counting input of the further scanning column by one increment counter Zxza during each scanning column. The described control of the counter-switched; after reaching the last counting step lers Zxza, the one of the number of a character is then activated via the 1-bit memory XZ the unlocking maximum width corresponding counting volume of lungsgatter Gnx , so that the delay z. B. 26 bits, the 65 memory RR is unlocked by two.

OR gate OGzx upstream gates Gwm and thus the presetting of the counter Zxza and

Gsp influenced in such a way that the counter Zxza after Er- the subsequent full counting of the counter only after

averaging a section F (see FIG. 1) overflow- Determination of a first overflowing section

Scanning column is going on, which runs behind a character that merges directly into the area surrounding the front cutout boundary, is shown in the circuit arrangement according to FIG. 2 connected to the locking gate GO gr the control input and to the locking gate Gl the reset input of a 1-bit memory SOgr , the output of which leads to one input of an AND gate GIa , which with its second input to the already mentioned line sgf and with its third input is connected to a signal element 1 leading line Sp in each case at the beginning of a scanning column. The coincidence condition is for this AND gate GIa only be fulfilled if in the course of the cutout F overflowing part (k, m; ..;. K, p 1 in Fig. 1) of the first overflow no characters within the cutout F Scanning column (k in Fig. 1) in the line-individual addition of scanning signal elements 0 at least once a sum of scanning signal elements 0 has occurred which exceeds the specified minimum sum of, for example, 15 bits, to which the storage register WM at the beginning of the relevant white section (k, m ;. ..; k, p— 1) has been postponed. The output signal emitted by the AND gate GIa in the case of coincidence thus indicates that the first scanning column, which does not overflow any character within the section F, runs behind a character that merges directly into the section surroundings at the front section boundary.

This determination is first stored in the memory LA connected downstream of the AND gate GIa. In order to carry out the presetting and the full counting of the counter Zxza and a resulting unlocking of the delay memory RR in dependence on the fact that it is determined in the said first scanning column that the rear boundary of a character passing directly into the cutout area at the front cutout boundary has actually been reached, one input of an AND gate Glaz is directly connected to the output of the memory LA , the other input of which is connected to a line gz carrying a signal 1 after the rear boundary of a character has been determined. The line gz forms the output line of a corresponding device ZY. In Fig. 2 indicates that the line gz can be connected to the output of a coincidence gate GZ for which the coincidence condition is met when the rear boundary of a character is determined. Further details about the circuit structure of such a device ZY are given below with reference to FIGS. 3 will be described in more detail; Here it is sufficient to first know that a signal element 1 appears on line gz with the determination of the rear boundary of a character.

The AND gate Glaz leads via a buffer LAZ2 and a downstream AND gate G 23, which can be transmitted at the beginning of a scanning column, _{to a further memory LAZT) 1,} the output of which is via a gate G 34 with the reset input, which is also only transferable at the beginning of a scanning column this further memory LAZ 3 is connected. In addition, the output of this further memory LAZ 3 leads to the signal input of the gate Gwm inserted between the shift output wm of the memory register WM and the one input of the OR gate OGzx and to the blocking input of the gate Gsp, the upstream of the other input of the OR gate OGzx with its control input on which a signal element 1 leading line Sp is in each case at the beginning of a scanning column. The mentioned AND gate Glaz also connects the output of the memory LA with the control input of a with its reset

ίο input to the output of the counter Zxza connected additional memory LAZl, to whose output an unlocking input of the gate Gsp and one input of an AND gate Gxza is connected, which with its other input can be connected directly after the output of the counter Zxza corresponding to the full counting volume can.

After the above in FIG. The circuit arrangement shown in FIG. 2 for carrying out the method according to the invention has essentially been explained in terms of its circuit structure and also in individual functional features, the mode of operation of the circuit arrangement will be discussed again in summary based on the relationships shown in FIG. Before that, however, a look at FIG. 5 are thrown, from which further details emerge about how the memory ZS, the adder ^, the comparator Vgl and the memory register WM can be constructed in terms of circuitry.

According to FIG. 5, each memory location ZmS of the memory ZS can be formed by a number of binary memory elements 2 ° ... 2 ⁴ , which is synchronously connected to the scanning within the scanning columns repeatedly in pulses with the adder Add in such a way that each memory element, e.g. B. the memory ^{element 2 3} , with its memory output connected to one input of an AND gate UG and an EXCLUSIVE-OR gate EG of the associated adder (A 2 ^s ), the other input of which is connected to the carry line leading from the preceding adder ü or the counting input α of the adder Add is connected and of which the AND gate UG to the transfer output ü of the adder and the EXKLU-SIV OR gate EG to the input of the relevant memory ^{element (2 3} ) of each with the adder Add connected space ZmS leads. To the counting input a of the adder Add an inverter NR may be connected, whose output is connected downstream to the blocking inputs of the EXCLUSIVE-SIV-OR gates EC locking gates SG and reset inputs of each connected to the addition unit Add memory elements 2 ° ... 2 ⁴ leads .

The comparator Vgl can each be formed from an adder stage of the adder Add and a storage element 2 ° ... 2 ^{4 of} the storage register WM associated stages, in each of which one connected with its blocking input to the relevant storage element and with its other input to the relevant adder stage Lock gate VSG and a downstream AND gate VUG, the other inputs of which are connected to the lock gates of all subsequent comparator stages, are provided, the said AND gates VUG each to an input of all

lead in equal stages common OR gate VOG , the output line gr of which forms the output line carrying a signal 1 when a sum greater than the sum stored in each case in the memory register WM occurs at the adder output. In addition, each comparator may comprise an input side, in turn, connected to the adder Add and the storage register WM equivalence gate VAG, said equivalence gate VAG are combined by an AND gate VCG, the output line GL, respectively in the event the same sums in the storage register WM and on a signal 1 Addierwerksausgang leads.

The storage register WM can be formed, each g a (in the circuit of F i by a series of binary memory elements 2 ° ... 2 ^4. 2, the adder Add is connected to the output of the associated adder and from the inhibit gate GO gr via a control line g-controlled) Einspeichereingang, one (in the circuit of FIG. 2 and comprises by the further inhibit gate Gl via a further control line m-controlled) 'reset input a connected to the output of the respective adjacent memory element shift input which s is controlled via a control line, in that if after detection of a the cut-F overflowing first scan column Qc in F i g. 1), which runs behind a character that merges directly into the area surrounding the cutout at the front edge of the cutout, one of the number of storage elements 2 °. .. 2 ⁴ corresponding number of shift pulses with a series of intervening pulse pauses of the series of valences2o, 2.1, 2 ³ , 2 ^{4 of} the individual storage elements of the corresponding duration occurs. A corresponding pulse pattern for a five-stage storage register is shown in FIG.

If such a pulse pattern corresponds to that shown in FIG. Storage register WM shown in Figure 5 is supplied via the control line s, so effected, starting from a specific setting of the memory register, the first pulse of the adjoining, one clock interval lasting pulse interval that the shift output wm leading issue stage S for the duration of a clock interval, one of the setting the memory element 2 <> assumes a corresponding setting; the second pulse with the subsequent pulse pause lasting two clock intervals causes the output stage S to then assume a setting corresponding to the setting of the memory element V for the duration of two clock steps; the third pulse with the subsequent, four clock intervals lasting pulse pause then causes the output stage S for the duration of four clock intervals to take a setting ^{corresponding to the setting of the memory element 2 2} , etc. According to this principle, which incidentally about the application in the invention Circuit arrangement is also of independent importance, a counting pulse is then transmitted to the counter Zxza via the gate Gwm (see FIG. 2) for each of the mentioned clock intervals, so that the counter can be preset according to the setting of the memory register WM. A pulse pattern as shown in FIG. 7 is expediently generated by means of a circular memory in which such a pattern is permanently written from the start and which outputs this pattern repeatedly at the beginning of each scanning column. Such a pulse generator is denoted by JG in FIG. 2.

The unlocking input, designed as a blocking input, of the gate Gwm connected downstream of the shift output wm of the memory register WM can then be connected to the control line s, on which the shift pulses occur with a series of intermittent pulse pauses, as is also shown in FIG. 2 is indicated.

In the following, the implementation of the method according to the invention by means of the method shown in FIG. 2, based on the circuit arrangement shown in FIG. 1 are explained. Let the recording medium T shown in FIG. 1 with the section F containing the character 9 along the lines shown in FIG. 1 indicated sampling columns . ..h - l, .. , k + 3 ... are scanned; the scanning signal elements resulting from the scanning may appear on the line η . It is assumed that the scanning initially extends over the left part of the recording medium T in which the scanning gaps have not yet passed over the section F. After according to FIG. 1 the recording medium T corresponds in its degree of brightness to that of the characters to be recognized, during this scanning, at least in the area of the individual scanning columns of interest here, initially only scanning signal elements 1 are generated, which then appear on the line η . These scanning signal elements 1 have the effect, via the blocking gate Gl and the control line m, that the storage register WM is set to a minimum sum of, for example, 15 bits, which is predetermined according to the width of a character; at the same time, the 1-bit memory 50 gr goes into the idle state. These relationships initially last until the end of the period shown in FIG. 1 indicated sampling column h - l .

Among the in F i g. 1, the following scanning column overflows, h for the first time the section F. Scanning signal elements 0 resulting from the scanning of white surface elements now also appear on line η . Such a scanning signal element 0 is generated, for example, when scanning the surface element Qi, m) or the surface element (h, p − l) . The same applies to the following scanning columns h + 1, ... k -1.

The resulting from the scanning of white surface elements, z. B. of the surface element Qc - 1, m) are added by the adder Add each line- individually stored sum of those scanning signal elements 0 in the memory ZS , which from the scanning of the surface element in question, for example the surface element Qc - l, m ) co-contained series of white surface elements adjacent to one another in one and the same line Qn); in the example, these are the surface elements Qi, m), Qi + I ₅ . m), ... Qc- 1, m). Simultaneously with this, ₅ that-the unallocated space DMF memory ZS is stored sum of Abtastsignalelementen 0 at which the relevant row m newly formed in each case, the sum by the comparator Cf. with the just been stored in the memory register WM sum is compared and if it is above

step this sum is written in its place in the memory register WM . This is brought about by the locking gate GO gr , which controls the storage input of the memory register WM via the control line g. In this case, however, the storage register WM is reset with the aid of the blocking gate Gl leading to the control line m whenever a scanning signal element 1 occurs on the line η. Among the in F i g. 1, this is the case in each case when the scanning point in the course of the scanning columns h ... k-l has reached the level of the line ρ . This ensures that during each white section of a scanning column, only the maximum sum of scanning signal elements 0 occurring for one of the lines extending over this white section is stored in the storage register WM.

Therefore, if in the course of the following scanning column k the scanning extends straight over the section F , then at the moment in which the scanning signal element 0 resulting from the scanning of the white surface element (k, p-1) has appeared on the line η and has been processed by the adder Add, in the memory register WM just in the course of the scan column k for one of the protracted via the cutout F line m ... p- be stored 1 resulting maximum sum of Abtastsignalelementen 0, which at the basis of the in F i G. 1 has exceeded the predetermined minimum sum of, for example, 15 bits with the previous resetting of the memory register WM.

The scanning column k is now the first scanning column which does not overflow any character within the section F. This result is at the end of the white section (k, m) given by the section F. . . (k, p- 1) of the scanning column k , so that at the moment when the scanning signal element 1 resulting from the scanning of the black surface element (k, p) appears on the line π, the determination of the the first signal element 1 indicating no character overflowing within the section F occurs. The occurrence of this signal initially has the consequence that with the occurrence of the above-mentioned scanning signal element 1 for the blocking gate Gl, the coincidence condition is no longer met, so that the resetting of the memory register WM , which is otherwise effected via the line m , is omitted; at the same time, the 1-bit memory SOgr also remains in the 1 state into which it was brought by the blocking gate GO gr at the beginning of the white section by the scanning signal element 0 resulting from its first white surface element {k, m). The signal element 1 appearing on line gf simultaneously activates the in FIG. 2 indicated 1-bit memory SGF of the device FY, so that from now on the 1-state prevails on the line jgf.

So that now the same time on the line sgf the 1-state is achieved and the 1-bit Speicher.SOgr is activated, indicating that (k, m) in the course of the cutout F overflowing part ... (k, p - 1) the first scanning column k, which does not overflow any characters within the section F, has at least one sum of scanning signal elements 0 summed up individually in line with the minimum amount of, for example, 15 bits specified in accordance with the minimum width of a character to be recognized by machine; Thus, a first scanning column k overflowing the section F, which runs behind a character that merges directly into the section surroundings T at the front section boundary, is determined. At the beginning of the next sampling column k +1, the coincidence condition is therefore fulfilled for the AND gate GIa; by the output signal delivered by the AND gate GIa, the memory

ίο LA activated.

As a function of this alone, the unlocking of the delay memory RR, in which at least the scanning signal elements resulting from the scanning of the scanning columns h-1... K are currently contained, could already be effected. Expediently, however, the delay memory RR can also be unlocked as a function of the fact that in the first scanning column k which does not overflow any characters within the section F, the rear boundary of a character (which merges directly into the area surrounding the section at the front section boundary) is determined. Such a dependency of the unlocking of the delay memory RR on a determination of the rear boundary of a character passing directly into the cutout area at the front boundary has the advantage that the scanning signal elements currently contained in the delay memory RR are only passed on to the actual recognition device, if it is actually a question of scanning signal elements that result from the scanning of a machine-recognizable character and its immediate surroundings, as is the case with the in FIG. 1 is actually the case. On the other hand, if, in deviation from the relationships shown in FIG. 1, for example, instead of the number 9, a black bar or the like that emanates from the left section environment T and protrudes to the right into section F would have been scanned, which is not considered to be automatically closed recognizing characters were to be evaluated, the delay memory RR would not be unlocked for the scanning columns overflowing this bar. This is shown in the arrangement according to FIG. 2 achieved with the aid of the AND gate Glaz connected downstream of the memory LA ; This gate is only transferable for the output signal emitted by the activated memory LA when a signal element 1 indicating the determination of the rear boundary of a character appears on the line gz. This condition can under the conditions shown in FIG. 1 must be fulfilled in the course of the scanning column k - \ - 1; the output signal emitted by the AND gate Glaz activates the two memories LAZ1 and LAZ 2. After the memory LAZ 2 has been activated, the coincidence condition for the gate G 23 is fulfilled at the beginning of the next sampling column k +2, so that at the beginning of this Sampling column k + 2 the subsequent memory LAZ 3 is activated. At the same time, the memory LAZ 2 is reset, as is the memory LA via the gate GrIa. The activation of the memory LAZ 3 effected at the beginning of the scanning column k + 2 initially has the consequence that the counter Zxza is reliably controlled via a differentiating element D emitting an output signal in the event of a 0-1 signal transfer and an OR gate OGr

609 609/166

19 20

is returned to the idle state. At the same time, at places not covered by the characters, the two key signal elements 1 are generated at the beginning of the scanning column k + 2 , before then being unlocked in gates Gs and Gwm, so that ■ - below that of the next column (Zz + 1 in FIG. 1) the non-effect of areas covered by the characters within the impulses according to FIG. 7 - only scanning signal elements 0 earth of the OR gate OGzx one that is currently being generated via the upper input s section F. This occurrence, which cannot be avoided even with the maximum sum stored exactly parallel to the cherregister WM, resulting in a segment limit running scanning columns , has its cause Zxza, which causes the counter to be preset by the scanning during digitization. The scanning signal supplied to the other input of the io device from a blocking gate Gsp only leading to an OR gate OGzx is blocked about halfway blackened with the meanwhile from the memory LyIZ 3, about the same probability a scanning signal-

With the beginning of the next following scanning column k + 3 element 0 or a scanning signal element 1, the memory LyIZ 3 is derived again via the gate G 34. If one considers in this respect the reset to the idle state, so that now the 15 Fig. 1, so can for example be locked within the AbGatter Gwm and the gate Gsp unlocked scanning column h when scanning the lower half of the. Via this gate, at the beginning of this section F, contrary to the above-described scanning column & + 3 and every further scanning column, there is also a counting pulse to character-covered parts of the section F scanning the counting input of the counter Zxza that are not covered by the writing from the line Sp , so that the 20 signal elements 1 are generated. This could lead to the counter being incremented by one counting step in each case, so that in the scanning column h is between upper. As soon as the counter Zxza is the full and lower cutout limit and from the counting volume of z. B. 26 bits corresponding counter characters not covered, but has reached the advance, is prepared on the following generation of scanning signal AND gate Gxza, which is evaluated by the memory LAZl for 25 elements 1 as black surface elements, the coincidence case , the 1-bit memory area elements activated the scanned number 9 in their XZ , which closes on the control input of the lower left part. This would result in the output line leading through the unlocking gate Gnx, the combination of the surface elements mentioned with xz, the actuation of the unlocking gate Gnx and the lines of the font being scanned, so that the unlocking of the delay memory RR 30 would result in the characters in the form elements of the font. The delay memory RR will characterize the information contained in addition so that false information is generated for the scanning signal elements of a scanning, columns which lead directly to the pretense of a digit 8 after the one at the front in the case under consideration, for example to delimit the section and the characters passing over the cutting environment could run with a false detection of the actually scanned scanning column k (in FIG. 1) preceded by a distance number 9 or at least a hindrance to it, which would cause the maximum sum of scanning signal detection. Such Fehlinforelementen 0 corresponds to m the protracted for which are on the mation modes now cut by a special F lines ... p l ermit- fication elimitelt of the inventive method and stored in the memory register World Cup, nes 40 before unlocked at all for the detection of the straight and the following scanning columns. scanned characters can be evaluated

It has already been noted that the check-NEN, namely by following the count of the payout of the scanning columns which cut the first behind the newspaper F h overflowing scanning columns ... k k and Chen extending scanning gaps, said her in the prior determination of the scanning gaps overflowing the gaps as well as the first scanning gaps k between them, which includes the scanning gaps behind one of the scanning gaps, based on the distance corresponding to the spacing of the area F trofsignalelements 0 not covered by the stored maximum sum of scanning at least one front section boundary is at least 1 smaller than the characters passing over in the course of the first section environment T behind the character scanning column lc runs 50, the delay memory RR for the scan-stored maximum sum of scanning signal element signal elements of a scanning column, the one mentioned th 0. The special significance of such a measurement column k in one of the counting results obtained would be given in the following: the corresponding distance precedes, and the

First of all, the following scanning columns can be unlocked in such a way that scanning of the recording medium in deviation from 55 that the earliest scanning signal elements of the second den

the relationships shown in Fig. 1 multiple section F overflowing scanning column h + 1 to the

it is not expected that the actual front recognition device will be passed on

border of the section F just between two.

Sampling columns (ft-1 and h in FIG. 1) and this can be done in the circuit arrangement according to FIG. 2 can therefore be achieved within the one column between the upper 60 expediently in that and the lower section delimitation only sampling with a delay memory RR, the sampling signal elements 1 and in the next sampling column with signal elements of a number of, for example, the places not covered by the characters only 27 Able to store scanning columns that the maxi-scanning signal elements 0 are generated. Beyond the character width of, for example, 24 bits by which, however, there is also, regardless of this, a number of probability, which cannot be neglected from reaching the rear limit, of placing a character in a column (A in Fig. 1) up to the completion of the Vordaß. between the setting of the counter Zxza , the elapsing sampling of the upper and lower cut-out limits split k ... k + 2 exceeds the counting volume

of the counter Zxza with, for example, 27 bits is at least 1 bit larger than the maximum possible sum to be stored in the memory register WM of, for example, 25 bits, taking into account a column-synchronized reaching of the full counting volume, in the case of a character passing directly into the cutout area T at the front edge of the cutout . If, in addition, a possible inclined position of the section delimitation is to be taken into account, the scanning signal elements thereof are expediently passed on to the detection device only from a correspondingly later scanning column extending over the section F. It should be noted at this point that in the circuit arrangement according to FIG. 2 in the desired sense, the fact that after the detection of the first scanning column k overflowing no characters, a larger sum of scanning signal elements 0 was no longer transferred to the storage register WM and therefore only the counter Zxza at the beginning of scanning column k + 2 0 was preset by the maximum sum of scanning signal elements reached in the course of the scanning column k.

At this point, it should be noted that the measure according to the invention, initially storing the scanning signal elements obtained when scanning a recording medium column by column, in a delay memory, the storage capacity of which allows the scanning signal elements resulting from at least one number of scanning columns corresponding to the maximum width of a character to be stored simultaneously to count the scanning columns overflowing the section and, according to a determination made according to the surface elements of the section not covered by the characters, of the first scanning column overflowing the section, which runs over a character at the front section boundary directly into the section environment, the delay memory for the sampling signal elements of a sampling column , which corresponds to said scanning column in a counting result obtained when counting the scanning columns overflowing the section computing distance precedes, and unlocking the subsequent scanning columns for transmission to the actual recognition device, has the particular advantage that only a single continuous column-by-column scanning of the recording medium along one row of the Sections overlapping scanning track needs to be made. This applies even if a scanned section F (in FIG. 1) with a digit adjoining its front boundary is preceded by another section, at the rear boundary of which a digit adjoins, and whose rear boundary can therefore not be easily ascertained. Furthermore, in the currently scanned section F (in Fig. 1), a digit adjoining the left section boundary can be followed by a further, free-standing digit or at all only such a digit not adjoining the left section boundary.

In order to take such a case into account, the circuit arrangement according to the invention according to FIG. 2, the AND gate Gxza led to the control input of the 1-bit memory XZ extending connecting via the one input of an OR gate OGxz, from the output thereof to the other: - Input A at the beginning of a scan column transfer enabled AND gate Gxfz leads. , which is connected downstream of the output of a memory LFZ; A gate Glfz leads to the control input of this memory LFZ.

Later delimitation of a character which does not immediately merge into the area surrounding T at the front boundary, the coincidence condition is fulfilled. For this purpose, the said gate Glfz is connected to the line gz and to the output of the memory LA which carries a 1 signal in the idle state. From the AND gate Gxfz , after determining the rear boundary of such a character that does not immediately merge at the front section boundary, the 1-bit memory XZ is activated immediately at the beginning of the next scanning column and the delay memory RR is thus unlocked.

A line ee leads to the reset input of the 1-bit memory XZ , on which a reset signal occurs in a manner not of further interest here after the recognition of the relevant character has been completed, so that the output of the delay memory RR is then locked again until one In the manner described above, after the rear boundary of a further character has been determined, the delay memory RR is again unlocked.

It should also be noted here that the inventive Procedure can also be used in a corresponding manner when it comes to the Scanning of white characters, which are located in black sections, their surroundings turn is white.

It should now be based on FIG. 6 are shown in what way the in Fi g. 2 device FY shown only in part can be formed. The in F i g. 6, first of all, by means of 1-signals appearing on its output lines gf or sgf , the determination of the first scanning column (k in FIG. 1) which does not overflow any character within the section F (see FIG. 1) is displayed. In addition, the circuit arrangement shown in FIG. 6 enables the position of the rectangular section F appearing on the recording medium T and containing the characters to be determined in a particularly expedient manner and then, as a result of this position determination, to output corresponding position signal elements on their output lines gyf or yf . The in F i g. 6 initially has a memory ZS for storing the sums of such scanning signal elements 1 resulting from the column-by-column scanning of the recording medium, which result from the scanning of black surface elements adjacent to one another in one and the same line perpendicular to the column direction. For this purpose, the memory ZS expediently comprises a number of memory locations Z1 5 . These storage locations are sequentially and synchronously via a distribution device V1, V1

23 24

for scanning within each scanning column, which extends right to the direction of the scanning columns, is connected to an adder Add . The adding parts from within the section add adds the scanning signal elements 1 occurring in the course of a scanning column as the upper or lower section to the limit value. The minimum sum 5 stored in the associated memory location can be used, for example, to determine the position of scanning signal elements 1 and, when call counter windows appear, first delete 12 bits and then a scanning signal element 0 which is 25 bits on the associated scanning signal element. The comparator circuit LSZ can be formed by a gate with its single-signal elements 1. after reaching the predetermined sum of the stored memory space

If one puts the in F i g. 1 illustrated ratios io minimum sum of activated outputs of the addition base, for example, with the occurrence of work Add is connected.
of that Abtastsignalelementes 1, selected from the waste Furthermore, the circuit arrangement according to keying of the by the coordinates Qc, m-l) Loading Fig. 6 is a coincidence gate Gfο on which corresponded black surface element originates, DIE gear side to a successively in Columnense scanning signal element 1 in the circuit arrangement 15 have scanning generated scanning signal elements according to FIG. 6 is added by the adder Add to the leading line η and to the synchronously counter-sum of scanning signal elements 1 which, if necessary, the exceeding of said scanning of the surface elements ... (h-l, m-l) minimum sum of z. B. 25 bits indicating signal ..., (/ c-1, m -1), so far to which the leading line Isz is connected, namely line m-1 allocated memory space of the memory 20 such that at the moment one simultaneous ZS is stored and the just about the distributor disappearance of the exceeding of the upstream circuit Vl is fed to the adder Add; given minimum sum indicating signal to the new sum formed in the adder Add from the line Isz and the last scanning signal element-scanning signal elements is then via the distributor 1 of a sequence of immediately successive circuits V2 again on the line zn-1 of the scanning signal elements 1 The coincidence gate Gfο the coincidence condition sum of scanning signal elements 1 is stored on the line for the allocated storage space of the memory ZS. is satisfied. For this purpose, between each of these If, on the other hand, a result from the scanning of a white two lines η and Isz and the associated surface element, e.g. B. of the surface element (h, m) input of the coincidence gate Gfο a different scanning signal element 0 occurs in each case, then 30 reference element D 10 ν or Dv is inserted, which jeam the counting input α of the adder Add no signal because only with a 1-0- Signal transition to an output element 1, which then emits signal 1 via the distributor. On the output side, the coincidence circuit Vl leads the adder Add , to gate Gfο via a buffer Sfο to the memory associated with the relevant line m , an input of a further coincidence gate GF, place of the memory ZS stored sum of Ab- 35 which with its further inputs would again have to be added to key signal elements 1; instead, the two mentioned lines η and Isz are connected, the occurrence of the scanning signal element 0 is sen, in such a way that at the moment, if necessary, even the deletion of the memory space previously associated with a simultaneous appearance of the above line in question, the specified minimum amount of z. B. memory ZS stored sum of scanning signal 40 25 bits indicating signal on the line Isz and elements 1, which is shown in FIG. 6 is indicated by a connection leading to the disappearance of the last scanning signal element 0 inverter NR to the reset input r of the adder of a sequence of directly successive works Aad. Scanning signal elements 0 on the line η for this

At the individual storage locations ZlS ... ZZS further coincidence gates GF the coincidence conditions

of the memory ZS of the circuit arrangement can be fulfilled after 45 generation. Between the two mentioned

F i g. 6 is therefore only a sum of such derivatives η and Isz and the further coincidence gate

key signal elements 1 stored, the one from the Ab- GF is each a differentiator D 01 or

scanning one of the scanning column just reached Dw inserted, which in each case only with one

still overflowing row of in the relevant 0-1 signal transition on the respective line (n or

50 Isz) located directly adjacent to one another in a row emits an output signal 1. As below

black surface elements. will be explained in more detail, shows the activation

In the circuit arrangement according to FIG. 6 is with the mentioned further coincidence gate GF at

the adder Add a comparator circuit LSZ fulfilling its coincidence condition the sampling

connected, which in each case then via their output des from the relevant scanning column (z. B. k in

line Isz emits an output signal 1 if an at 55 F i g. 1) the overflowing part of a

a currently controlled storage space of the storage contrasting section F of the

chers ZS stored sum of scanning signal drawing carrier T an.

elements 1 exceed a predetermined minimum value to such a display only when scanning. This minimum sum can initially be achieved according to a section F of the recording corresponding to the expected extent of the circumferential carrier T , in which it is actually a section F (see F i g. 1) before its front boundary that can be recognized by machine is specified, but if it is expedient to deal with the excerpt, it is expedient to determine from the determination of the position of the excerpt F in whether a just scanned excerpt is the first within the excerpt F no font 65 has a corresponding height in its scanning column overflowing from the relevant scanning column at the correspondingly running part. Set to the maximum width of a character. this purpose leads to the circuit arrangement. This ensures that there is no lowering of F i g. 6 the buffer store Sfο, on the back of which

25 26

Control input occurs via an upstream OR gate on a line Sp , a transfer of the data stored in the buffer register ZSW when a 1 signal occurs on the line Isz

or the line η a reset signal occurs, from counting steps in a countdown register RZW on the input side directly to the counting input and acts, at the same time the counting up register VZW an inverter NGf to the reset input of a 5 and the buffer register ZSW reset

Counting device Zf . On the one for the be.

cut F predetermined minimum height of z. B. The Rückwärtszählregister RZW is now in the plugged by 17 bits corresponding count output of this counting, the same scanning by the above-the preprovisioning Zf is the control input of a bistable wärtszählregister VZW a direction geKippschaltung Sf whose output had been io controls, in the opposite Rich then controlled with the said one input of the further device. This is achieved in that the coincidence gate GF is connected; the down control input of the down counting register RZW with the control input of this bistable multivibrator Sf is the output of the input side to the line η to a delay register J? from the height of z. B. 23 is connected bits corresponding count output 15 length of a scanning gaps, namely the counter Zf and also in turn connected to a respective one only 1-0 signal inverter NGF. transition of an output signal 1 emitting difle-

The further coincidence gate GF then shows with reference link DlOr. At the control input of the return of its activation by a shift pulse line gf occurring on its output counting register RZW , signal element 1 occurs that just 20, which compared to the previously overflowing register VZW of the register VZW supplied from the relevant scanning column, each part of the section F des Recording medium T have been delayed by the length of a scanning column, has been scanned; With the position of the associated By each of these pulses, the individual white sections of this scanning column are then also given the steps of the down-counting register RZW , the position of the section F in its 1-signal elements stored by the waste by a scanning column overflowed. Step shifted to the left. The countdown

To this cut-out position in the special purpose register, therefore, is attached to each of its first steps

To be able to display moderately, is in the scarf reaching a previously by activating the

processing arrangement according to Fig. 6 a counting device further coincidence gate GF marked counting

for counting the up 30 steps in each sample column.

This signal arrives at one input of one of the scanning signal elements 0 provided. This counting device herewith to the first stage of the down -counting register initially has an up-counting register RZW connected to the blocking gate GYF. With its VZW, whose input is connected to the scanning signal blocking input is this barrier gate GYF η Auselemente to the leading line in the connectedness way gear 35 n-l of said delay register R is the that of the connected Vorwärtszählregisters at the entrance. At the output gy / of this blocking gate VZW in each case only in the case of a 1-0 signal transition to GYF, there is therefore a counting pulse from the eye of the line η. This is shown in view of the signal state 1, in which in the course of one of the circuit arrangement according to FIG. 6, with the help of the scanning column, the scanning point is reached at the level of the already mentioned Difierenzier member D 10ν. 40 upper limit of the excerpt test (see FIG. 1) in be-The up- counting register VZW thus counts the part running from the previous scanning column over the course of a scanning column in the sequence; the signal state 1 lasts from immediately adjacent scanning up to the moment at which the scanning point elements 0, ie the white sections contained in the relevant at the level of the lower limit of the section F scanning column are counted. For 45 in its explanation, which is more detailed than the preceding scanning column, a look at the current part should be taken here. Just for this time-F i g. 1: In the span shown there, at the output of the delay ratio, for example, in the course of the rungsregister R, those scanning signal elements 0 scanning column k just a white segment are counted, which is the one formed by the segment F , namely the one to which the reading characters 50 white section belonging to this section F containing the preceding scanning column; correspond, while at the same time at the first stage in the course of the scanning column h-l , the 1-signal state of the down-counting register RZW, no white section was detected at all. prevails. So for the period mentioned occurs

The counting device is in each case in the eye - the output of the gate GYF, the position of the outlook, in which for the further coincidence gate GF 55, section F of the recording medium T occurs in its coincidence case, a marking signal for the relevant scanning column overflowed part; this marking signal causes the signal pointing in, which may also be specifically referred to as the counter window of the up-counting register signal at this moment, on. This counter window VZW achieved counting step is marked, the signal is thereby directly in a sequence that can be formed in the known manner 60 consecutive signal elements, which are referred to here as position signal elements "L" by shifting a 1-signal element from one ; the first counting stage, for example in the second counting stage of the up-counter window signal, is indicated schematically in the right-hand part of FIG. 1 up-counting register VZW just reached counting step.

stored in an intermediate storage register ZSW for storing which the cutout position is specified. After completion of the scanning of the position signal element "L" in the circuit scanned scanning column, a synchronizing arrangement according to FIG. 6 a conversion signal to the gate GYF , which in this case is not of further interest register YF with a storage of the signal elements occurring in a render manner at the beginning of a scanning column scanning column.

27 28

downstream of the storage capacity. The output element, for example the by Abtastdes gate GYF is split to the one input k and the line m-l certain surface of an OR gate OGYF connected to the element (k, m - 1) derived Abtastsignalanderem input via an inhibit gate SGYF the element 1 arrives from the line η leads to the number output of the circulating register YF . The blocking input α of the adding unit Add, the simultaneous input of the aforementioned blocking gate SGYF, forms the line-individually, namely at one of the pertaining to a clearing input for the circulating register. The sum of that sampling according to FIG. 1, stored in the circuit arrangement ZS , occurs at the memory location of the storage area assigned to line m-1 of this clearing input. 6 signal elements 1 is supplied after each marking, which from the Abeines reached by the up- counting register VZW -io scanning of the relevant surface element (Ic, m-l) th counting step to a clear signal, which for the included row of in one and the same the Duration of a full scanning column and in the process causes a deletion of previously stored position signals m-1 black surface elements "L" that are adjacent to one another. This is achieved in the circuit elements ... (h-l, m-l), ... (k-l, m-l) arrangement according to FIG. The additional coincidence gate GF, a bistable toggle sum, which is connected to the counting input α , is connected to this line-individually stored step FGS , which is added via the one input signal element 1, and it then becomes the output of an AND gate, the other input of which is a new sum such scanning signal elements 1 to which a signal element 1 is supplied via the line Sp at the beginning of a memory column assigned to the relevant line m- 1, stored at a location in the memory ZS . In the case of a blocking input of the blocking gate SGYF upstream, the further bistable flip-flop SYFL , which is at least of the order of magnitude, leads; known dimensions of the recordable flip-flop SYFL (in particular by one also given to the output of the last-mentioned call counter front panel) and to the mentioned line carrier T with the (the counter window Sp a further AND gate connected, the 25 speaking) section F and then the maximum leads to the respective reset input of the two bi-character widths corresponding to predetermined minimum stable flip-flops SYFL and FGS . sum of z. B. 12 or 15 bits, this minimum

To the coincidence gate GF, which with its active sum up to reaching the front

fouration indicates that the particular delimitation of the section F for the line m-l

within the cutout F no characters must be exceeded 3 ° and thus even more so in the case of the

overflowing scanning column overflowing part of the scanning of the black surface element (k, m- 1).

Excerpt F of the recording medium T from exceeding the specified minimum amount

has been scanned, and its output line for this line m- 1 is indicated by the fact that to

Above-mentioned output line gf of the facility at the appropriate time at which also on

FY forms, finally a 1-bit memory SGF 35 of the line η is the associated scanning signal element 1

connected. This memory becomes signal state 1 on the Isz line when it occurs

groping a cutout through the first of prevails.

The signal emitted by the coincidence gate GF is activated and if the scan then continues within the scan, it remains in this state until it continues from the line column k to the height of the line m, then yfe occurs, on the basis of the 40, which is not of further interest here, on the basis of the values shown in FIG 1 a signal occurs after reaching the rear limit of a ratio at the corresponding point in time on section F , a scanning signal element 0 in the idle state of the line η. One is deferred. The output line of this 1-bit such Abtastsignalelement 0 would optionally, memory SGF, the above-mentioned output particularly when just the front boundary sgf management of the facility FY represents. Would have been exceeded by the overall 45 of the section F, the compound dashed lines shown between the storage deletion date on which the line m and the comparator zugeordcher SGF LSZ is stored indicated that, as stated above, first to cause a sum of Abtastsignalelementen 1 Neten location of the memory ZS. To determine the position of a section F at the point in time now being considered, such a first deletion within the section no character 50 is not necessary, since now at overflowing scanning column in the comparator the relevant memory location no sum circuit LSZ a smaller minimum sum of z. B. of scanning signal elements 1 is stored. May be on the 12 predetermined bits, and then to the output line Isz but independently thereof, reaching the rear segment boundary is the disappearance of k within the scanning gaps full, the width of a character corresponding to 55 to the line m-l forthcoming display of the minimum sum of z. B. 25 bits. Incidentally, the above-mentioned lapse of the specified minimum sum prominence yfe still leads to the blocking input being called, ie there is a 1-0 signal over a blocking gate connected upstream of the memory YF , as it is at the same time on the scanners after reaching the rear cutout limits - signal elements leading line η occurs. To be able to delete the cut-out position 60 stored in the memory YF for the two lines η and Isz at the same time. the 1-0 signal transitions have over the two dif-

To further explain the in F i g. 6 illustrated ferenzierglieder DlOv and Dv the fulfillment of the

th circuit arrangement should now again the coincidence condition for the coincidence gate Gfo

Fig. 1 can be considered. Based on and the activation of the following Zwider in FIG. 1 is assumed to result in 65 schenspeichers Sfο, so that from now on the

men that the scan just over the counting means in Zf by each of the on line T

Fig. 1 draws indicated sampling column k. Each clock pulse that occurs by one counting step

while scanning a black area is switched on.

29 30

This state now lasts until the specified maximum load separates within the

Sampling column k exceeds the white surface element (k, p-l). ·

has been scanned and the scanning point has now reached the level of the line ρ at the same time as the processes described so far. In this the moment obtained in the course of the scanning column k there is a 0-1 signal transition 5 sequences of immediately successive Abs both on the line η and on the line scanning signal elements 0 in the counting up register VZW Isz, since the scanning signal element (k, p) counted a black one. Based on the in F i g. 1 is a surface element that is based on a correspondingly set relationship during the scanning lengths, by black scanning signal elements column k, just such a sequence - correspondingly formed part of the line ρ immediately follows. The one white section of this sampling column k - counted during the previous white section of the sampling. The carried out at the moment of activation of the column k of the counter Zf said further coincidence gate GF and counting of the surface elements of this white portion at the moment who had simultaneously with the Wiederzur determining the length of the white portion appear an indication of exceeding the vorzur result, a counting step reaches was, the 15 given minimum sum of z. B. 25 bits through which the minimum length of, for example, 17 bits speaks to one another in one and the same line ρ , which is easy to recognize through the height of a machine-adjacent black surface element ... (h-1, p) Character-containing section ... (k, p) starting scanning of the white section determined by the section F is given, white section (Jc, m) ... (k, p- 1), but not a counting step by using it, which corresponds to a disappearance of such a display of the given maximum length of, for example, 23 bits exceeding the specified minimum sum of. Under these conditions, is caused at the end of 25 bits, then another of the (k, p) from the counter Zf during this white-black portion ... reached counting section counting process carried out which is with in the intermediate storage register ZSW marked and the corresponding count outputs of Zähleinrich- 25 at the end of the scanning column k in the down counting registerZ / connected bistable flip-flop Sf still transmitted stei RZW. Activated in the down-counting register RZW , so that the further coincidence gate GF is now prepared for the coincidence case from the output line n-1 of the. The coincidence delay register R via the differentiating condition for this gate GF is now met by the element DlOr with a delay of the duration that with the 0-1 signal transition to the two scanning columns the lines η and Isz previously counted upwards the counting signals fed to the two differentiating registers VZW are fed once again to elements D 01 and Dw signal elements 1 to the two. The down-counting register RZW counts further inputs of the mentioned further coincidence, therefore, to a certain extent again, which arrive in the scanning column k denzgatters GF. The activation of this contained white sections, whereby during the ver coincidence gate GF indicates that the counting step from the down counting register is entered with the just 35 remaining on the scanned white section (k, m) ... (k, p-V) marked during the counting up Signal location of such on the recording medium T is emitted. Was within the time period in which occurring cutout F in his this signal to the pending loading of the one input of the gate GYF taken scan column k uncrowded part fixed, access provided to the lock input of this gate, in which due to its size 40 of the line n-1 may contain the characters to be processed, which originate from the scanning of the white section and the position on the recording medium, that are to be processed by machine, so that for the duration of the abbots. This determination is based on the fact that scanning along the line of white surface elements forming this white section at the end of the sequence of white surface elements or black section preceding the relevant white section, a previously 45 derived scanning signal elements 0 at the output indicating that the preceding GYF position signal elements have been exceeded » L «given minimum sum are subordinated by a row which represent a» counter window signal «showing the position of the section F in one and the same line (m-T) adjacent to the part of black surface elements overflowed by the scanning column k ,
and that precisely at the beginning of the circuit section, at the beginning of the circuit section, a further black time following a white section occurs, such a display of the exceeding of the arrangement according to FIG. 6 on; In addition, they are re-entered into the circulating register YF of the length of an Abist for the specified minimum amount. An elimination of entered on the recording probe column so that they are stored in 55 and possibly also in which, based on their height, no further scan columns for specifying the characters to be recognized are to be expected from the outset , cut position can be used. In the case was made using the counter DA Zf circuit arrangement according to F i g. 6 is made beforehand that a predetermined seen that the stored position signal elements minimum length of z. B. 17 bits less than 60 "L" can be deleted as soon as a marking or a predetermined maximum length of z. B. 23 bits of white section in the counting device VZW, ZSW, exceeding white section of the further loading RZW indicates that consideration was excluded in a further scanning column, so that in turn a location determination for the font containing the location of the characters containing the characters Section F made section F in its from the relevant section. The repeated positional sensing column overflown part with the position of a determination made possible by this has the advantage that in the course of the absolute white section it is determined that the sensing compared to an initially determined position does not have the specified minimum length under the section F, such as

31 32

they are for example by oblique to the sensing coils. This means that a 0-1 signal transition or a 1-0 signal can be detected when the cutout boundaries are running. transition within a considered line to the in the above with reference to the F i g. 6 explained to this line associated memory location of the device (FY in Fig. 2), the said training 5 single memory ZS gf stored sum of outgoing lines, SGF, GYF and further comprising yf, tastsignalelementen 0 or Abtastsignalelementen 1 thus determined to it is once again erased in summary and from now on a sum of denials is formed, the position of the section F of the recording that is testifying to its surroundings and the detection signal elements 1 and / or the scanning signal elements 0. The comparator circuit LSZ becomes the carrier T in the following way: It initially adds a gate at io, which is expediently connected immediately after column-wise scanning of the recording medium, which is only transferable when there is an occurrence of Abdie from the scanning of black area scanning signal elements 1.
It has already been pointed out above, because for the line-individually stored sum that in the circuit arrangement according to the invention of those scanning signal elements 1, which from the sampling 15 of the delay memory RR expediently in the scanning of the surface element in question, depending on a Determination of the rear row contained in one and the same lowering boundary of a possibly running at the front right to the column direction under cut boundary is unlocked directly into the black surface elements adjacent to each other. In each case, the 20 for which purpose in the circuit arrangement according to FIG. 2 the exceeding of a predetermined minimum sum AND gate Glaz is provided, which with his of z. B. 25 bits by such a row in the one input to a black-back border of a character that is adjacent to one another after determining the relevant line, a signal of zer surface elements is displayed. In each case with the performing line gz lies. This line gz represents an output line of the one in FIG. 2 only partially shows the line, the row of black areas- shown device ZY . The element-terminating white surface element her- device ZY still has another output line touching scanning signal element 0 is the concerned yz , which is line-individually to the control input of the decelerator Stored sum of further Ent-scanning signal elements 1 connected downstream from approximate memory RR is deleted. After an equal- 30 locking gate Gnxy leads. Via this further time-out with a delay line caused by this, the delay speed of such a display of the exceeding memory can only be unlocked for the scanning signal elements of the in Question coming scanning of a black section within the scanning columns can be effected. Using the half of the scanning column just scanned, FIG. 3 is intended to show how such a position of an adjoining white alignment ZY can be constructed in detail.
section of this scanning column with subsequently the same- The circuit arrangement according to FIG. 3 has a gate GOwm at the same time as the recurrence of such a display, which, when the predetermined minimum sum 40 is exceeded, is a locking input to a black surface element stored in the memory register WM (see Fig. 2) when such a row occurs When scanning begins, the sum smaller or larger sum at a further black section within the output of the adder Add (FIG. 2) a signal wheel scanned scanning column cherten the position of the output line g1 or gr of the section F in its from the relevant Sampling 45 comparator Vgl (F i g. 2) is connected and found with a column overflowing part. In this one blocking input on one of the scanning signal elements circuit arrangement, which incidentally is via an application-leading line n-1. With a third extension in the inventive circuit arrangement control input of the gate is located on a GO wm Leinach Fig. 2 addition, independent significance to-tung Ig / 2, the intra only comes after determination of the first, may be in accordance with F i g. 6 provided memory 50 half of the section F no characters overflow ZS together with the distribution circuit V1, V2 and fenden sampling column (k in Fi g. 1) for the duration of a control signal 1 to the adder Add identical to the memory ZS, sampling column. For the case considered here of the distribution circuit V1, V1 and the adder, that the circuit arrangement after Add of the circuit arrangement according to the invention is FIG. 3 with the circuit arrangement according to FIG. 2 according to FIG Circuit parts have been explained both for the line-specific addition, in the second behind a scanning signal elements 0 which are used at the front tion and storage of the respective possible section delimitation directly to the scanning signals 1 as well as the characters passing over into the respective cutting environment Sampling column (/ c + 1 in FIG. 1) on its den. For this purpose, advantageously, without this gz in 60 output line to output a signal element 1, the drawings, there is shown still, the Zählein- leads said conduit Ig / 2 likewise for the gear α of the single adder A dd an OR duration of that scanning gaps Ic + 1 a control signal. Gate connected immediately upstream, this is achieved by the fact that an AND gate and a WEDER-NOR-discussed line sgf (see FIG. F i g. 2 and 6) lead to the two inputs on the gate, both of which lead to the above inputs Inputs syn- 55 from the detection of the first scanning within a scanning column with the scanning within a scanning column cut F no character overflowing scanning the corresponding scanning signal elements column (k in Fig. 1), at which the 1-state prevails, a two consecutive scanning columns supplied only at an output signal at an O-1 signal transition

33 "34

output differentiator Dsgf is connected, which in the adder Add (see Fig. 2) to a maximum of which via a 1-bit buffer 1GF and at least within predetermined limits of the maximum sum of the scanning column, which is connected downstream of it and is only stored at the beginning of a storage register WM Transferable gate G12 leads to a different character-individually formed sum in a further 1-bit memory IGF 2 ; its 5 lead from scanning signal elements 0. These are the output line, the said line Ig / 2, those scanning signal elements 0, which come from the Aban at the same time via a likewise only at the beginning of a scanning of the gate of the rear section F , which can be transmitted between the upper limit of the scanning column, and the by a dashed line ο the control input of the 1-bit memory LGF2 is connected to the indicated upper character limit. Within the mentioned scanning column (£ + 1) is the io section of the scanning column k and from the scanning the gate G Owm due to its connection to the between the by a dashed line μ to the two lines gl and gr only for the lower character limit and the Scanning signal elements 0 capable of being transmitted, which originate at the lower limit of the section F from a section of the scanning column k which is at most within predetermined limits. On the maximum line gyf stored in the memory register WM , the position signal elements “L”, which differ from the section sum and which are formed individually for each line, appear as they carry the sum of scanning signal elements 0. In the right part of FIG. 1 are indicated. As long as one input of gate GOwm is connected to a co-ordinate sampling point via the upper surroundings of the cidenzgatter GOwm /, the other section F of which is running, the only input on line n-1 is connected to a line gyf which has 20 sampling signal elements 1 so that at the output of the position signal gate GO wot indicating the position of the section F and the subsequent coincidence elements, as in the right part of FIG. 1 gattersGOwm / the O-state prevails. After are indicated; the line gyf can be an output - the transition from the line m-1 to the line m, ie line of the above with reference to FIG. 6 after exceeding the upper cutout limit device FY . 25 tongues, step on the line n — l scanning signal

Furthermore, in the circuit arrangement according to elements 0, and at the same time the line gyf Fig. 3 leads a blocking gate Goa and an AND gate Gof position signal elements "L", so that now at the output ■ provided; the blocking gate Goa is with its blocking the coincidence gate GOwmf the 1-state input directly to the output of the coincidence gate prevails. This state lasts until the GOwmf and with its other input via a sampling point at the height of the upper limit ο only with a 0-1 signal transition an output signal from the differentiating element DTF , which is triggered at the front area, is sent to the longitudinal ends Section 9 according to fig. 1 has arrived. Line gyf leading from this signal element is connected, instantly the gate GOwm is no longer locked while the AND gate Gof escapes with its one input from one of the two lines gl or gr directly to this line gyf and with its other one, As a result, at the output of the ren input via a differentiator which emits an output signal only in the case of a 1-0 signal over coincidence gate G Owmf to a 1-0 signal transition. DWS connected to the output of the differentiating circuit DWS to the coincidence gate G0 wmf thus occurs a signal member 1 nachist. The two gates are each followed by a 1-bit intermediate line gyf, as before, position signal memory Soa or Sof . In addition, there are 40 elements "L" leads, the fulfillment of the coincidence three further AND gates Gloz, GIz and Gluz is a precondition for the AND gate Gof ; see this. This has the consequence of these further AND gates that the 1-bit buffer Sof first AND gate Gloz is activated at the coincidence gate. This means that the further AND- GOwmf and the gate GIz after the blocking gate Goa are connected from its lower input for the switched 1-bit buffer memory Soa. 45 prepared coincidence. This state remains. The second further AND gate GIz is also maintained until the sampling point at the level of the coincidence gate GOwmf and at the AND of the lower limit u of in FIG. 1 gate Gof shown downstream 1-bit buffer character (number 9) and thus connected at the level Sof . The third further AND gate of a line (u) has arrived, in which Gluz is already at this 1-bit buffer 50 of the front boundary of the section F at Sof and via a white only with a 1-0 signal transition Line up surface elements. In the line (u) corresponding to an output signal emitting differentiator DFT , the scanning signal element 0 now occurring on the line gyf line n-1 leading to the position signal elements is connected. The three other AND gates mentioned, in turn, lead to an input of an OR gate at most, each leading to an input of an OR gate OGz stored in the storage register WM. The activation of this OR gate th maximum sum differing line-by-line OGz thus shows that the rear limit formed sum of scanning signal elements O has been reached, which means that one displayed at the front section boundary by 1-signals on the line g1 or gr directly into the section environment (T in F i g. 1) and a renewed unlocking of the gate override character. 60 GOwm. At the exit of the coincidence

For a more detailed explanation, at this point a gatters G Owmf prevails again the 1-state,

Look at the fig. 1 thrown. As already stated so that now the coincidence condition for the further

is based on the in F i g. 1 shown AND gate GIz is fulfilled; at the same time the 1-bit

conditions provided the gate G Owm from the Lei-Speicher Sof, which thus from the upper writing

direction Ig / 2 for the duration of the scanning column 65 character limit ο to the lower character

k + 1 unlocked. Under the influence of the two line limit «was activated, in the idle state gl and gr transfers it to those placed on the. That at the output of the further AND gate

Line n-1 occurring scanning signal elements 0, GIz occurring signal element 1 indicates that the

35 36

rear delimitation of such a white surface section delimitation extending towards the front scanning column extends directly into the out-elements. At the same time, the 1-bit memory cut environment T is set back to the idle state (number 9 Soa . The in Fig. 1) is reached, which occurs neither to the upper nor output of the further AND gate Gloz to the lower limit of the Excerpt from F an- 5 signal element 1 thus shows the reaching of the rear end. the limitation of such a sign, the so-

If, in deviation from the in Fig. 1 ones shown, probably at the front and at the upper Ordered conditions the character in question limitation of the detail F in the immediately does not pass only the front segment limit check ambient T.

but at the same time also to the lower output. The OR gate OGz, which combines the three other section limits, initially up to the AND gates Gloz, GIz and Gluz , is to activate the 1-bit buffer Sof connected to the one input an additional AND processes just described analog processes gate GZ , the other input from. Below the character there is now no line extending from the front output 15 Sp 10 to the output of a bistable multivibrator. This bistable flip-flop Sp 10 is a section boundary up to the one just considered with its control input at one of the minimum height scanning column (k) containing white surface elements; of a machine-recognizable character instead, the sequence of the reset input on line gyf to one of the maximum height of an occurring position signal element "L" is ended when the lower output correspondingly predetermined counting level is reached and with its cut limit. The 20 characters to be recognized by machine correspond to the 1-0 signal thus occurring on the line gyf and the predetermined counting stage of a counter ZpIO transition acts via the differentiating element DFT to connected. The counter Zp 10 is connected to the lower input of the further AND gate Gluz, the 1-bit memory Soa, Sof OR-a, so that for this AND gate, which is controlled via its gate OGpIO, so that the counter Zp 10 upper input from the 1-bit memory Sof for the 25 during each clock interval, during which a coincidence case is prepared, the coincidence condition of such 1-bit memory is activated in order to meet a count. At the same time, the 1-bit step is switched on again. Was after, as shown memory Sof, which thus was of the upper written, such a 1-bit-store just over ο character boundary to the lower boundary of the training of a scanning gaps between the upper boundary section F enabled in the idle state to - 30 and the lower limit (see. Fig. 1) one withdrawn. The signal element 1 that occurs at the output of the further AND-keyed character arrives at the gate Gluz , indicating that the counter Zp 10 is at a counting step corresponding to the level of the relevant character. Together with it is sufficient that at the front and at the same time at that of the bistable flip-flop Sp 10, the counter allows the lower limit of the section F in its 35 ZpIO to check the height of a character, environment T. whose rear limit has just been reached. Is the

If it is, again in deviation from the character height, too small or too large for it to be in FIG. 1, in order to create a typeface to a machine-recognizable character that could be treated on the front and on the upper one, the bistable flip-flop stage Sp 10 delimitation of the section F in its surroundings T 40 is not activated or activated at all. it is put back again, passes over, so, in contrast to the two cases previously considered when the output of the OR gate OGz activated, runs above the text; In this case, the coincidence condition will not indicate a line that is not met by the previous output for the additional AND gate GZ. If, on the other hand, a character has been scanned up to the point just viewed, the height of the scanning column has white surface elements. After 45 does not go below or above the sampling point, the upper cutout limit, the gate GO wm gang of the OR gate OGz is a signal element 1 not from one of the two lines gl or larger occurs, the bistable multivibrator in the 1 state, which unlocks; at the output of the gate G Owm and that the coincidence condition for the gate GZ is also fulfilled at the output of the subsequent coincidence 50. The activation of the OR-gate OGz shows gattersGOwm / so that the 0-Zu- still prevails, that the rear limit of one was confessed at all. At the same time, however, a 0-1 signal transition occurs on the line, if necessary at the front section boundary gyf , since from now on this line gyf transitions directly into the section area, the position signal element "L" on the sign was reached, which is his step. The signal element 1 given by the differentiating element DTF by a machine-recognizable signal element 1 causes the characters to be fulfilled, while the activation coincidence condition for the blocking gate Goa, which the additional AND gate GZ indicates, indicates that activation of the subsequent 1-bit memory, the height of the character results in a Soa . This is the further AND machine-recognized character. The gate Gloz prepared from its lower input for the 60 output line gz of the mentioned additional AND coincidence. The coincidence condition gate GZ thus represents each after determination is fulfilled as soon as the scanning point at the level of the rear boundary of a character has reached a lower limit u of the character signal element 1 leading line, as it is above; from this point in time onwards it is again mentioned in the explanation of FIG. at the output of the coincidence gate GOwmf of the 65 In the device ZY shown in Fig. 3 to the 1-state, since below the character determination of the rear limit of a scanned character again a line with itself from the front th character is still a per se be-cutout limit up to to the just considered known counting device for counting the activation

the 1-bit buffer (Soa, Sof) is provided. This counting device initially has an up-counting register VZ , the input of which is connected to the output of the OR gate OGpIO connected downstream of the 1-bit buffers via a differentiating element Dv which only emits an output signal when there is a 0-1 signal transition. In this counting device, the counting steps of the up-counting register VZ that are reached at the moment when the additional AND gate GZ is activated are marked. For this purpose, the counting device has an intermediate storage register ZSZ , which stores the counting steps of the up-counting register VZ marked by activation of the AND gate GZ. Thereafter, the counting device emits a signal 1 to one input of a further AND gate Gze , the other input of which is connected to the output of a delay register Rz with the length of a scanning column, which is connected to the input side when such a marked counting step is reached the OR gate OGp 10 connected downstream of the 1-bit buffers. This is achieved in that the intermediate storage register ZSZ transfers the counting steps of the up-counting register VZ stored in the course of a sampling column (e.g. k + 1) and thus marked at the beginning of the next sampling column (k + 2) into a down-counting register ZZ, the control input of which with the The output of the delay register Rz is connected via a differentiating element Dr which emits an output signal only in the event of a 0-1 signal transition and to whose first stage the one input of the further AND gate Gze is connected. For the AND gate Gze, the coincidence condition is thus met in the course of the mentioned next sampling column for the period of time during which the sampling point is between the points shown in FIG. Boundaries ο and u , shown in dashed lines, possibly coinciding with the upper or lower section delimitation, are located. At the output ze thus occurs in the course of the relevant scanning column, for example in the course of the scanning column Ic + 2, an end-of-character signal indicating the reaching of the rear boundary of a scanned character and at the same time its position. In the circuit arrangement according to the invention according to FIG. 3, the AND gate Gze is followed by a circulating register YZ , in which the end-of-character signal elements indicating the position of the character can be stored synchronously with the scanning within the scanning columns. The output yz of this circulating memory YZ can be connected to the control input of a further unlocking gate Gnxy connected downstream of the delay memory RR of the circuit arrangement according to the invention according to FIG. 2, as is also shown in FIG. 2 is indicated; the delay memory RR is then only unlocked for those scanning signal elements of the scanning columns which are considered in accordance with the above explanations and which occur within the limits given by the character position stored in the circular memory YZ. The delay memory RR must have the scanning signal elements of a number of z. B. can store 27 scanning columns which exceed the maximum character width of, for example, 24 bits by the number of scanning columns (e.g. k ... k +2) passing from reaching the rear limit of a character of the scanning columns passing to unlock the unlocking gate Gnxy.

The above with reference to FIGS. 3 explained circuit arrangement is thus able, to summarize it again, to reach the rear boundary of a character passing directly into the cutout area T at the front cutout boundary with the occurrence

ίο of a surface element (/ c, o) at least one of the front edge of the cutout to a minimum length specified according to the width of a machine-recognizable character and of surface elements not covered by the character (h, o), ... (k, o) existing line segment and a surface element (k, u) occurring only at a distance therefrom that is maintained according to the height of a character, at least one other such line segment (h, u) ... (k, u) in the course of the first within the cutout F no characters overflowing scanning column k and possibly the occurrence of the upper or lower cutout limit instead of one of the surface elements mentioned and determine the position of the character with the position of between the so-called surface elements (k, o) and (k, u) or between the such a surface element and the lower or upper cutout boundary lying A section (k, o). .. {k, u) to determine the relevant sampling column k. After determining the position of the section F in its part (k, m) overflowing from the first scanning column k, which runs behind a character that merges directly into the section environment T at the front section boundary. . . (k, p - l) the reaching of the rear boundary of a character and at the same time the position of the character in the direction of the scanning columns by a comparison between the position signals indicating the cutout position and the occurrence of such a sum of scanning signal elements 0, which are added synchronously within a scanning column, in each case which exceeds a minimum sum of, for example, 15 bits specified in accordance with the width of a character and at the same time deviates from the maximum sum of scanning signal elements 0 corresponding to the number of scanning columns h ... k-1 overflowing the character within predetermined limits, determines the indicating signals and then determines them stored in the correct position. A circuit arrangement operating according to the above-mentioned principle, which, incidentally, is based on the application in the circuit arrangement according to the invention according to FIG. 2 is also of independent importance, the reaching of the rear boundary of a character and at the same time its position in the specified manner can also be determined if, in deviation from the relationships shown in FIG. 1, the front cutout boundary runs obliquely to the direction of the scanning column. For this purpose, the described comparison between the position signals indicating the section position and the signals indicating the occurrence of such a line-individually formed sum of scanning signal elements 0, which deviates from the maximum sum at most within predetermined limits, synchronously within a scanning column

carried out, it is expedient, before the comparison, for the lines extending over the section F to increase the respective sum of the scanning signal elements 0 corresponding to the expected inclination.

This can be done in the circuit arrangement according to the invention according to FIG. 2 and 3 can be achieved in that the above-mentioned line Lgf 2 of the circuit arrangement according to FIG. 3 to which one input of an AND gate (not shown in the drawings) is connected, the other input of which is connected to the line gyf carrying the position signals and which leads to additional addition inputs of the adder Add . As in detail from FIG. 5 is seen in the total increase can respective adders of adder yidd to the backward extending from the respective preceding adding stage the carry line above which a respective input of a leading to the gates UG and EC additional EXCLUSIVE-OR gate scaler and a via an additional OR Gate ZOG as well as the AND gate UG be connected to the carry output ü of the adder leading additional AND gate ZUG , the other input of which forms such an additional addition input ζ . This ensures that even with a deviation from the in FIG. 1 illustrated relationships z. B. obliquely to the bottom left front boundary of the section F then resulting from the line /? - 1 resulting maximum sum of scanning signal elements 0, which is stored in the course of the scanning column k in the memory register WM , in the comparison mentioned also for the lines ο and u line -specific sums formed by Abatstsignalelemente 0 are exceeded or at least reached, so that the above-described unlocking and blocking of the gate GOwm through the output lines gr and gl of the comparator Vgl is guaranteed. In this connection it should also be mentioned that in the circuit arrangement according to FIG. 3 such an additional addition of 1 bit to each line-individually formed sum of scanning signal elements 0 is achieved from the outset in that signals from a scanning column (Ic) appear on the lines «-1 and gyf leading to the two gates GO wm and GOwmf , which that scanning column (/ c + l) from which the signals appearing on the comparator output lines gr and gl originate, immediately precedes.

So that in the circuit arrangement according to the invention according to FIG. 2 the delay memory RR can also be unlocked by means of the unlocking gate Gnxy within the limits given by the respective character position for the scanning signal elements of the scanning columns in question, if in the currently scanned section F another free-standing character adjoining the front section boundary Character follows or there is only one such character that does not adjoin the front section boundary, leads to a further input of the OR gate OGz of the circuit arrangement according to FIG. 3 yet another AND gate Gz, one input of which is connected in a manner known per se to the output of a WEDER-NOR gate Gp 00, the same as a further provided blocking gate Gp 10 step by step the scanning signal elements and their position within a scanning column corresponding, per se known projection signal elements are fed simultaneously to one input each. S The WEDER-NOR gate Gp 00 leads via a buffer Sp 00 to one input of an AND gate Gp 0010, the other input of which is connected to the output of the blocking gate Sp 10 and which in turn has a 1-bit buffer Sp 0010 leads to the other input of said further AND gate Gz . At the same time, a further input of the OR gate OGp 10 is connected to the 1-bit memory Sp 0010. The counting device including the up -counting register VZ also has an intermediate storage register ZSz , which stores the counting steps of the up-counting register VZ marked by activation of the OR gate OGz and transfers them to a down- counting register RZz at the beginning of the next scanning column, whose control input matches that of the down-counting register RZZ is interconnected and the one input of an AND gate Gl is connected to its first stage. This ensures that the AND gate Gl at its output 1 the reaching of the rear boundary of a scanned character od. 3 is fed to one input of the further AND gate Gze connected with its other input to the first stage of the down counting register RZZ. The scanning signal elements fed step-by-step to the blocking input of the blocking gate GpIO and to one input of the WEDER-NORCH gate GpOO are expediently supplied by a gate Gn-lyf ", which can only be transmitted for the scanning signal elements occurring synchronously with the position signal elements" L "indicating the cutout position. this Abtastsignalelemente arrive at the same time via the one input of an OR gate OGp to a circulating register Rp of the length of one scan column, at the output of the other two inputs of the two gates GPIO and GpOO are connected. in the circulation registers an erasure gate SGP is provided with a clear input is connected to the aforementioned line 1 and which can be connected to a further clear input on the output line gyf of the circuit arrangement according to FIG front cutout limit ng contiguous character containing part of the section F is included transversely to the scanning direction.

Further explanations of this partial circuit of the circuit arrangement according to the invention according to FIG. 3 should be superfluous after the functional principles on which this subcircuit is based are already known.

The circuit arrangement according to FIG. 3 it should also be noted that the counter Zp 10 contained in it, if necessary, with the counter Zf of the circuit arrangement according to FIG. 6 can be identical, it being possible for counting signals to be fed alternately from scanning column to scanning column from the OGpIO or the buffer memory Sfο; at the same time, this change can also be taken into account when activating the further switching means: this

does not need to be pursued further here, however, since this is not necessary for an understanding of the invention is.

Finally it should be noted that the gate circuits, bistable flip-flops, register and counters included in the circuits shown in the drawings can be realized in a known manner. Examples of such realizations are in "Fig. 4a to 4k shown

4a shows a bistable multivibrator with two control elements;

Fig. 4b shows a built with bistable flip-flops Shift register;

F i g. 4 c shows one constructed with bistable flip-flops Counter;

F i g. 4 d shows a register combination as used in the circuit arrangements according to the invention is used;

Fig. 4e and 4f show the two basic circuits, with which the various gates can be realized;

F i g. 4g shows an negator;

F i g. 4h shows a only in the case of an O-1 signal transition a differentiator emitting an output signal, and

F i g. 4 k shows a only in the case of a 1-0 signal transition a differentiator emitting an output signal.

Claims (40)

Claims: 30 1. A method for the automatic detection of characters contained in a section of a recording medium that contrasts with its surroundings, the degree of brightness of which corresponds to that of the section environment and which can pass directly into its surroundings at the front boundary of the section, characterized in that the column-wise scanning of the The scanning signal elements originating from the recording medium (T) are first stored in a delay memory (RR) , the storage capacity of which permits the storage of the scanning signal elements resulting from at least one number of scanning columns (... h ... k-l) corresponding to the maximum width of a character that at the same time the scanning columns (h ... k ) overflowing the section (F) are counted and that, according to a determination made according to the surface elements of the section (F) not covered by the characters, the first Abta st column (k), which runs behind a character passing over at the front edge of the cutout directly into the cutout area (Γ), the delay memory (RR) for the scanning signal elements of a scanning column (h + 1), that of said scanning column (k) in one the corresponding interval is preceded by the counting result obtained when counting the scanning columns (h ... k ) overflowing the section (F) , and the subsequent scanning columns (h + 2, ... ) are unlocked for forwarding to the actual recognition device. 2. The method according to claim 1, characterized in that the delay memory (RR ) is unlocked at the earliest for the scanning signal elements of the second scanning column (h + 1) overflowing the section (F). 3. The method according to claim 1 or 2, characterized in that at the same time that the scanning signal elements obtained in the column-by-column scanning of the recording medium (T) are first stored in the delay memory (RR) , which from the scanning of white surface elements (k-l , m) resulting scanning signal elements 0 are each added to the line-individually stored sum of those scanning signal elements (0) that result from the scanning of the row of white surface elements adjacent to one another in one and the same row (m), which also contains the relevant surface element (k-l, m) (h, m, ..., k-1, m) resulting, and in that after determination of the cut-out (F) overflowing the first scan column (k) behind an immediately transitioning to the front cutout limit in the cutout area (T) mark runs, the delay memory (RR) for the scanning signal elements of a scanning column (h + 1), that of said scanning column (k) in one the same for a protracted over the opening (F) line (m ... p- 1) stored maximum sum of scanning signal elements (0) corresponding distance precedes, and the subsequent scanning columns (h + 2, ...) is unlocked for forwarding to the actual recognition device. 4. The method according to any one of claims 1 to 3, characterized in that the cutout (F) overflowing first scanning column (k), which runs behind a at the front cutout boundary immediately into the cutout area (T) merging characters, with the occurrence at least a sum of line-individually summed scanning signal elements (0) in the course of the part (k, m; ...; k, p-1) of the first within the section (F) no characters overflowing scanning column (k) is determined. 5. The method according to claim 2 and claim 3 or 4, characterized in that the number of the first scanning column (k) running behind the character, said scanning column (h +1) sowiedie intermediate scanning columns (h + 2, ..., k-l) comprising scanning columns (h + 1, ..., k) at least 1 less than that in the course of the first scan column extending behind the character (k) is stored maximum sum of scanning signal elements (0). 6. The method according to any one of claims 1 to 5, characterized in that the delay memory (RR) as a function of a determination of the rear boundary of a character passing directly into the cutout area (T) at the front cutout boundary in the said first scanning column (k) is unlocked. 7. The method according to any one of claims 1 to 6, characterized in that the delay 609 609/166 approximately memory (RR) is only unlocked for the scanning signal elements of the scanning columns Qi + 1... k) that occur within limits given by the character position. 8. The method according to any one of claims 1 to 7, characterized in that reaching the rear boundary of a character passing over at the front cutout boundary directly into the cutout environment (T) with the appearance of a surface element Qc, o) at least one of the front cutout boundary a line section Qi, o; which exceeds the minimum length (e.g. 15 bits) specified in accordance with the width of a character and consists of surface elements not covered by the character. ..; k, o) and a surface element Qc, u) at least one further such line section Qi, u; ... ; k, u) in the course of the first within the section (F) overflowing scanning column (A :) and possibly the occurrence of the upper or lower section delimitation in place of one of the surface elements mentioned and the position of the character with the position of the between the mentioned surface elements (k, o; k, u) or between the one such surface element and the section boundary lying section (k, o; ...; k, u) of the relevant scanning column Qc) is determined. 9. The method according to any one of claims 1 to 8, characterized in that after determining the position of the cutout (F) in its from the first scanning column Qc), which runs behind a at the front cutout boundary directly into the cutout environment (T \ overlaying characters , overflowing part (k, m; ... ; k, p-l) the reaching of the rear boundary of a character and at the same time its position in the direction of the scanning columns by a comparison between the position signals indicating the detail position and the synchronous to this within a scanning column Qc + 1 ) the occurrence of such a sum of line-individually summed scanning signal elements (0) which exceeds a minimum sum (e.g. 15 bits) specified in accordance with the width of a character and at the same time depends on the number of scanning columns Qi, .. overflowing the character. k-V) corresponding maximum sum of scanning signal elements (0) at most deviates within predetermined limits, a n-indicating signals is determined and, if necessary, stored in the correct position. 10. The method according to claim 9, characterized in that before the comparison for the lines Qn) extending over the section (F), their respective sum of scanning signal elements (0) is increased by at least 1. 11. The circuit arrangement for implementing the method according to claim 1, characterized by a memory (ZS) with the length of one scan column Qi) corresponding number of one line Qn) associated with storage locations (DMF), successively through a distribution circuit (Vl, V2) synchronously with the scanning within a scanning column Qi) are connected to an adder (Add) which adds the scanning signal elements (0) occurring in the course of a scanning column Qi) to the sum of scanning signal elements (0) stored at the associated memory location (ZmS) and at Occurrence of a scanning signal element (1) deletes the sum of scanning signal elements (0) stored in the associated memory location (ZmS) by means of a memory register (WM) in which up to the first scanning column (k) that does not overflow within the section (F ) during each White portion Qc, m; . . .; k, p-l) of a scanning column Qc) the maximum sum of scanning signal elements (0) occurring for one of the lines Qn ... ρ-1) extending over the white section (Jc, m; ...; k, - T) is, and by a counter (Zxza) with one of the number of scanning columns overflowing a character of maximum width corresponding counting volume (z. B. 26 bits), the input side after determining a first scanning column (F) overflowing the section (F), which is behind a at the front edge of the cutout runs directly into the cutout area (T), through which the maximum sum stored in the memory register (WM) is preset and then switched by one counting step during each scanning column Qc + 3, ...) and whose counting volume corresponds to the full counting volume (e.g. B. 26 bits) corresponding output is connected to the control input of an unlocking gate (Gnx), which is connected to the line leading from the scanning device to the detection device (n-nx-nx y) inserted delay memory (RR) is connected downstream. 12. Circuit arrangement according to claim 11, characterized in that the storage input of the memory register (WM) is connected to the output of the adder (Add) and to the read output of the memory register (WM) one input of one with its other input also to the output of Adder (Add) connected comparator (Vgl) is connected, the occurrence of a sum greater than the sum stored in each case in the storage register (WM) at the adder output a signal leading output line (gr) leads to the signal input of a blocking gate (GOgr) , which with its blocking input to a line (sgf) carrying a blocking signal (1 ) and a second blocking input to which the line (s) carrying the scanning signal elements (0) is connected to a scanning column Qc ) which does not overflow any characters within the section (F) and on the output side via a control line (g) the Einspeicherang at the output of the Addi erwerkes (Add) pending larger sum in the memory register (WM) controls. 13. Circuit arrangement according to claim 12, characterized in that a further blocking gate (Gl) with a blocking input to a scanning column Qc which overflows no characters after determining the first within the section (F), a blocking signal (1) leading line (gf, sgf) and with its signal input to the Scanning signal elements (1) leading line (s) is connected and on the output side via a control line (m ) controls the deletion of a sum stored in the storage register (WM) while resetting the storage register (WM). 14. Circuit arrangement according to claim 13, characterized in that the memory register (WM) is reset to a predetermined minimum sum (z. B. 15 bits). 15. Circuit arrangement according to one of claims 11 to 14, characterized in that the memory register (WM) has a shift output (wm) at which, after determining a section (F) overflowing the first scanning column (k), which is behind one at the front Segment boundary runs directly into the segment environment (T) , a number of control pulses corresponding to the sum of scanning signal elements (0) stored in the memory register (WM) occurs, which are sent to the counting input of the counter (Zxza) via the one input of an OR gate ( OGzx) , at the other input of which a counting pulse then occurs at the beginning of a scanning column. 16. Circuit arrangement according to claim 15, characterized in that the storage register (WM) is formed by a number of binary storage elements (2 ° ... 2 ⁴ ), each having a storage input controlled via a control line (g) and a storage input via a further control line (m) controlled reset input as well as a shift input connected to the output of the respective adjacent storage element, which is controlled via a control line (s) on which, if necessary, a number of shift pulses corresponding to the number of storage elements (2 ° ... 2 ⁴⁾ a series of intervening pulse pauses of the series of valences 2 ° ... 2 ^{l of} the individual storage elements of the corresponding duration occurs. 17. Circuit arrangement according to claims 12 and 13 and claim 15 or 16 for performing the method according to claim 4, characterized in that the control input to said blocking gate (C Ogr) and the reset input of a 1- bit memory (SOgr) is connected, the output of which leads to one input of a line (sgf) and a signal (1) with its second input to the scanning column (k) which does not overflow within the section (F) after the first scanning column (F) has been determined with its third input leads to an AND gate (GZa) connected to a line (1) leading to a signal element (1) at the beginning of a scanning column, which is followed by a memory (LA) , with its output control inputs of two of the two inputs of the OR Gatters (OGzx) upstream gates (Gwm, Gsp) are connected (Fig. 2). 18. Circuit arrangement according to claim 17, characterized in that the memory (LA) is connected to the control input of a further memory (LAZ3) via a gate (G 23) capable of transmission at the beginning of a scanning column, the output of which is also only connected at the beginning of a Scanning column transferable gate (G 34) is connected to the reset input of this further memory (LAZ 3) and also to the signal input of the gate inserted between the shift output (wm) of the memory register (WM) and the one input of the OR gate (OGzx) ( Gwm) and to the blocking input of the gate (Gsp) connected upstream of the other input of the OR gate (OGzx) , the control input of which is connected to the line (Sp) leading to a signal element (1) at the beginning of a scanning column. 19. Circuit arrangement according to claim 18, characterized in that an additional memory (LAZl) is connected to the memory (LA), the reset input of which is connected to the memory output via a gate (GrIa) capable of transmission at the beginning of a scanning column, to the output of which a Entriegelungseingang of said other input of the OR gate (OGzx) upstream gate (Gsp) and optionally the one input of its other input to the corresponding the full counting volume count output of the counter (Zxza) downstream aND gate (Gxza) is connected. 20. Circuit arrangement according to claim 18 or 19 for performing the method according to claim 6, characterized in that the one input of an AND gate (Glaz) is connected directly to the output of the memory (LA) , the other input of which is connected to a respective one after determining the rear limit of a character, a signal (1) carrying line (gz), and the right to the control input of the connected with its reset input to the output of the counter (Zxza) additional memory (LAZl) and a latch (LAZ 2) leads to the gate (G 23) connected upstream of the further memory (LAZ3) , to whose output the reset input of the intermediate memory (LAZ 2) is also connected. 21. Circuit arrangement according to one of claims 11 to 20, characterized in that the control input of the unlocking gate (Gnx) is connected to the output line (xz) of a 1-bit memory (XZ) , the input side with the output corresponding to the full counting volume Counter (Zxza) is connected. 22. Circuit arrangement according to claim 21, characterized in that the connection runs via one input of an OR gate (OGxz) , to the other input of which an AND gate (Gxzf) which can be transmitted at the beginning of a scanning column and which leads to the output of a memory (DT) is connected, leads to the control input of a gate (GIFZ), · for each to determine the rear limit of a not immediately transitioning to the front cutout limit in the cutout area (T) character, the coincidence condition is fulfilled. 23. Circuit arrangement according to one of claims 11 to 22 for performing the method according to claim 2, characterized in that in a delay memory (RR) which has the scanning signal elements of a number of Able to store scanning columns, which the maximum character width (z. B. 24 bits) by the number of scanning columns (e.g. k ... k +2) exceeds the counting volume (e.g. 27 bits) of the counter {Zxza) compared to a counting volume (e.g. 26 bits) that is the highest possible for a character that merges directly into the cutout area (Γ) at the front edge of the cutout in the memory register (WM) to be stored sum (z. B. 25 bits) of scanning signal elements (0) is at least 1 bit larger. 24. Circuit arrangement according to one of claims 11 to 23 for performing the method according to claim 8, characterized by a line-individually formed sum of only for those scanning signal elements (0) which differ from the maximum sum stored in the storage register (WM) at most within predetermined limits Scanning signal elements (0) lead, transmittable gate (GOwn) and a coincidence gate (G Owmf) connected downstream of it with its one input, the other input of which is connected to a line (gyf) leading the position of the section (F) indicating position signal elements, through a blocking gate (Goa) and an AND gate (Gof), of which the blocking gate (Goa) with its blocking input directly to the output of the coincidence gate (GOwmf) and with its other input via a differentiating element which only emits an output signal in the event of a 0-1 signal transition (DTF) to the line (gyf) leading the position signal elements and the AND gate (Gof) with sei One input is connected directly to this line (gyf) and its other input is connected to the coincidence gate (GO wmf) via a differentiating element (DWS) that only emits an output signal in the event of a 1-0 signal transition, and each of which has a 1-bit buffer (Soa or Sof) is connected downstream, and by three further AND gates (Gloz, GIz, Gluz), of which the first (Gloz) is connected to the coincidence gate (GOwmf) and the 1-bit buffer memory connected downstream of the blocking gate (Goa) (Soa), the second (GIz) also to the coincidence gate (GO wmf) and the 1-bit buffer (Sof) connected downstream of the AND gate (Gof ) and the third (Gluz) also to this 1-bit buffer ( Sof) and via a differentiating element (DFT) which only emits an output signal in the event of a 1-0 signal transition, to which the line (gyf) carrying the position signal elements is connected and which each lead to an input of an OR gate (OGz) , the activation of which is achieved the rear limit of a at the front edge of the cutout immediately into the cutout area (T) (F i g. 3). 25. Circuit arrangement according to claim 24, characterized in that the gate (Gowm) with a Entriegelungseingang to one of a same or opposite of the data stored in the memory register (WM) sum larger amount at the Addierwerkausgang a signal element (1) leading in the event output line (gl, gr ) of the comparator (Cf) and having a blocking input to a the Abtastsignalelemente (0) carrying line (n-l) is connected and lgf with a third control input connected to a line (2), which only after determination of the first within the cutout ( F) no character overflowing scanning column (k ) carries a control signal (1) for the duration of a scanning column (k + 1). 26. Circuit arrangement according to claim 25 for performing the method according to claim 10, characterized in that one input of an AND gate is connected to said line (lgf 2) , the other input of which is connected to the line (gyf) carrying the position signals and which leads to the additional addition inputs (z) of the adder (Add) . 27. Circuit arrangement according to one of claims 24 to 26, characterized in that a further AND gate (Gz) leads to a further input of the OR gate (OGz) , one input of which is connected to the output of a WEDER- NOCH gate (GpOO) is connected, to which the scanning signal elements as well as the projection signal elements corresponding to their position within a scanning column are fed step-by-step to one input each, as well as a blocking gate (GpIO) that is also provided, and that via a buffer (Sp 00) to the one input of an AND gate (GpOOlO) leads, the other input of which is connected to the output of the blocking gate (Sp 10) and which in turn via a 1-bit buffer (Sp 0010) to the other input of the said further AND gate ( Gz) leads. 28. Circuit arrangement according to one of claims 24 to 27, characterized in that one input of an additional AND gate (GZ) is connected to the OR gate (OGz) , the other input of which is connected to the output of a bistable multivibrator (5p 10 ), which is controlled by a counter (Zp 10) connected to the output of an OR gate (OGpIO) connected to the said 1-bit buffers (Soa, Sof, SpOOlO), the bistable multivibrator (5p 10) with its control input is connected to one of the minimum height of a character corresponding predetermined counting stage and with its reset input to one of the maximum height of a character corresponding predetermined counting stage of the counter (Zp 10). 29. Circuit arrangement according to one of claims 24 to 28, characterized in that a per se known counting device (Vz, ZSz, RZz, ZSZ, RZZ) is provided for counting the activations of the 1-bit buffer (Soa, Sof, Sp 0010), in which the counting steps reached in each case at the moment of activation of the additional AND gate (GZ) are marked and that the counting device then sends a signal (1) to one input of a counter signal when such a marked counting step is supplied again when such a marked counting step is reached another AND gate (Gze) whose other input output with the output of a delay register (Rz) the length of a scanning column, which is connected on the input side to the OR gate (OGpIO) connected downstream of the 1-bit buffer (Soa, Sof, Sp 0010) and at its output ( ze) so that an end-of-character signal indicating the reaching of the rear boundary of a scanned character and at the same time its position occurs. ίο 30. Circuit arrangement according to one of claims 24 to 29, characterized in that in the counting device (VZ, ZSZ, RZZ) the counting steps reached at the moment of activation of one of the further AND gates (Gloz, GIz, Gluz, Gz) are marked and that the counting device emits a signal (1) to one input of an AND gate (Gl) ao, the other input of which is connected to the output of a delay register (Rz) by the Length of a sampling column which is connected on the input side to the OR gate (OGpIO) connected downstream of the 1-bit buffers (Soa, Sof, Sp 0010) and which at its output (Z) indicates that the rear limit of the sampled is reached Character and at the same time its position indicating, to erase the projection of this character in a circulating register (Rp) usable erase signal (1) emits. 31. Circuit arrangement according to claim 29 or 30, characterized in that the additional AND gate (Gze) is followed by a circulating register (YZ) in which the end-of-character signal elements indicating the position of the character are stored synchronously with the scanning within the scanning columns and its output ( yz) is connected to the control input of a further unlocking gate (Gnxy) connected downstream of the delay memory (RR). 32. Circuit arrangement according to one of claims 12 to 31, characterized in that a device (FY) for determining the position of the section (F) of the recording medium (T) contrasting with its surroundings is provided, which means with or after determining the first within the section (F) no character overflowing scanning column (k) has a signal (1) leading line (gf, sgf) and the line (gyf) leading the position signal elements as output lines and which ones a) for each raster line (m-l, ...) the scanning signal elements (1) resulting from directly adjacent black surface elements (h-l, m- 1) are added in an adder (Add) and the sums obtained in the raster lines (m —L, ...) stores assigned memory locations (Z1S, Z2S ... ZZS) of a memory (ZS) , b) deletes the sum contained in a line memory (ZlS, Z2S ... ZZS) when a scanning signal element (0) originating from a white surface element of the relevant raster line (m-1, ...) occurs, c) by means of a comparison circuit (LSZ) the exceeding of a predetermined minimum amount, z. B. 25, determined in such a line memory (Z 15, ZlS. .. ZZS) and d) determines the position of the section (F) and, if necessary, records it by means of a circular register (YF) the length of a scanning column if the above-mentioned minimum sum has been exceeded in a scanning column (k) and after a white section (k) following in this scanning column (k) , m; ... ; k, p— 1) this minimum sum is exceeded again in a subsequent grid line (ρ). 33. Circuit arrangement according to claim 32, characterized in that in the device (FY) for determining the position of the section (F) of the recording medium (T) which contrasts with its surroundings a) the number of white sections is counted in each sample column (k), b) in each case the counting step is marked which is reached when the above-mentioned minimum sum has been exceeded in a scanning column (k) in a raster line (m-1) and, after one immediately following in this scanning column (k) , a predetermined one . Minimum length, e.g. B. 17 bits, not falling below and a predetermined maximum length, z. B. 23 bits, not exceeding white portion (k, m; ...; k, p- 1) in an immediately adjoining raster line (ρ) this minimum sum is exceeded again and c) then, when the white sections of the relevant scanning column (k) are counted again when such a marked counting step is reached, the position of the section ( k, m; ... ; k, p- 1) for the duration of the scan along said white section (k, m; F) indicating position signal elements ("L") are output on the named line (gyf) and, if necessary, stored in the circulating register (YF). 34. Circuit arrangement according to claim 32 or 33, characterized by a memory (ZS) with a number of memory locations (ZlS ... ZZS) assigned to the length of a scanning column (k) corresponding to a row (m ), which are via a distribution device . (Fl, V 2) are connected one after the other synchronously to the scanning within a scanning column (k) with an adder (Add) , which adds the scanning signal elements (1) occurring in the course of a scanning column (k) to the respective memory location (Z 15. .. ZZS) added sum of scanning signal elements (1) and when a scanning signal element (0) occurs, the sum of scanning signal elements (1) stored in the associated memory location is deleted by a comparator circuit connected to the adder (Add) 609 609/166 (LSZ), on whose output line (Isz) an in each case when the specified minimum amount is exceeded, z. B. 25, a signal indicating this exceeding occurs through a stored sum, and through a coincidence gate (Gfo) which, on the input side, is connected to a line (ή) which successively leads the scanning signal elements generated in the column-by-column scanning and to the line (ή) synchronously with this, if necessary, the exceeding the said minimum sum indicating signal line (Isz) is connected that in each case at the moment of a simultaneous disappearance of the exceeding of the predetermined minimum sum indicating signal and the last scanning signal element (1) of a sequence of immediately successive scanning signal elements (1) the coincidence condition is met, and which on the output side leads via a buffer (Sfo) to one input of a further coincidence gate (GF) , which is connected to the two mentioned lines (n, Isz) with its further inputs in such a way that in each case at the moment of a simultaneous appearance a signal indicating that the predetermined minimum sum is exceeded and the last scanning signal element (0) of a sequence of immediately successive scanning signal elements (0) disappears, the coincidence condition can be met, and its activation enables scanning of the part of the part that is in contrast to its surroundings overflown by the relevant scanning column (k) Section (F) of the recording medium (T) . 35. Circuit arrangement according to claim 34, characterized in that memory (ZS) and the adder (Add) are formed by the features mentioned in claim 11 memory (ZS) and the product stated in claim same adder (Add). 36. Circuit arrangement according to claim 35, characterized in that an AND gate and a WEDER-NOR gate lead to the counting input (a) of the adder (Add) via an OR gate, the two inputs of which are synchronized with the sampling within one Sampling column the mutually corresponding sampling signal elements of two successive sampling columns are supplied. 37. Circuit arrangement according to one of claims 34 to 36, characterized in that the buffer (Sfo) on the output side leads directly to the counter input and via an inverter (NGf) to the reset input of a counter (Zf) , at the predetermined minimum length (17 bits ) The corresponding counter output is connected to the control input and to its counter output corresponding to the specified maximum length (23 bits) the reset input of a bistable trigger circuit (Sf), which is also connected to the inverter (NGf) , is connected, the output of which is connected to the aforementioned one input of the further coincidence gate (GF) is. 38. Circuit arrangement according to claim 37, characterized in that the counter ( Zf) is identical to the counter (ZpIO) mentioned in claim 28 and alternates between the OR gate (OGpIO) or the buffer (Sfo) from scanning column to scanning column Counting signals are supplied. 39. Circuit arrangement according to one of claims 34 to 38, characterized in that a per se known counting device (VZW, ZSW, RZW) is also provided for counting the sequences of directly adjacent scanning signal elements (0) occurring in each scanning column (k), in which the counting steps reached in each case at the moment of activation of the further coincidence gate (GF) are marked and which are then marked each time the scanning signal element sequences are fed in again when such a step is reached. Counting step emits a signal to one input of a blocking gate (GYF) , the blocking input of which is connected to the output of the delay register (R) connected to the line (s) leading to the scanning signal elements and which has the length of a scanning column and which is connected to it at its output (gyf) the position of the section (F) of the recording medium (T) in its part overflowed by the relevant scanning column (k) indicating position signal elements ("L"). 40. Circuit arrangement according to Claim 33 and 39, characterized in that the circulating register (FF) connected downstream of the blocking gate (GYF) , in which the position signal elements ("L") are stored synchronously with the scanning within the scanning columns, has a clear input at which each after a counting step reached in the course of counting the sequences of scanning signal elements (0) has been marked for the duration of a scanning column, an erasing signal for erasing a previously stored section position occurs. Considered publications:
German exposition No. 1151140,
349;
Documentation of the Belgian patent No. 637 372. In addition 4 sheets of drawings 609 609/166 8.66 © Bundesdruckerei Berlin