DE1170465B - íÀExclusive-Oderí gate with two inputs and its use in a half adder - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Boarding school Class: H 03 k

German class: 21 al -36/18

Number: 1170465

File number: N 22156 VIII a / 21 al

Filing date: September 29, 1962

Opening day: May 21, 1964

In Fig. 6 of British patent specification 773,962, an "all-OR" gate with two inputs, one output and two transistors of the same conductivity type (both PNP or both NPN transistors) has been described, one transistor having one input and the other transistor the other Input is assigned in such a way that the collector of each transistor is connected to the output, its emitter to the input terminal assigned to it and its base to the input terminal not assigned to it. However, this "only-or" gate has the disadvantage that it only works satisfactorily if the two voltage levels of the two signals fed to the input terminals are exactly the same. Otherwise the output terminal supplies the correct output signal in the cases (x = y = 0), (x = 1, y = 0) and (x = 0, y - 1), but not in the case (x = y = 1). In the French patent specification 1,232,185, a means of avoiding this disadvantage has already been indicated. This means consists in that the emitter of each transistor is connected via a resistor to the input terminal assigned to the transistor in question and also via another resistor to a point of constant potential, the constant potential being chosen so that the output terminal in the case (x = y - 1) does not provide any output current, even if the voltages applied to the input terminals in this case are not exactly the same.

In the French patent specification 1 232 186 it was further described how the aforementioned "Exclusively I-Or" gate with two further transistors, which together form an "and" gate can, resulting in a circuit with two inputs and two outputs, the half adder can work.

The invention creates a further improvement which increases the speed of the "only-or" gate and, in the case of the combination with an "and" gate, enables the output current levels of the "only-or" gate and the "and" gate to be adjusted. To make Tors equal to each other. According to the invention, this purpose is achieved in that the emitter of each transistor is also connected via a diode to a point of constant potential, so that, like every transistor, each diode is assigned to an input, and that the potential of the point of constant potential is so it is selected that each diode changes from the conductive to the non-conductive state or vice versa, if the voltage of the assigned input has an "exclusive-or" gate with two inputs
and its application in a half adder

Applicant:

N.V. Philips' Gloeilampenfabrieken, Eindhoven

(Netherlands)

Representative:

Dr. H. Scholz, patent attorney,

Hamburg 1, Mönckebergstr. 7th

Named as inventor:

John Anthony Weaver, Crawley, Down, Sussex,

Dennis Brian Jarvis, Reigate, Surrey,

Raymond William Clarke,

Smallfield, Horley, Surrey (UK)

Claimed priority:

Great Britain from October 4, 1961,

dated August 3, 1962 (35 758),

dated October 31, 1961 (38 911),

dated December 11, 1961,

dated August 3, 1962 (44 233),

dated December 11, 1961,

dated August 14, 1962 (44 234) - ·

see the voltages assigned to the two signal values located voltage exceeds.

The invention is explained in more detail below with reference to the drawing.

Fig. 1 shows the well-known "exclusively-or" - Gate;

F i g. Figures 2 and 3 show two examples of an "only-or" gate according to the invention;

F i g. Figure 4 shows a half adder with an "all-or" gate according to the invention.

1 shows the improvement described in French patent specification 232 185 of the "only-or" gate described in British patent specification 773 962. The circuit has two inputs 3 and 4, to which signals are fed which are identified with the variables χ and y , and an output 5 at which_sich_ results in a signal which is identified with the Boolean function xy + Icy . The signals χ and y are both bivalent; the value 0 is identified with earth potential, the value 1 with a positive voltage. The output signal is the same

409 590/409

if two-valued: the value 0 is identified with the absence, the value 1 with the occurrence of a current. The circuit contains two pnp transistors 1 and 2, the first of which is assigned to the input terminal 3 and the second to the input terminal 4, and also four resistors r _v r ₂ , r ₃ and r ₄ . The collectors of the transistors are connected to the output terminal 5. The emitter of the transistor 1 is connected to the input terminal 3 via the resistor r _t

has an accelerating effect. The changes in the currents in the outer circles can even be made practically equal to zero by connecting each of the two diodes 7 and 8 in series with an expediently dimensioned resistor. As a result, the resistances r ₃ and λ ₄ are even superfluous and can be infinitely large (that is, they can be omitted).

Instead of using diodes with a

and a terminal 6 can also be connected to the diodes via the resistor r ₃ with the additional voltage threshold, which in the illustrated case provides a slight bias in the reverse direction and is grounded. The base of the transistor 1 is without resistance as in FIG. 3 is shown. The diodes 7 and 8 are connected to the input terminal 4. In this circuit via resistors r ₅ or r _e with the emitter of transistor 2 is via resistor r. _{2 connected to} an additional terminal 9, which is connected to a voltage source with the voltage + V via the input terminal 4 and via the resistor 15. Also r, connected to the additional terminal 6. The resistors r ₃ and r _{i can be} omitted here. The base of the transistor 2 is without a resistor and, by the way, the circuit according to FIG. 2 Ver input terminal 3 connected. find application, where the preload in the

If the variables χ and y both have the value 0, reverse direction of the diodes 7 and 8 to the additional, the variable xy + xy also has the value 0. ao terminal 6 is applied. In this case, the diodes, which in this case receive the input terminals 3 and 4, do not have a voltage threshold, which means that the two transistors need to be non-conductive in series and the output terminal 5 is connected to a resistor, and in the latter case does not supply any output current. If χ - 1 and y = 0, then the resistors r ₃ and r _{4 can be} omitted is xy ± xy = 1. In this case the input 35 is obtained.

terminal 3 a positive voltage and the input The circuits according to FIGS. 2 and 3 can

terminal 4 earth potential, whereby the transistor 1
conductive and transistor 2 is non-conductive. The output terminal 5 now supplies an output current. Even if χ = 0 and y - 1, xy + xy = 1.
In this case, the transistor 1 is non-conductive and
the transistor 2 conductive, so that the output terminal 5 now also has an output current
supplies. If χ = y = 1, the transistors are 1
and 2 both non-conductive because both are based on 35
of the combinations effective as voltage dividers
of resistors r _v r ₃ and r ₂ , r _{4 has} a positive voltage with respect to the emitter. This is also
then still the case when the voltage levels of the
two terminals 10 and 11 which coincide 40 connected to the input terminals 3 and 4, signals are not exactly the same or if the cons are at a voltage source with the voltage + V

lie. The output terminal 5 supplies a signal identified with the sum figure ζ = xy + xy and the output terminal 12 a signal identified with the carry c = xy 45. The voltages V and V and the resistances r _v r ₂ ... r _e must be dimensioned so that the transistors 13 and 14 are conductive only when χ - y = 1, while further it can be ensured that of the clamps are bridged. However, these diodes must have a 50 men 3 and 4 supplied currents in this case voltage threshold, so that each diode consists of half the resistors r ₃ and r ₅ or r ₄ and r _{e of} a silicon diode, two germanium diodes in and the other half Transistor 13 or 14 series, a silicon diode in series with a Ger- flows through. This has the advantage that for the ausmanium diode or two silicon diodes in series input signals, the current levels can be practically the same, depending on the required or some of the input signals. That all this desired voltage threshold. The diodes can be seen as follows. If the purpose is to prevent the emitter of the tran- χ = ν = 0, there is an undesired and 4 earth potential at both input terminals 3 sistors in the non-conductive state, so that none of the four tranhigh voltage. The fact that the transistor is conductive. None of the output terminals 5 voltages of the emitters of the transistors 1 and 2 60 and 12 now supplies an output current, which must be kept low under all circumstances corresponds to the fact that for these values of χ and y an accelerating effect on the effect of the variables z - ~ xy + xy and c = xy both that of the »exclusively-odera gate, because any scatter values have 0. If χ - 1 and y = 0, there is a capacitance as a result of a lower voltage at input terminal 3, a positive voltage and voltage and a smaller charge. 65 at input terminal 4 earth potential. The Tran-Also now occur minor changes in the transistor 2, 13 and 14 are now non-conductive, and the currents in the outer circles on, what with reverse transistor 1 is conductive. With regard to the transistors 1, see any leakage inductances also a 2 and 14, this is readily apparent. Because the oil

expediently on the from F i g. 2 of the French patent specification 1 232 186 known manner can be supplemented by two further transistors, which together 30 form an "and" gate. This results in a half adder. F i g. 4 shows the circuit diagram of such a half adder. Except for the "exclusive or" gate, which consists of transistors 1 and 2, diodes 7 and 8, and the six resistors r _v r ₂ . . . r _e consists, the circuit contains two further transistors 13 and 14. The emitters of these transistors are connected to the emitters of transistors 1 and 2, their collectors with a second output terminal 12 and their bases with two if necessary

states r _v r ₂ and r _v r _{i are} not exactly the same in pairs. In this case, the output terminal 5 does not supply any output current, which is completely in line with the fact that xy + xy - 0 is now.

F i g. 2 shows a first embodiment of the invention. The difference compared to the circuit arrangement according to FIG. 1 is that the resistors r, and r, through the diodes 7 and 8, respectively

sistor 1 is conductive, its emitter has practically the voltage of the base, ie earth potential. As a result, there is practically ground potential at the emitter of transistor 13 and this transistor is therefore also non-conductive. The diode 7 is also non-conductive in this case, and the same applies, of course, to the diode 8. The current supplied to the input terminal 3 thus flows almost completely via the transistor 1 to the output terminal 5, which in this case is the only current-supplying output terminal, which is completely corresponds to the fact that in this case ζ - xy + xy = 1 and c = xy = 0. When χ = y = 1, input terminals 3 and 4 both receive a high voltage and diodes 7 and 8 are both conductive, but transistors 1 and 2 are both non-conductive, the latter for the reason discussed above. As a result, the voltages of the emitters of transistors 13 and 14 rise to above the voltage + V (which must therefore not be too high), as a result of which transistors 13 and 14 both become conductive. By appropriate dimensioning it can be achieved that half of the currents supplied to the input terminals 3 and 4 in this case flow through the transistor 13 or 14 and the other half through the diode 7 or 8. In this case, only the input terminal 12 thus supplies an output current which, when appropriately rated, is equal to the currents supplied to each of the input terminals 3 and 4. This is entirely consistent with the fact that now z = xy + xy = 0 and c = xy - 1.

Claims (5)

Patent claims: 1. »Exclusively Odere Gate with two entrances, one output and two transistors of the same conductivity type (either both of the pnp type or both of the npn type), one of which is an input and the other is the is assigned to another input, in such a way that for each transistor the collector with the output, the emitter via a resistor with the input terminal assigned to the respective transistor and via another resistor with a point of constant potential and the base with the not associated with the transistor in question Input terminal is connected, characterized in that the emitter each transistor is also connected to a point of constant potential through a diode is, so that, like every transistor, every diode is assigned to an input, and that the Potential of the point of constant potential is chosen so that each diode from the conductive to the transitions to the non-conductive state or vice versa when the voltage of the associated input exceeds a voltage between the two signal values assigned to voltages. 2. “Exclusively-orÄ-gate according to claim 1, characterized in that the diodes have a voltage threshold. 3. »Exclusively Odere gate according to claim 1 or 2, characterized in that each diode is connected in series with a resistor is. 4. Half adder with an "exclusively-or" gate according to claim 1, 2 or 3, thereby characterized in that the emitter of each of the two transistors with the emitter of another Transistor is connected, the collectors of these two further transistors with one second output terminal and the bases with for connection to a source of positive voltage certain additional terminal are connected. 5. Half adder according to claim 4, characterized in that the resistors are chosen are that the current levels of the output signals are practically equal to those of the input signals are. 1 sheet of drawings 409 590/409 5.64 © Bundesdruckerei Berlin