DE112022003363T5 - DYNAMIC ALLOCATION OF CACHE MEMORY AS RAM - Google Patents

Abstract

A device includes a cache control circuit and a cache memory circuit further including a cache memory having a plurality of cache lines. The cache control circuit may be configured to receive a request to reposition a portion of the cache memory circuit that is currently in use. This request may identify an address range corresponding to one or more of the cache lines. The cache control circuit may be further configured, in response to the request, to convert the one or more cache lines to the directly addressable random access memory (RAM) by excluding the one or more cache lines from cache operations.

Description

BACKGROUND

TECHNICAL AREA

Embodiments described herein relate to systems-on-a-chip (SOCs), and more particularly to methods for operating a cache memory.

DESCRIPTION OF THE STATE OF THE ART

System-on-a-chip (SOC) integrated circuits (ICs) generally include one or more processors that serve as central processing units (CPUs) for a system, along with various other components, such as memory controllers and other agents. As used herein, an "agent" refers to a functional circuit capable of initiating or being a target for a transaction over a bus circuit. Accordingly, general purpose processors, graphics processors, network interfaces, memory controllers, and other similar circuits may be referred to as agents. As used herein, a "transaction" refers to an exchange of data between two agents over one or more bus circuits. Transactions by an agent to read data or store data from or to a memory circuit is a typical type of transaction and may involve large amounts of data. Memory circuits may use multiple clock cycles to access data within their memory cells.

Cache memories are commonly used in SoCs to support increased performance of processors by reducing delays associated with transactions on system memory and/or non-volatile storage memories. Cache memories can store local copies of information stored at frequently accessed memory addresses. These local copies can have shorter delays for accessing cached values compared to performing a memory access to a target memory address. When a memory access is made to a target address that is not currently cached, the addressed memory can be accessed and values from a plurality of sequential addresses, including the target address, are read as a group and can then be cached to reduce future access times. If the cached information in a cache line becomes invalid or it is determined that the cached information is not frequently accessed, the cached information may be invalidated and marked for unlock, allowing it to be overwritten by other information accessed by the SoC's processors.

BRIEF DESCRIPTION

In one embodiment, a device includes a cache control circuit and a cache memory circuit further including a cache memory having a plurality of cache lines. The cache control circuit may be configured to receive a request to reposition a portion of the cache memory circuit that is currently in use. This request may identify an address range corresponding to one or more of the cache lines. The cache control circuit may also be configured to, in response to the request, convert the one or more cache lines to directly addressable random access memory (RAM) by excluding the one or more cache lines from cache operations.

In another example, the cache control circuitry may be further configured to support a real-time virtual channel for memory transactions in the identified address range and to prioritize a memory transaction received over the real-time virtual channel over a memory transaction received over a volume virtual channel. In an example, the cache control circuitry may be further configured to determine that the address range is included in a secure access range. In response to the determination, the cache control circuitry may be further configured to ignore a memory transaction in the address range from an agent that is not authorized to access the secure access range.

In another example, the cache control circuitry may also be configured to flush the one or more cache lines prior to conversion to the directly addressable RAM. In an example, the cache control circuitry may be further configured to issue a writeback request for the valid cache line in response to data being written to a valid cache line. The cache control circuitry may also be configured to exclude the one or more cache lines from writeback requests.

In one embodiment, the cache control circuitry may be further configured to receive a different request to allocate the portion of cache memory from the directly addressable RAM. In response to the different request, the cache control circuitry may be further configured to include the one or more cache lines in cache operations without copying data stored in the directly addressable RAM while the one or more cache lines are being reallocated. In another embodiment, the cache control circuitry may also be configured to generate a fault in response to a memory transaction in the directly addressable RAM received after allocating the portion of cache memory.

BRIEF DESCRIPTION OF THE DRAWINGS

• 1 veranschaulicht zu zwei Zeitpunkten ein Blockdiagramm einer Ausführungsform eines Systems, das einen Cache-Speicher und eine Adresskarte einschließt.
• 2 zeigt ein Blockdiagramm einer Ausführungsform eines Systems, das einen Prozessor, einen Cache-Speicher mit einer Vielzahl von Wegen und eine Adresskarte einschließt.
• 3 stellt ein Blockdiagramm einer Ausführungsform des Systems von 1 zu zwei unterschiedlichen Zeitpunkten dar.
• 4 veranschaulicht ein Blockdiagramm einer Ausführungsform des Systems von 1, das zwei Schreibanforderungen empfängt.
• 5 zeigt ein Blockdiagramm einer Ausführungsform eines Systems, das zwei Agenten einschließt, die Speichertransaktionen über einen Netzwerk-Arbiter an einen Cache-Speicher senden.
• 6 veranschaulicht ein Blockdiagramm einer Ausführungsform eines Systems, das zwei Agenten, einen vertrauenswürdigen und einen nicht vertrauenswürdigen, einschließt, die Speichertransaktionen an einen Cache-Speicher senden.
• 7 zeigt ein Flussdiagramm einer Ausführungsform eines Verfahrens zum erneuten Zuweisen eines Abschnitts eines Cache-Speichersystems an einen direkt adressierbaren Adressbereich.
• 8 stellt ein Flussdiagramm einer Ausführungsform eines Verfahrens zum Empfangen einer Speichertransaktion von einem nicht autorisierten Agenten und zum Abweisen eines Abschnitts eines Cache-Speichersystems von einem direkt adressierbaren Adressbereich dar.
• 9 veranschaulicht zu zwei Zeitpunkten ein Blockdiagramm einer Ausführungsform eines Systems, in dem ein in einem Systemspeicher befindlicher Puffer einem Cache-Speicher zugewiesen ist.
• 10 zeigt zu zwei unterschiedlichen Zeitpunkten ein Blockdiagramm einer Ausführungsform des Systems von 9, bei dem ein Versuch, einen Speicherplatz einem Cache-Speicher zuzuweisen, wiederholt wird.
• 11 stellt ein Blockdiagramm einer Ausführungsform eines Systems dar, das einen Prozessorkern und einen DMA einschließt, der einen Puffer einem Cache-Speicher zuweist.
• 12 veranschaulicht zu zwei verschiedenen Zeitpunkten ein Blockdiagramm einer Ausführungsform des Systems von 9, bei dem Volumentransaktionen und Echtzeittransaktionen in Verbindung mit einem Puffer und einem Cache-Speicher verwendet werden.
• 13 zeigt ein Flussdiagramm einer Ausführungsform eines Verfahrens zum Zuweisen eines Puffers zu einem Cache-Speichersystem.
• 14 stellt ein Flussdiagramm einer Ausführungsform eines Verfahrens zum Verwenden von Volumentransaktionen und Echtzeittransaktionen in Verbindung mit einem Puffer und einem Cache-Speicher dar.
• 15 veranschaulicht ein Flussdiagramm einer Ausführungsform eines Verfahrens zum Bestimmen einer Cache-Fehlrate beim Zugreifen auf einen Puffer, der einem Cache-Speicher zugewiesen ist.
• 16 zeigt verschiedene Ausführungsformen von Systemen, die gekoppelte integrierte Schaltungen einschließen.
• 17 stellt ein Blockdiagramm eines beispielhaften computerlesbaren Mediums gemäß einigen Ausführungsformen dar.

The following detailed description refers to the accompanying drawings, which are now briefly described.

• 1 illustrates, at two points in time, a block diagram of one embodiment of a system that includes a cache memory and an address map.
• 2 shows a block diagram of one embodiment of a system that includes a processor, a cache memory with a plurality of ways, and an address map.
• 3 is a block diagram of an embodiment of the system of 1 at two different points in time.
• 4 illustrates a block diagram of an embodiment of the system of 1 that receives two write requests.
• 5 shows a block diagram of an embodiment of a system that includes two agents that send memory transactions to a cache memory via a network arbiter.
• 6 illustrates a block diagram of an embodiment of a system that includes two agents, one trusted and one untrusted, that send memory transactions to a cache.
• 7 shows a flowchart of an embodiment of a method for reallocating a portion of a cache memory system to a directly addressable address range.
• 8th illustrates a flow diagram of one embodiment of a method for receiving a memory transaction from an unauthorized agent and rejecting a portion of a cache memory system from a directly addressable address range.
• 9 illustrates, at two points in time, a block diagram of an embodiment of a system in which a buffer located in a system memory is mapped to a cache memory.
• 10 shows at two different times a block diagram of an embodiment of the system of 9 , in which an attempt to allocate a memory location to a cache memory is repeated.
• 11 illustrates a block diagram of one embodiment of a system including a processor core and a DMA that maps a buffer to a cache memory.
• 12 illustrates, at two different times, a block diagram of an embodiment of the system of 9 , which uses volume transactions and real-time transactions in conjunction with a buffer and a cache memory.
• 13 shows a flowchart of an embodiment of a method for allocating a buffer to a cache memory system.
• 14 illustrates a flow diagram of one embodiment of a method for using volume transactions and real-time transactions in conjunction with a buffer and a cache memory.
• 15 illustrates a flowchart of an embodiment of a method for determining a cache miss rate when accessing a buffer allocated to a cache memory.
• 16 shows various embodiments of systems including coupled integrated circuits.
• 17 illustrates a block diagram of an example computer-readable medium, in accordance with some embodiments.

While embodiments described in this disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and are described in detail herein. It is to be understood, however, that the drawings and detailed description thereof are not intended to limit embodiments of the particular form disclosed, but on the contrary, all modifications, equivalents, and alternatives that may be included within the spirit and scope of the appended claims.

DETAILED DESCRIPTION OF EMBODIMENTS

Transactions can be classified into two or more priority levels, such as "real-time" and "volume". A real-time transaction may have a higher priority level than a volume transaction and can therefore be processed more quickly by the bus circuits and any intermediate agents through which the real-time transaction passes. Agents can use real-time transactions to meet deadlines for completion of processing, failure to meet which can result in poor performance, incorrect calculations, or even system failure. For example, the playback of a video may stall or be corrupted if low-latency deadlines are missed. Competition from other agents for access to bus circuits and memory circuits is one source of complicating such low-latency deadlines.

Caches can be used to mitigate some of the complications of meeting low-latency deadlines by storing copies of memory locations closer to a corresponding agent, thereby reducing a number of bus circuits and/or intermediate agents that a real-time transaction must traverse when processing. Furthermore, when a plurality of caches are available, a given cache may be accessed by fewer agents, thereby increasing a probability that an agent can access the cache while meeting low-latency deadlines. However, cached values may be released from a cache if they are not frequently accessed and/or if there is contention from other agents to cache values in the cache.

Accordingly, techniques for using caches to store values used and/or utilized for real-time transactions are desired. Two general approaches for using caches to implement a faster access memory region are presented herein. In a first approach, a portion of cache memory may be mapped to a system bus accessible address range, where the addressable cache memory may be accessed in a manner similar to random access memory (RAM). To implement such a technique, a control circuit may be used to map a portion of cache memory as RAM. Cache lines in the mapped portion of cache memory are flushed, and any dirty data (e.g., data modified in cache memory without updating corresponding locations in system memory) is written back to system memory. The cache lines in the mapped portion are enabled for access via a memory mapped address range and are removed from the available cache lines. Agents may then be able to directly access the address space mapped to memory with real-time transactions that can be processed in a similar amount of time as a cached location. Because the address space mapped to memory is not treated as part of the cache during allocation, values stored in this space are not at risk if they cannot be accessed for an extended period of time. 1 to 8 , described below, illustrate various details for this cache-as-RAM approach.

In a second approach, a buffer is allocated within system memory, where the buffer is designated for use with low-latency memory transactions. To reduce the latency of accessing values in this buffer, the buffer may also be allocated in cache memory. In some embodiments, a cache may include support for high priority data, including techniques for associating a particular cache line with low-latency transactions. Such support may include limiting or eliminating deals for the associated cache lines. However, cache allocation of a large buffer (e.g., a buffer sized for use with a video frame, another image, an audio file, etc.) may begin to suffer cache misses because portions of the buffer allocated toward the end of the cache allocation process have a higher probability of being allocated to cache lines that are now occupied by portions of the buffer that were previously cached. When cache allocation begins with one end of the buffer, the opposite end suffers a higher number of cache misses, increasing cache misses as accesses to the buffer are shifted toward the last sections to be allocated.

The disclosed techniques attempt to distribute the cache allocation of portions of the buffer across different locations in the buffer. To achieve this, the buffer may be logically divided into a A cache can be divided into a plurality of blocks. An attempt can then be made to allocate a first sub-block from each block into the cache. Subsequent attempts can then be made to allocate a second sub-block from each block into the cache. This can be repeated for a number of sub-blocks in each block until an attempt has been made to cache all of the sub-blocks. Such a technique can spread cache misses for different sub-block allocations across an entire buffer so that the misses do not cluster toward one end of the buffer. For example, if the buffer is used to process an image, then cache misses can occur consistently, but with a lower concentration, across the processing of the entire image, rather than having a few misses at the beginning of processing the image and then having more frequent misses as processing approaches the end of the image. As misses occur more frequently, more real-time transactions can be generated to retrieve the requested data from system memory. Processing a larger number of real-time transactions simultaneously can increase the likelihood that low-latency deadlines will be missed, thereby increasing the likelihood of poor performance or system failure by a user of the system. 9 to 13 , described later in this disclosure, illustrate details regarding this distributed caching approach.

1 illustrates a block diagram of one embodiment of a cache memory system at two points in time. As illustrated, system 100 includes cache control circuitry 101, cache memory circuitry 105, and address map 110. Cache memory circuitry 105 includes cache lines 120-127. Address map 110 is shown with four address ranges 115a-115d (collectively, address ranges 115). System 100 may correspond to a processor circuit, such as a microprocessor, a microcontroller, or other form of system-on-chip (SoC). System 100 may be implemented on a single integrated circuit or by using multiple circuit elements coupled on a circuit board.

As illustrated, cache memory circuit 105 may be implemented using any suitable type of memory circuit design, such as static random access memory (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FeRAM or FRAM), magnetoresistive RAM (MRAM), flash memory, and the like. Cache memory circuit 105 may be organized using any suitable cache structure, including using multiple types and/or sets. Cache control circuit 101 includes circuitry for performing cache operations in cache memory circuit 105, such as maintaining cache tags, determining whether an address related to a memory transaction is a hit (a cache line currently corresponds to the address) or miss (no cache line has been filled with data corresponding to the address), issuing cache line fill requests in response to a miss, marking memory lines for enablement, and the like. Address map 110 includes any suitable combination of software, firmware, and hardware circuitry for determining a physical address for registers and memory circuitry associated with memory. In some embodiments, address map 110 includes translation tables for converting logical addresses to physical addresses.

As shown, cache control circuit 101 receives allocation request 145 at time t0. Cache control circuit 101 is configured to receive allocation request 145 to reallocate a portion of cache memory circuit 105 that is currently in use. Allocation request 145 identifies one of address ranges 115 (e.g., address range 115b) that corresponds to one or more of cache lines 120-127 (e.g., cache line 123). Cache control circuit 101 receives allocation request 145 at time t0 at which cache memory circuit 105 was in use, and one or more of cache lines 120-127 may be in use in cache locations in a system memory (not shown). Allocation request 145 may specify address region 115b by including an address value corresponding to address range 115b. In other embodiments, other forms of indication may be used to identify address range 115b, such as an index value corresponding to address range 115b.

Each of the address ranges 115, when active, may correspond to a plurality of addresses corresponding to memory locations in the cache memory circuit 105, such as one or more of cache lines 120 through 127. When a particular one of the address ranges 115 is active, the corresponding cache line(s) is/are not used to cache data, but rather is/are used as RAM. When an address range is inactive, the corresponding cache line(s) may be used to cache data values. Addresses associated with an inactive address range may be considered an illegal address. and can therefore generate an exception if they are included in a transaction. At time t0, address range 115b is not active (as determined by hashing in 1 indicated) and therefore no data values can be stored within the range. Address ranges 115c and 115d are also inactive, while address range 115a is currently active. In some embodiments, address range 115a may correspond to a main system memory and may include addresses for all memory locations and registers associated with the memory that are always enabled when system 100 is active.

In response to allocation request 145, cache control circuitry 101 may be further configured to convert cache line 123 to direct addressable memory (RAM) at time t1 by excluding cache line 123 from cache operations. Cache line 123 may then be directly addressed using memory transactions addressed to locations within address range 115b. For example, activating address region 115b may include modifying address map 110 so that transactions addressed to locations within address range 115b are directed to memory cells corresponding to cache line 123. Additionally, cache control circuitry 101 may further set an indication that cache line 123 is unavailable and that no cached data is currently stored in cache line 123. For example, cache control circuit 101 may set one or more bits in a cache tag corresponding to cache line 123 that provides such information.

Use of such a cache-to-RAM technique may allow a process executing in system 100 to allocate a portion of cache memory circuitry 105 for use as directly addressable RAM at any time the system is active. As previously described, such an allocation may allow a particular agent to reserve memory space with low latency access times for use with data related to high priority transactions, such as real-time transactions. Allocating this space in cache memory circuitry 105 may further prevent other agents from benefiting from use of the allocated portion until the particular agent has completed real-time transactions, and may relegate the portion for use as cache line 123.

It is pointed out that System E100, as in 1 illustrated is merely an example. The illustration of 1 has been simplified to emphasize features relevant to this disclosure. Various embodiments may include additional elements and/or a different configuration of the elements. For example, only eight cache lines and four address ranges are shown. Any suitable number of cache lines and address ranges may be implemented in other embodiments. Although address range 115b is shown as corresponding to a single cache line, in other embodiments the address range may correspond to any suitable number of cache lines as well as a portion of a cache line.

This in 1 The system illustrated is shown in a simplified representation. Cache memory systems can be implemented in various ways. Another example of a system with a cache memory is shown in 2 shown.

In 2 , a block diagram of one embodiment of a cache memory system employing the use of ways in a cache memory circuit is shown. System 200 includes, as illustrated, cache control circuit 201, cache memory circuit 205, address card 210, and processor 230. Processor 230 may correspond to a general processing core or other type of processing circuit capable of processing data and issuing memory requests. Except as described below, elements of system 200 perform functions as described for similarly named and numbered elements of 1 are described.

As shown, cache memory circuit 205 includes multiple way caches 240a-240d and a plurality of sets 250-257. Processor 230 is configured to issue memory requests using address map 210, which includes active and inactive address ranges 215. In the illustrated embodiment, address range 215m is always active when system 200 is active and may include addresses for main system memory as well as various registers. When processor 230 issues a memory request to system memory (e.g., an address in address range 215m), a fetch address included in the memory fetch is used by cache control circuit 201 to determine whether a cache line in cache memory circuit 205 currently holds valid values for the system memory locations corresponding to the fetch address. To make such a determination, cache control circuit 201 may use the fetch address to identify a particular one of sets 250 through 257. For example, cache control circuit 201 may use at least a portion of the fetch address in a hashing algorithm to determine a particular hash value. This hash value can then be used to identify a particular one of sets 250 through 257. Each of sets 250 through 257 includes at least one cache line from each of ways 240. If a cache line in one of ways 240 holds valid values for the particular set that correspond to the fetch address, then the store request to cache memory circuit 205 is a "hit." Otherwise, the store request to cache memory circuit 205 is a "miss." Using multiple ways can allow some flexibility by allowing cache control circuit 201 to map fetched values into cache lines of cache memory circuit 205.

As described above, cache memory circuitry 205 may provide low latency access, also referred to as a higher quality of service (QoS), and not access system memory, such as in address space 215m. Under certain conditions, processor 230 may be required to process a block of data with a high QoS deadline. Since processing data from system memory may jeopardize the successful processing of the data within the constraints of the high QoS deadline, processor 230 may send allocation request 245 to cache control circuitry 201 to request that a portion of cache memory circuitry 205 be reallocated.

Cache control circuitry 201, as shown, is configured to receive allocation request 245 from processor 230 to reallocate a portion of cache memory circuitry 205 as directly addressable memory. Allocation request 245 identifies address range 215b that is inactive at the time allocation request 245 is received. For example, allocation request 245 may include a particular address value or other type of indication that identifies address range 215b. Based on allocation request 245, cache control circuitry is further configured to select a portion of ways 240 to convert. As shown, each of ways 240 may correspond to one of address ranges 215, including, as indicated, way 240b that corresponds to address range 215b. In other embodiments, cache memory circuitry 205 may include additional ways so that two or more ways may be associated with a given address range. Allocation request 245 may also specify more than one address range, such as address ranges 215b and 215c. In some embodiments, the portion of ways 240 may be one half or another portion of a particular way. For example, 240b may include multiple cache lines in each of sets 250-257, such as two lines per set. In such embodiments, one of the two cache lines from each of sets 250-257 may be reallocated, leaving half of ways 240b for use as cache while the other half is reallocated to address range 215b.

To convert way 240b, cache control circuit 201 may be configured to set respective indications in cache tags corresponding to particular cache lines included in the selected portion of ways. Cache lines 250b through 257b are included in way 240b and are selected for reassignment to address range 215b as shown. By adding respective indications to cache tags for each of cache lines 250b through 257b, the corresponding cache line is removed from use as a cache. Such indications may cause cache control circuit 201 to ignore cache lines 250b through 257b when determining whether a received store request in cache circuit 205 is a hit or miss, and may further prevent cache control circuit 201 from mapping an address from a cache miss to any of cache lines 250b through 257b. Accordingly, cache lines 250b-257b are effectively removed from cache memory usage while these indications are placed in the cache tags. Cache control circuitry 201 is further configured to map cache lines 250b-257b in path 240b for use in the identified address range 215b. Address range 215b, as illustrated, includes a number of addresses that may be reserved for use with newly allocated cache lines 250b-257b and thus may not be mapped to other memory locations or registers. When address range 215b is inactive, an attempt to access these addresses may result in an exception being generated and/or a default return. Cache control circuitry 201 may be further configured to place respective real-time indicators in the cache tags corresponding to the particular cache lines 250b-257b. Such real-time indicators may indicate that cache lines 250b through 257b, and therefore addresses in the address range 215b, are allocated to real-time transactions with higher priorities than volume transactions. Accordingly, memory accesses to any of the newly allocated cache lines 250b through 257b may be treated as real-time transactions even if a real-time transaction is not explicitly used in the memory access.

In addition, cache control circuit 201 may be further configured to control one or flush several of the cache lines 250b through 257b in path 240b prior to mapping path 240b for use in address space 215b. Since cache memory circuitry 205 may be in use prior to processor 230 issuing allocation request 245, one or more of the cache lines in path 240b may be used to cache memory locations, such as locations in address space 215m. If currently cached values in the respective locations in address space 215m match, those values may simply be deleted or ignored when the respective cache line is mapped to address space 215b. However, if a value cached in path 240b has been modified but has not yet been written back to address space 215m, such a value may be designated as "dirty" and a flush command issued to write dirty values back to the system memory locations in address space 215m. For example, in the illustrated example, cache lines 251b, 254b, and 257b include dirty data. Cache control circuit 201 issues flush command 248 to write the dirty values in these cache lines back to the corresponding locations in address range 215m. One or more flush commands may be issued prior to converting the cache lines from path 240b to directly addressable locations in address range 215b.

After processing the data block with the high QoS deadline, processor 230 may have no immediate use for the high QoS directly addressable memory in address space 215b and may be configured to issue a request to reject way 240b. Cache control circuit 201 may be further configured to, in response to receiving the request to reject the directly addressable memory in address space 215b, include way 240b in cache operations. Values stored in the directly addressable memory while way 240b was being reallocated are not reallocated in response to the request to reject the directly addressable memory. Any values written to address space 215b during the reallocation may be deleted or ignored and subsequently overwritten as way 240b is returned for use in operations of cache memory circuit 205.

It is noted that using ways 240 of cache memory circuitry 205 to reallocate cache memory to directly addressable memory may be implemented with an acceptable amount of additional logic circuitry while allowing continued operation of cache memory circuitry 205 with little to no interruption. Implementing reallocation of cache memory on an individual cache line basis, on the other hand, may require the addition of larger logic circuitry, particularly when the cache memory is large and/or has many sets and ways. Further limiting an amount of cache memory that can be reallocated, on the other hand, may not provide adequate resolution to manage between the requirements for high QoS locations and ongoing cache operations. For example, if reallocation of cache memory circuitry 205 is limited to half of the cache, the amount of memory allocated may be much larger than required to handle the high QoS data, and may further reduce a capacity of the cache and potentially reduce an efficiency of agents utilizing the cache.

It is also noted that the embodiment of 2 is an illustration of a cache memory system. Although only four ways and eight sets are shown, in other embodiments, any suitable number of cache ways and sets may be included. Although five address ranges are shown, address map 210 may be divided into any suitable number of ranges.

The description of 2 described a rejection of directly addressable memory locations. The rejection of a directly addressable memory region back to the cache memory can be implemented in several ways. 3 shows such a way.

With reference to 3 the system is 1 again illustrated at two different points in time. System 100, as described with reference to 1 includes cache control circuit 101, cache memory circuit 105, and address map 110. At time t0, cache line 123 is mapped to directly addressable memory in address range 115b and is therefore unavailable for caching operations. As illustrated, cache control circuit 101 is configured to be accessed by, for example, an agent such as processor 230 in 2 Reject request 345 to reject cache line 123 from the directly addressable memory in address space 115b. In response to reject request 345, cache control circuit 101 is further configured to include cache line 123 in cache operations without copying data stored in the directly addressable memory while cache line 123 in address space 115b has been reallocated. For example, as described above, cache control circuit 101 may provide an indication in a set the associated cache tag for cache line 123 to indicate that cache line 123 has been remapped to directly addressable memory. To reject cache line 123, cache control circuit 101 may clear this indication, thereby removing cache line 123 from address range 115b and including cache line 123 in subsequent cache operations.

Values written to cache line 123 while assigned to address range 115b may be discarded or ignored when the specification in the associated cache tag is cleared. Because addresses in address range 115b may not be implemented elsewhere in address map 110, no writeback requests may be issued to copy these values. Unless an agent explicitly uses address range 115b while it is active, the data from address range 115b is copied to other locations in address map 110, the values in address range 115b may be lost when the rejection is complete.

At time t1, memory transaction 350 is issued by an agent to access a value in address range 115b. Cache control circuitry 101 is configured to generate an error message 355 in response to receiving memory transaction 350 after rejecting address range 115b. In some embodiments, error message 355 may be generated if memory transaction 350 includes a write or modification of an address in address range 115b. Otherwise, if memory transaction 350 only includes read accesses to address range 115b, cache control circuitry 101 may return a particular default value, such as all zero bits or all one bits, to the requesting agent instead of or in addition to generating an error message 355. Generating error message 355 may be implemented using a variety of techniques. For example, error message 355 may be generated by asserting an exception signal, which in turn causes a special process to be executed by one or more processor cores in system 100. Generating error message 355 may include returning a special value indicating to the agent that the issued memory transaction 350 that issued address region 115b was rejected.

3 represents the rejection of cache lines from a directly addressable address range. Continuing with 4 System 100 is shown with address space 115b active (using cache line 123) and illustrates how caching and access to address space 115b can be handled simultaneously. System 100 in 4 shows cache control circuit 101 receiving write requests 445 and 446.

As shown, write request 445 includes a write request to write data to one or more locations currently cached in cache line 121 of cache memory circuit 105. Similarly, write request 446 includes a write request to write data to one or more locations in address range 115b, which is implemented by remapping cache line 123 from cache memory circuit 105 to address map 110. Cache control circuit 101 is configured in response to write request 445 to issue a writeback request 447 for cache line 121. The modified values in cache line 121 are included in writeback request 447 along with corresponding destination addresses in system memory. Writeback request 447 causes these modified values to be updated at the destination addresses in system memory. If cache line 121 is freed and then mapped to different addresses in system memory, the target addresses in system memory may still have current values.

Cache control circuitry 101 is further configured, as illustrated, to exclude cache line 123 from write-back requests. Write request 446 may modify one or more values in address range 115b (including cache line 123). Despite the modification of the values in cache line 123, cache control circuitry 101 is configured to ignore these modifications with respect to the write-back commands. Address range 115b, although including cache line 123, is treated as an endpoint memory destination. No destination address in system memory corresponds to the addresses in address range 115b. Accordingly, modified values stored in cache line 123 may not be updated in another memory circuitry in response to write request 446.

However, it should be noted that a different cache may be located between cache memory circuit 105 and processing circuitry issuing write request 446. For example, cache memory circuit 105 may be an L2 cache and the processing circuitry issuing write request 446 may include an L1 cache. In such an embodiment, the L1 cache may cache at least some values stored in address range 115b (e.g., in cache line 123).

It is further pointed out that the embodiments of 3 and 4 are merely examples to illustrate disclosed concepts. The system 100 shown in these figures is simplified for clarity. In other embodiments, additional elements may be included, such as one or more agents that issue memory transactions that effect the described operations. Although 3 and 4 System 100 by 1 the techniques described can be used on System 200 from 2 be applied.

The use of real-time transactions is described above in various capacities as used in conjunction with the disclosed techniques. Both real-time and volume transactions may be used for memory requests directed to the cache-based address ranges described herein. 5 illustrates an example of how the use of transactions with different QoS levels can be implemented.

now to 5 5 shows a system in which arbiters are used to schedule transactions over a system network. System 500 includes cache control circuit 501 and address card 510, which are similar to 1 , 3 and 4 named and described, except as described below. System 500 further includes agents 530a and 530b (collectively, agents 530), network arbitration circuitry 540, and bus circuitry 545. 5 illustrates a flow of two memory transactions (memory transactions 550 and 555, which are a real-time transaction and a volume transaction, respectively) addressed to address range 515b, which is implemented using one or more cache lines from cache control circuit 501 using a technique as described above.

At a first time, agent 530b issues volume storage transaction 555 with a destination in address range 515b. Similar to address ranges 115b and 215b in 1 and 2 address range 515b includes a portion of cache memory associated with cache control circuit 501. As illustrated, memory transaction 555 is received by network arbiter circuit 540 on its way to cache control circuit 501. Since memory transaction 555 is a volume transaction, network arbiter circuit 540 places memory transaction 555 in volume queue 565a until bus circuit 545 has available bandwidth to forward memory transaction 555 to cache control circuit 501.

Bus circuit 545 includes a set of wires that couple cache control circuit 501 to network arbiter circuit 540. In some embodiments, bus circuit 545 may include a sufficient number of wires to support independent physical volume and real-time channels. However, as shown, bus circuit 545 does not include such a number of wires, and thus both real-time and volume storage transactions are transmitted using the same set of wires, utilizing virtual volume and real-time channels to support the respective QoS levels for each transaction type. Accordingly, network arbiter circuit 540 uses a prioritization scheme to select between real-time (RT) queue 560a and volume queue 565a for a next transaction sent over bus circuit 545. For example, network arbiter circuit 540 may send transactions in RT queue 560a first and then send transactions in volume queue 565a after RT queue 560a is empty. In other embodiments, additional considerations may be included in the selection process to avoid volume queue 565a reaching a full state or having a volume transaction stall in volume queue 565a for an excessive amount of time.

As used herein, a "channel" is a medium used to transmit information between a source agent (e.g., a processor circuit) and a destination agent (e.g., a memory circuit). A channel may include wires (including traces on a circuit board or integrated circuit) and various other circuit elements. In some embodiments, a channel may further include antennas and electromagnetic waves of a particular frequency or range of frequencies. A "physical" channel refers to the circuit elements that comprise a channel. A "virtual" channel refers to two or more different "channels" implemented over a same physical channel. Virtual channels may be implemented using a variety of techniques. For example, virtualization of a channel in a channel interface may be implemented by including respective queues for each virtual channel. An agent sends and receives transactions over a given channel using the queue for the respective channel. Other circuits may then control channel arbitration between the respective queues to select specific transactions to be sent when the channel is available. In other embodiments an agent may be responsible for assigning various transactions to appropriate virtual channels. In such embodiments, the agent may maintain appropriate data structures for assigning transactions to appropriate virtual channels and then arbitrate to select a given transaction to be sent when the channel is available.

At a second time, network arbiter circuit 540 selects memory transaction 555 from volume queue 565a and forwards it to cache control circuit 501. Cache control circuit 501 may in turn place memory transaction 555 in volume queue 565b until bandwidth is available to process memory transaction 555 in address space 515b. Meanwhile, at a third time after the second time, agent 530a sends memory transaction 550 to cache control circuit 501 via bus circuit 545. Network arbiter circuit 540 receives real-time memory transaction 550 and places it in RT queue 560a. At a subsequent fourth time, memory transaction 550 is selected by network arbiter circuit 540 and sent to cache control circuit 501, which places the received memory transaction 550 in RT queue 560b.

In the illustrated example, both memory transactions 550 and 555 are in RT queue 560b and volume queue 565b, respectively. Cache control circuitry 501 is configured to support the real-time and volume virtual channels for memory transactions in address ranges 515a through 515d. Accordingly, using a selection scheme similar to network arbiter circuitry 540, cache control circuitry 501 prioritizes memory transaction 550 received over the real-time virtual channel over memory transaction 550 received over the bulk virtual channel. At a fifth time, after the fourth time, cache control circuitry 501 skips memory transaction 555 waiting in volume queue 565b and instead selects memory transaction 550 waiting in RT queue 560b. Later, at a sixth time, memory transaction 555 meets the selection criteria and is processed in address range 515b.

It is noted that system 500 is an example to highlight disclosed concepts. 5 is simplified for clarity. In other embodiments, additional elements may be included, such as additional agents, multiple bus circuits, associated network arbiter circuits, and the like.

5 shows how memory transactions with different QoS levels can be handled using the disclosed techniques. The disclosed cache control circuitry can be further configured to manage address ranges that fall into different types of secure memory areas. A description of such an embodiment is presented next.

With reference to 6 , an embodiment of a system is shown that includes support for publicly accessible and secured memory areas. System 600 includes cache control circuitry 601, address map 610, system memory map 620, trusted agent 630, and untrusted agent 635. System memory map 620 is divided into two areas, as shown, the publicly accessible area 623 and the secured area 627. Address area 615b in address map 610 corresponds to a newly allocated cache memory, as described above, and is mapped within the secured access area 627. The trusted agent 630 and the untrusted agent 635 issue memory transactions 650 and 655, respectively, both targeting a destination address in address area 615b.

System memory map 620, as illustrated, includes a memory map of all address ranges included in system 600. These address ranges can be classified into two types of security ranges: public access range 623 and secure access range 627. The public access range includes all memory ranges to which any agent within system 600 (including trusted agent 630 and untrusted agent 635) can issue memory transactions. The public access range may include memory used for general application use, including, for example, memory used to process images, audio files, and run general applications. Secure access range 627 includes memory ranges that have restricted access. Only agents classified as trusted, such as trusted agent 630, can access memory locations within secure access range 627. A memory transaction from an untrusted agent to an address in the trusted access range 627 may be ignored or may result in the generation of an error indication, such as an exception.

In the illustrated example, both the trusted agent 630 and the untrusted agent 635 provide respective Memory transactions 650 and 655 for a destination address in address range 615b. To support secure access ranges, cache control circuitry 601 is configured to determine that address range 615b is included in the secured access range 627. In response to the determination, cache control circuitry 601 is configured to ignore memory transaction 655 from untrusted agent 630, which is not authorized to access the secured range 627. However, trusted agent 630 is authorized to access the secured range 627, and therefore cache control circuitry 601 is configured to process memory transaction 650 in address range 615b.

In response to receiving the memory transaction 655, cache control circuitry 601 may be further configured to generate an error indication. For example, cache control circuitry 601 may return an error code to the untrusted agent 635, where the error code includes a particular value indicating access to an unauthorized address. Cache control circuitry 601 may instead or additionally be further configured to assert one or more exception signals, such as an illegal address exception and/or a security violation exception.

It should be noted that system 600 is merely an example. Various elements may be omitted from system 600 for clarity. In other embodiments, system 600 may include additional secured access areas. For example, a plurality of different secured access areas may be implemented, with each area corresponding to a different secured access level and therefore accessible by different combinations of trusted agents.

The above with respect to 1 to 6 describe various techniques for reallocating a portion of a cache memory to a directly addressable address range. A variety of methods may be used to implement these disclosed techniques. Two such methods are described below with reference to 7 to 8 described.

now to 7 Turning now to FIG. 7, a flowchart is shown for one embodiment of a method for reassigning a portion of a cache memory circuit to a directly addressable address range. Method 700 may be performed by a cache control circuit, such as cache control circuits 101, 201, 501, and 601 in 1 , 2 , 5 or 6 , may be performed. Method 700 may be performed by a processing circuit executing software or firmware through hardware circuits including, for example, logic gates or a combination thereof. With common reference to 1 and 7 Process 700 begins at block 710.

At block 710, method 700 includes receiving, by cache control circuit 101, allocation request 145 to reallocate a portion of cache memory circuit 105 that is currently in use to a directly addressable memory location. As shown, allocation request 145 identifies inactive address range 115b. Allocation request 145 may be received at time t0, at which time cache memory circuit 105 was in use and one or more of cache lines 120-127 were in use to cache cache locations in system memory. Address range 115b may be specified by including in allocation request 145 an address value in address range 115b or an index value corresponding to address range 115b.

Method 700 further includes, at block 720, selecting cache line 123 of cache memory circuitry 105 for conversion based on identified address range 115b. As illustrated, cache line 123 may be associated with address range 115b due to software executing in system 100, such as an operating system. In other embodiments, cache line 123 may be hardcoded to address range 115b based on circuit design of system 100. Although only one cache line is shown as being selected for use in address range 115b, any suitable number of cache lines may be selected. For example, as described with reference to 2 As described, a cache memory circuit may include a plurality of ways, and an entire way or multiple ways may be selected for use in a directly addressable address range.

At block 730, method 700 also includes setting, by cache control circuit 101, a respective indication for the selected cache line 123 to exclude cache line 123 from further caching operations. For example, cache control circuit 101 may set a particular bit or group of bits in a cache tag corresponding to cache line 123 to indicate use of cache line 123 in address range 115b. Additionally, cache control circuit 101 may set a real-time memory indicator indicating that cache line 123 is allocated to real-time transactions with higher priorities than volume transactions. Such an indication may prevent cache control circuit 101 from releasing the contents of cache line 123 after it has been reallocated in address range 115b. A real-time indication may further prioritize any transactions with an address in address range 115b as a destination over all volume transactions queued for cache control circuit 101.

In some embodiments, method 700 may further include flushing cache line 123, by cache control circuitry 101, prior to setting the respective indication. Because cache memory circuitry 105 was used prior to receiving allocation request 145, valid data may be cached in cache line 123. If any value in cached cache line 123 has been changed and that change has not been written back to a destination in system memory, a flush command may be issued by cache control circuitry 101 that generates writeback requests for each location with modified values currently cached in cache line 123. After the writeback requests are issued, cache line 123 may be available for use in address range 115b.

Using a portion of the cache memory as a directly addressable address range may enable a low latency memory region that can be used by a particular agent to perform memory accesses that have a high QoS deadline that may not be achievable by direct addresses to the system memory, even when typical caching techniques are used for the system memory accesses. By creating a low latency memory region using cache memory circuits, the particular agent may be able to buffer data to be processed in that low latency memory region without risking the buffered data being released from the cache if not accessed within a particular time frame.

While address range 115b is active, cache lines 120 through 122 and 124 through 127 may be used for caching operations in cache memory circuit 105. For example, data written to a particular address currently cached in cache memory circuit 105 may be written back to the particular address in system memory. However, cache line 123 is not used for caching operations. For example, data written to a different address located in cache line 123 in address range 115b is not written back to system memory. Instead, cache line 123 may be used as a final destination for data written to address range 115b.

Method 700 may end in block 730 or may repeat some or all of the operations. For example, method 700 may return to block 710 in response to receiving another allocation request from cache control circuit 101. In some embodiments, multiple instances of method 700 may be performed concurrently. For example, cache control circuit 101 may be able to process a second allocation request while continuing to perform a first allocation request. If system 100 includes multiple cache control circuits (e.g., for respective cache memory circuits), each cache control circuit may be able to perform method 700 in parallel. It is noted that the method of 7 is merely an example of allocating a portion of cache memory as a directly addressable address range.

With reference to 8th , a flow chart is shown for one embodiment of a method for operating and disabling a directly addressable address range using a portion of a cache memory. In a similar manner to method 700, method 800 may be performed by a cache control circuit, such as cache control circuit 101, 201, 501, and 601, as shown in 1 , 2 , 5 or 6 Method 800 may also be performed by a processing circuit executing software or firmware through a hardware circuit or a combination thereof. Referring to 1 , 3 and 8th the method 800 begins in block 810 with cache line 123 already reassigned to address range 115b.

Method 800 includes receiving, at block 810, by cache control circuit 101 from an unauthorized agent, a memory transaction for address range 115b. As described above with respect to 6 As described, a system memory map for system 100 may include a publicly accessible area and one or more secured areas. Various agents may attempt to access address range 115b, some of which may be authorized to access one or more of the secure areas, while other agents may not have authorization to to access all addresses except those in the publicly accessible area.

At block 820, method 800 includes, in response to determining that address range 115b is part of a secure access range, ignoring, by cache control circuitry 101, the memory transaction from the unauthorized agent. As illustrated, an address included in the received memory transaction targets a location in address range 115b. Address range 115b may be determined to be within a secure access range of the system memory card to which the unauthorized agent does not have access. In response to this determination, the received memory transaction is ignored. As described above, an error message may be returned to the unauthorized agent and/or an exception signal may be asserted, e.g., to indicate to an operating system that unauthorized access was attempted.

At block 830, the method also includes receiving, by cache control circuit 101, the deny request 345 to deny cache line 123 of cache memory circuit 105 from the directly addressable address space 115b. An agent that was using address space 115b may complete activities that initiated a request to reassign cache line 123 to address space 115b. For example, a processor may have requested activation of address space 115b in response to startup of a particular application or start of a particular process within an application. Once the application or process is completed, address space 115b may not be needed and therefore may be returned for use in cache memory circuit 105, thereby increasing an amount of data that may be cached at a given time.

Method 800 further includes cache line 123 in cache operations at block 840 in response to reject request 345. As illustrated, cache line 123 is returned to cache memory circuitry 105 for use as a cache. For example, if one or more bits in a cache tag corresponding to cache line 123 were set to include cache line 123 in address range 115b, those bits may be cleared to return cache line 123 to cache memory circuitry 105. Data stored in address range 115b while cache line 123 was being reallocated may be overwritten without being written back to a system memory circuitry. Values stored in address range 115b may need to be explicitly copied to other memory locations using respective memory transactions before cache line 123 is rejected. Otherwise, any values from the address range 115b may be lost after rejection.

The method further includes, at block 850, returning a default value in response to a read request for an address in address range 115b received after rejecting cache line 123 of cache memory circuit 105. As illustrated, if memory transaction 350 is directed to an address in address range 115b after reject request 345, a default value indicating access to an inactive address is returned to an agent issuing memory transaction 350.

At block 860, method 800 also includes generating an error by cache control circuit 101 in response to a write request to an address in address range 115b received after the rejection. In addition to block 850, or in some embodiments instead of block 850, an error may be generated, such as asserting an exception signal. Such an error may provide an indication to a monitoring processor, security circuit, exception handling circuit or process, and/or other hardware circuits or software processes that an access to an inactive address has been made. In some cases, such an access may indicate an improper operating system, and a recovery operation may be initiated, such as a system reset or exception routine.

In some embodiments, method 800 may end in block 860, or in other embodiments, may repeat some or all of the operations. For example, method 800 may return to block 830 to reject a different address range in response to a different rejection request. Note that operations of method 800 may be performed in a different order, in whole or in part. For example, blocks 810 and 820 may be performed one or more times before block 830 has performed an initial time. Blocks 830 through 860 may be performed without blocks 810 and 820.

The performance of various operations of methods 700 and 800 may be performed simultaneously or in an overlapping manner. For example, cache control circuit 101 may be configured to manage multiple address ranges simultaneously. thereby enabling different processor circuits to utilize different directly addressable address ranges in an overlapping manner. Accordingly, method 800 may be performed in whole or in part while method 700 continues.

1 to 8 show various embodiments of a cache-as-RAM technique in which a portion of cache memory is mapped to a system bus accessible address space, thereby enabling a low latency memory space for a given agent or group of agents. 9 to 15 , described below, represent a distributed buffering technique in which a buffer is allocated within system memory and then allocated into a cache using a special ordering that attempts to distribute cache misses across the entirety of the buffer.

continuing with 9 1 is a block diagram of one embodiment of a system including a cache memory, illustrated at two points in time. As shown, system 900 includes processing circuitry 901, cache memory circuitry 905, and system memory circuitry 910. Cache memory circuitry 905 includes cache lines 920a through 920h (collectively, cache lines 920). System memory circuitry 910 is shown with nine memory locations 935a through 935i (collectively, locations 935). System 900 may correspond to a processor, such as a microprocessor, a microcontroller, or other form of system-on-chip (SoC). System 900 may be implemented on a single integrated circuit or by using multiple circuit elements coupled on a circuit board.

As illustrated, processing circuitry 901 may be a processor core in a single or multiple core processor complex. System 900 may include a non-transitory computer-readable medium having stored thereon instructions executable by processing circuitry 901 to perform the functions described below with respect to 9 to 15 Such a non-transitory computer-readable medium may include non-volatile memory circuitry included in and/or coupled to the system memory circuitry 910. The non-volatile memory circuitry may include, for example, flash memory arrays, a solid state drive, a hard disk drive, a universal serial bus (USB) drive, optical disk drives, floppy disk drives, and the like.

System memory circuit 910 and cache memory circuit 905 may each include one or more types of RAM, such as SRAM, DRAM, and the like.

Processing circuitry 901 is shown configured to allocate memory locations 935 in system memory circuitry 910 of system 900 to buffers 915. In various embodiments, processing circuitry 901 and/or another agent in system 900 (not illustrated) may use buffers 915 to process information related to an application executing on system 900. To meet a desired performance of that application, access to buffers 915 may have particular quality of service (QoS) needs. To increase the likelihood of meeting the QoS needs, processing circuitry 901 is further configured to allocate memory locations 935 in cache memory circuitry 905. Accesses to cache memory circuitry 905 may typically have a higher QoS level that accesses system memory circuitry 910.

To allocate buffer 915 to cache memory circuit 905, processing circuit 901 is configured to select a particular order for allocating memory locations 935 in cache memory circuit 905. This particular order may increase uniformity of cache miss rates compared to a linear order. Allocating memory locations 935 in a linear order, e.g., starting with allocating location 935a and progressing, in order, with memory locations 935b, 935c, 935d, etc. up to memory location 935i, may result in cache misses occurring more frequently for the memory locations at the end of buffer 915. For example, memory locations 935g, 935h, and 935i may have a higher probability of being unallocated because a corresponding cache line is already allocated to a different other memory location. Accordingly, a particular order for performing the allocations of memory locations 935 to cache memory circuit 905 is selected that allocates memory locations 935 in a more uniform manner that increases a probability that locations at the end of buffer 915 can be successfully allocated to cache memory circuit 905.

After the particular order is selected, processing circuitry 901 is further configured to cache one of the memory locations 935 of buffer 915 in cache memory circuitry 905 in the particular order. In some embodiments, processing circuitry 901 may be further configured to submenu 935 memory locations, each with multiple memory locations, instead of selecting and assigning individual memory locations.

As an example, at time t0, processing circuitry 901 allocates buffers 915, including memory locations 935, in system memory circuitry 910. At time t1, processing circuitry 901 is configured to segment buffers 915 into a plurality of blocks based on the particular order. This plurality of blocks corresponds to memory locations 935 and has a serial logical order, as shown.

Each memory location 935 may include any suitable number of bytes of system memory circuitry 910, such as one byte, sixteen bytes, 128 bytes, etc. In some embodiments, different memory locations 935 may include different numbers of bytes. For this example, a memory location 935 has an equal number of bytes as a cache line 920. Sizes for memory locations 935 may be determined by processing circuitry 901 based on the particular order. As shown, buffer 915 is divided into nine memory locations, and the particular order includes allocating every third memory location starting with memory location 935a, then 935d, and then 935g. The order reverses to memory location 935b, then 935e, and then 935h. The final three memory locations are then allocated starting with 935c, then 935f, and ending with 935i.

Processing circuitry 901 is further configured to cache memory locations 935 using an increment that selects one of the memory locations 935 in the particular order, which differs from the serial order. In the illustrated example, this increment is three, although any suitable number may be used. Memory location 935a is assigned to cache line 920c, followed by memory location 935d to cache line 920f, and then 935g is assigned to cache line 920h. Cache memory circuitry 905 is configured, as shown, to map a given memory location 935 to a corresponding cache line 920 based on a particular system address included in the given memory location 935. For example, cache memory circuitry 905 may hash the particular address or a portion thereof, and the resulting hash value is used to map the particular address to a corresponding cache line 920. Because cache memory circuit 905 may be much smaller than system memory circuit 910, two different system addresses may result in hash values associated with the same cache line 920. In such a case, the second of the two addresses may not be assigned.

In the example of 9 locations 935b, 935f, and 935i are mapped to cache lines 920h, 920e, and 920c, respectively. However, these three cache lines 920 have already been mapped to locations 935a, 935h, and 935g. Accordingly, locations 935b, 935f, and 935i are unmapped. As shown by the bold italicized text in buffer 915, locations that could not be mapped are distributed throughout buffer 915. As contents of buffer 915 are then traversed by an agent in logical order starting at location 935a, cache misses occur one after another separated by two or more cache hits before reaching the next cache miss.

However, if memory locations 935 were allocated in the same linear order when traversing buffer 915, memory location 935b would have been allocated instead of memory location 935g, and memory location 935f would have been allocated instead of memory location 935h. This would have resulted in memory locations 935g, 935h, and 935i all being unallocated. When the agent traverses buffer 915 in this scenario, three cache misses occur in a line at the end of buffer 915, with no cache hit occurring between the misses. Three fetches into system memory circuit 910 in a line could result in delays because the second and third fetches may have to wait for the previous fetches to be processed. Accordingly, allocating buffer 915 using the particular order instead of a linear order may reduce an overall time to traverse buffer 915.

Once allocation of buffer 915 to cache memory circuitry 905 is complete, processing circuitry 901 or other agents in system 900 may access cache memory circuitry 905 as a low latency path to values stored in buffer 915. Locations 935 that are successfully cached may provide faster access to contents of buffer 915 compared to direct accesses to locations 935 in system memory circuitry 910.

It is pointed out that the embodiment of 9 is merely an example. 9 includes only elements for describing the disclosed techniques. In other embodiments, additional elements may be included. For example, one or more Bus circuits, memory management units, and the like may be included in other embodiments. The number of cache lines and memory locations is limited for clarity. In other embodiments, any suitable number of cache lines and memory locations may be included.

In the description of 9 A failure to successfully allocate a location of a buffer is briefly discussed. If a particular location in the buffer is allocated to a cache line that has already been allocated to a different location in the buffer, the allocation fails. In some embodiments, a particular location in a buffer may be allocated to a cache line that is currently allocated to a different location in system memory that is not associated with the buffer. A technique for handling such a case is now presented.

Transitional to 10 is a block diagram of an embodiment of the system 900 of 9 again illustrated at two points in time. As shown, System 900 is the same as in 9 except that the cache memory circuit is shown with four additional cache lines, cache lines 920i through 9201. As mentioned above, for clarity, cache memory circuit 905 is shown with a limited number of cache lines in 9 In various embodiments, cache memory circuitry 905 may include any suitable number of cache lines, including, for example, additional cache lines besides the twelve shown in 10 Processing circuit 901 is shown allocating memory locations 935b, 935e, and 935h from buffer 915 into cache memory circuit 905. At time t0, processing circuit 901 attempts to allocate memory location 935b in cache line 920k.

As in 9 shown, memory location 935b was allocated to cache line 920h, which had previously been allocated to memory location 935g of buffer 915. In the embodiment of 10 memory location 935b may be further mapped to cache line 920k. For example, cache memory circuitry 905 may be set associatively and include a plurality of ways so that a given system memory address may be mapped to two or more cache lines 920. Accordingly, cache line 920k may be on a way that is different from cache line 920h and may therefore provide an alternate cache line in which to map memory location 935b.

However, cache line 920k, at time t0, is allocated to memory location 1035y, which may be a location in system memory circuitry 910 that is not allocated to buffer 915. In response to the failure to cache memory location 935b in cache line 920k, processing circuitry 901 is configured to retry caching memory location 935b before caching another memory location. As shown, processing circuitry 901 generates a new allocation request to cache memory location 935b. In some embodiments, processing circuitry 901 may include a delay of a particular amount of time or number of instruction cycles or bus cycles between the original attempt to allocate memory location 935b and the retry attempt.

At time t1, location 1035y may be freed from cache line 920k, and therefore location 935b may be successfully cached into cache line 920k. Processing circuitry 901 may then continue to attempt caching location 935e, followed by location 935h.

By repeating the cache allocation attempt of memory location 935b, processing circuit 901 can increase a number of memory locations of buffer 915 that are successfully cached. The more memory locations of buffer 915 that can be allocated in cache memory circuit 905, the better the likelihood of meeting the QoS needs of the application that will utilize buffer 915.

It is noted that the 10 is an example for demonstrating the disclosed techniques. Only elements describing these techniques are illustrated. As described above, additional elements may be included in other embodiments, such as additional cache lines and memory locations, as well as additional processing circuitry and other bus and memory management circuitry.

The system of 9 describes a processing circuit as performing many of the acts associated with caching memory locations into a cache memory circuit. Various types of processing circuits may be used to perform such acts. One such processing circuit includes a direct memory access (DMA) circuit as in 11 shown.

With reference to 11 is shown an embodiment of a system that includes a DMA circuit for temporarily storing a buffer of a system memory in a cache memory System 1100 includes processor core 1190 coupled to DMA circuitry 1101, which is further coupled to cache memory circuitry 905 and a system memory circuitry 910. In various embodiments, DMA circuitry 1101, processor core 1190, or a combination of both may be coupled to processing circuitry 901 of 9 and 10 are equivalent to.

Processor core 1190 may be a general purpose processor that performs computational operations. In some embodiments, processor core 1190 may be a special purpose processing core, such as a graphics processor, an audio processor, or a neural processor. Processor core 1190 may include, in some embodiments, a plurality of general purpose and/or special purpose processor cores, as well as auxiliary circuitry for managing power signals, clock signals, memory requests, and the like. DMA circuit 1101 is illustrated as configured to issue memory transactions to copy or move values between various memory addresses via a memory card of system 1100. DMA circuit 1101 may be implemented as a special purpose circuit, a general purpose circuit programmed to perform such tasks, or a combination thereof. DMA circuit 1101 is programmable, at least by processor core 1190, to perform multiple memory transactions in a desired sequence.

As previously described, processing circuitry 901 selects the particular order for caching locations from buffer 915 into cache memory circuitry 905. As shown in system 1100, selecting the particular order is performed by processor core 1190, for example, based on a size of buffer 915 and/or an availability of cache lines in cache memory circuitry 905. Processor core 1190 is configured to program the particular order into DMA circuitry 1101 and use DMA circuitry 1101 to cache one of the locations 935 from buffer 915 into cache memory circuitry 905. For example, DMA circuitry 1101 may include various registers into which processor core 1190 may store source addresses for locations 935 and destination addresses to cache memory locations 935 in cache memory circuitry 905, including providing the particular order for issuing memory transactions corresponding to one of the memory locations 935.

As illustrated, processor core 1190 is further configured to track a cache miss rate in cache memory circuitry 905 for memory transactions that include accesses to memory locations 935. After buffer 915 is allocated in cache memory circuitry 905, processor core 1190 or a different agent in system 1100 may issue different memory transactions that access one of the memory locations 935. Depending on how many of the memory locations 935 were successfully allocated to cache memory circuitry 905, a particular cache miss rate may be determined for those memory transactions that target addresses in memory locations 935. For example, if ten percent of memory locations 935 are unallocated and memory locations 935 are accessed evenly by a particular agent using buffer 915, then the cache misses would be close to or equal to ten percent. However, if the particular agent accesses particular ones of the memory locations 935 more frequently than others, then the cache miss rate may be higher or lower than ten percent, depending on whether the more frequently accessed memory locations were successfully allocated.

In response to a determination that the tracked cache miss rate meets a threshold rate, processor core 1190 may be further configured to modify the particular order in DMA circuitry 1101. For example, if the threshold miss rate is 15% and the tracked miss rate is 18%, processor core 1190 may identify memory locations 935 that were not cached but were frequently targeted in memory transactions, as well as successfully cached memory locations 935 that were not frequently targeted. A revised order may adjust the order for allocating these identified memory locations so that the more frequently accessed locations are allocated earlier in the modified order and the less frequently accessed locations are moved toward the end of the modified order. When a subsequent buffer is to be allocated to cache memory circuitry 905, the modified order may be selected over the original particular order. In some embodiments, different orders may be determined and assigned to particular agents, tasks, processes, and the like, such that a selected order for assignment takes into account the performance of similar tasks.

With respect to determining an allocation order, a technique has been disclosed above in which subsequent memory locations are selected using a particular increment between consecutive positions. In 11 A technique is illustrated which divides the partition buffer 915 into a plurality of blocks 1130a to 1130c (collectively blocks 1130) each having rows of contiguous memory locations 935. The nine illustrated memory locations 935 are divided into three blocks 1130, with each block 1130 including three consecutive memory locations 935. Although blocks 1130 are shown to include an equal number of memory locations 935 per block, in other embodiments the number of memory locations 935 included in each block 1130 may vary. For example, a use for buffers 915 may be known, and based on the known use, particular memory locations 935 or groups of locations may be known to be infrequently accessed while others are known to be accessed more frequently. A number of memory locations 935 assigned to each block may therefore be adjusted such that, for example, an initial memory location 935 for each block is a location known to be accessed more frequently.

After memory locations 935 are divided into respective blocks 1130, processor core 1190 may select a particular order that allocates a first memory location 935 to a respective series of blocks 1130 of cache memory circuit 905 and then allocates a second memory location 935 of the respective blocks 1130. As shown, block 1130a includes initial memory location 935a, followed by memory locations 935c and 935c. Similarly, block 1130b includes initial memory location 935d, followed by memory locations 935e and 935f, while block 1130c includes initial memory location 935g, followed by memory locations 935h and 935i.

In a first pass, processor core 1190 causes DMA circuit 1101 to cache the initial memory location of each of blocks 1130, memory locations 935a, 935d, and 935g. DMA circuit 1101 then caches a second memory location of each block 1130 (memory locations 935b, 935e, and 935h) in a second pass, followed by a third pass in which a third location of each block 1130 (memory locations 935c, 935f, and 935i) is cached.

As mentioned above, processor core 1190 may modify the particular order based on a monitored cache miss rate. This modification may include adjusting a number of locations included in each block, a number of locations stored at one time by each block, or an order for allocating the locations within each block. For example, processor core 1190 may determine that memory location 935e is accessed more frequently than memory location 935d in block 1130b. In a modified order, the initial memory location allocated from block 1130b may be 935e rather than 935d.

Please note that System 1100 is only an example. 11 has been simplified for clarity. Although nine memory locations and three blocks are shown, buffer 915 may include any suitable number of memory locations, and these locations may be divided into any suitable number of blocks. A number of locations included in each block may vary between blocks. In addition, a number of locations of each block allocated at a given time may vary between runs.

Different types of QoS levels are defined in relation to 1 to 8 discussed. Transactions used to cache a buffer from system memory to cache memory can also use different QoS levels for different tasks. 12 illustrates the use of volume and real-time transactions with the disclosed techniques.

Now continuing with 12 is an embodiment of System 900 from 9 and 10 at two different times during a buffer allocation for caching and during use of the allocated buffer. System 900 includes the elements as previously described in 9 and 10 . Additionally, cache memory circuitry 905 and system memory circuitry 910 are configured to support volume and real-time channels 1240 and 1245, respectively. In some embodiments, volume and real-time channels 1240 and 1245 may use separate physical connections between different agents and memory circuitry to complete the respective transactions. In other embodiments, at least a portion of real-time channel 1245 and volume channel 1240 are shared and may be implemented as virtual volume and real-time channels, as described above, in some embodiments.

At time t0, buffer 915 is cached in cache memory circuit 905. In the present embodiment, buffer 915 is a real-time buffer. A "real-time buffer" as used herein refers to a memory buffer in which real-time transactions are primarily used to access the buffer's locations. A real-time buffer may be used with an agent and/or task that may experience a failure of a particular QoS requirement. question could lead to improper operation of the agent or task. For example, processing a frame of a video for playback must be completed within a specific amount of time, otherwise the video playback may cause noticeable stalling or disruption to the viewer.

Although buffer 915 is a real-time buffer, the initial allocation of buffer 915 into the cache may not be time sensitive. Accordingly, caching of storage locations 935 of buffer 915 may be performed using volume transactions 1242 over volume channel 1240 to allocate the plurality of storage locations 935 in cache memory circuit 905. As shown at time t0, volume channel 1240 is used to transmit volume transactions 1242a, 1242b, and 1242c to allocate storage locations 935a, 935d, and 935g in cache memory circuit 905, respectively. During this buffer allocation task, the agent that is to use buffer 915, processing circuit 901, for example, may not have values ready to be read from or written to buffer 915. Accordingly, volume transactions 1242 may be used to allocate buffer 915.

However, because buffer 915 is used with real-time transactions, volume transactions 1242 may include an indication with successfully cached memory locations 935 indicating that those cached memory locations are associated with real-time transactions. For example, cache tags associated with each successfully cached memory location 935 may include a particular bit or group of bits indicating that the associated cache line 920 is used with real-time transactions. Cache lines 920 with the real-time indications in their respective cache tags may receive higher priority when identifying cache lines for release. For example, when a particular number of cache lines 920 in cache memory circuitry 905 reach the threshold level, e.g., approaching a certain percentage of maximum memory capacity, particular ones of the cache lines 920 that have not been frequently accessed may be selected for release. Cache lines 920 with the real-time indications set may no longer be considered for deallocation or may be placed very low in an order to be selected, e.g., other cache lines would have higher probabilities of being selected for deallocation.

Cache memory circuitry 905 may also reserve a particular amount of bandwidth for retrieving data from system memory circuitry 910 in response to a cache miss associated with a real-time memory transaction. Cache memory circuitry 905 may limit a number of volume transactions that are issued and active at a given time such that bandwidth remains to issue a real-time transaction. For example, bus circuitry between cache memory circuitry 905 and system memory circuitry 910 may include a credit-based arbiter circuit. To have an issued transaction selected by this arbiter circuitry, cache memory circuitry 905 may maintain a particular number of bus credits. In such an embodiment, cache memory circuitry 905 may delay issuing a volume transaction when the number of bus credits is at or near the particular number. The volume transaction may be sent after cache memory circuitry 905 has accumulated a sufficient number of bus credits.

At time t1, buffer 915 has been allocated to cache memory circuitry 905. As indicated by the bold italic text, locations 935f and 935i have not been successfully cached. For example, locations 935f and 935i may have been mapped to cache lines 920i and 9201 that were previously mapped to locations 1235x and 1235y, respectively. Processing circuitry 901 is further configured to access the successfully cached location 935c using real-time transaction 1250a. Cache memory circuitry 905 may be configured to process real-time transaction 1250a using values stored in cache line 920a.

Cache memory circuitry 905 is configured to generate fetch requests to system memory circuitry 910 in response to a cache miss associated with a respective memory transaction, wherein the generated fetch requests have a QoS level compatible with the corresponding memory transaction. For example, cache memory circuitry 905 may generate volume fetches 1265a and 1265b in response to volume transactions from a given agent. Processing circuitry 901 may be further configured to access the unsuccessfully cached memory location 935f using real-time transaction 1250b. Cache memory circuitry 905 is configured in response to a cache miss for memory location 935f to satisfy real-time transaction 1250b using a real-time fetch 1290. Because cache memory circuitry 905 is configured to reserve bandwidth for real-time fetches, real-time fetches may be prioritized over other volume fetches that have not been issued. For example, volume retrieval 1265b may be queued and await completion of volume retrieval 1265a. If real-time retrieval 1290 is generated before volume retrieval 1265b, real-time retrieval 1290 may be processed before volume retrieval 1265b.

Using such real-time and volume QoS levels can reduce access times for an agent using a real-time buffer allocated to cache memory. Using the real-time QoS level can also reduce memory access times in case a portion of the real-time buffer is not allocated to the buffer.

It is pointed out that the embodiment of 12 is only an example for demonstration purposes. For clarity, 12 numerical elements shown are minimized. Despite the illustrated number of memory locations and cache lines, any suitable number of memory locations and cache lines may be included in other embodiments. Although only real-time and volume transactions are shown, any suitable number of QoS levels may be used in other embodiments.

The above with respect to 9 to 12 describe various techniques for allocating a buffer located in a system memory to a cache memory. A variety of methods may be used to implement these various techniques. Three such methods are described below with reference to 13 to 15 described.

Transitioning now to 13 , a flowchart is shown for one embodiment of a method for caching a buffer located in a system memory into a cache memory circuit. In various embodiments, method 1300 may be performed by processing circuit 901 in 9 , 10 and 12 as part of the process of caching buffer 915 in cache memory circuit 905. For example, processing circuit 901 may include (or access) a non-transitory computer-readable medium having stored thereon program instructions executable by the processing circuit to perform the functions described with reference to 13 With joint reference to 9 and 13 Process 1300 begins at block 1310.

At block 1310, method 1300 includes allocating, by processing circuitry 901, a plurality of memory locations 935 in system memory circuitry 910 to buffer 915. As shown, processing circuitry 901 or a different agent in system 900 may request buffer 915 to be allocated in system memory circuitry 910 for use with a particular process or task that the agent is preparing to perform. For example, the task may include processing an image, an audio file, encrypting or decrypting a file, analyzing input from a sensor, and the like. In some embodiments, buffer 915 may be a real-time buffer that uses real-time transactions to access memory locations 935. As previously described, real-time transactions have a higher level of QoS than other transactions, such as volume transactions.

Method 1300 further includes, at block 1320, determining a particular order for allocating memory locations 935 in cache memory circuitry 905. This particular order may be selected to increase uniformity of cache miss rates compared to using a linear order. As previously described, allocating memory locations 935 using a linear order may result in memory locations 935 near the beginning of the linear order being successfully cached, while memory locations 935 at the end of the linear order are not successfully cached because they are mapped to the same cache lines 920 as previously cached memory locations 935. If data from memory locations 935 in buffer 915 is accessed in the same order as it was allocated, more cache misses would be expected as processing moves toward the end of the order. Accordingly, the particular order is selected such that caching occurs in an order that attempts to evenly distribute cache misses during use of buffer 915. Accordingly, cache misses may not be concentrated during any particular portion of buffer accesses during use of buffer 915.

At block 1330, method 1300 also includes caching memory locations 935 from buffer 915 using the particular order. After the particular order for allocating memory locations 935 is selected, processing circuit 901 begins allocating memory locations 935 in cache memory circuit 905. In some embodiments, as in 10 shown, method 130 may include repeating again in response to a failure to cache a particular memory location 935 (e.g., memory location 935b), wherein memory location 935b is cached before a different memory location 935, such as memory location 935e, is cached.

Method 1300 may end in block 1330. In some embodiments, at least a portion of method 1300 may be repeated. For example, method 1300 may be repeated in response to receiving a request to allocate a different buffer in system memory circuit 910. In some cases, method 1300 may be performed concurrently with other instances of the method. For example, two or more instances of processing circuit 901, or multiple process threads within a single instance of processing circuit 901, may each perform method 1300 independently of one another.

With reference to 14 14 illustrates a flow chart for one embodiment of a method for using different QoS levels with a buffer allocated in a cache memory circuit. In a similar manner to method 1300, method 1400 may be performed by processing circuit 901 in 9 , 10 and 12 As described above, processing circuitry 901 may include (or access) a non-transitory computer-readable medium having stored thereon program instructions executable by processing circuitry 901 to perform the functions described with reference to 14 With joint reference to 12 and 14 Procedure 1400 begins at block 1410.

At block 1410, method 1400 includes using volume transactions 1242 to allocate the plurality of locations in the cache memory circuit. As illustrated, the allocation process of buffer 915 may not have a critical QoS requirement. Accordingly, caching of storage locations 935 of buffer 915 may be performed using volume transactions 1242 to allocate storage locations 935 in cache memory circuit 905. As at time t0 of 12 As shown, volume channel 1240 is used to transfer volume transactions 1242a, 1242b, and 1242c to allocate memory locations 935a, 935d, and 935g, respectively, in cache memory circuit 905.

Method 1400 also includes, at block 1420, an indication of successfully cached memory locations 935 indicating use with real-time transactions. Although the allocation process for buffer 915 may not have had a real-time need, buffer 915 may be expected to be accessed using real-time transactions. Accordingly, when a particular memory location 935 is successfully cached into a respective cache line 920, a corresponding cache tag for the cache line may include an indication that the cached contents are associated with real-time transactions. As previously described, such indications may help avoid deallocation of cache lines 920 allocated to buffer 915.

At block 1430, method 1400 further includes accessing by an agent (e.g., processing circuit 901) that has successfully cached storage locations 935 using real-time transactions. After the allocation of buffer 915 is completed, processing circuit 901 may, as in 12 shown, access one of memory locations 935 using real-time transactions 1250a and 1250b. Real-time transaction 1250a encounters cache line 920a where memory location 935c has been cached. If real-time transaction 1250a includes a read request, data from cache line 920a corresponding to a requested address may be sent from cache memory circuit 905 to processing circuit 901 using a real-time transaction.

Method 1400 at block 1440 also includes, in response to a cache miss for a particular location of memory locations 935 that could not be cached, using, by cache memory circuitry 905, real-time transactions to access the particular location 935 in buffer 915 in system memory circuitry 910. As in 12 As shown, real-time transaction 1250b is directed to memory location 935f. However, memory location 935f could not be successfully cached in cache memory circuit 905. Accordingly, cache memory circuit 905 generates and issues real-time fetch 1290 to system memory circuit 910 to retrieve values from memory location 935f. If either volume fetches 1265a and 1265b, also generated by cache memory circuit 905, have not been issued when real-time fetch 1290 is ready, real-time fetch 1290 may be prioritized over the unissued volume fetches.

Method 1400 may end in block 1440 or may be repeated in whole or in part in some embodiments. For example, block 1430 may be repeated while processing circuit 901 stores processing values in buffer 915. Similarly, block 1440 may be repeated if processing circuit 901 accesses a memory location 935 that was not successfully cached. Similarly to method 1300, method 1400 may be performed concurrently with other instances of method 1400.

Continuing now with 15 is a flowchart for one embodiment of a method for selecting and adjusting a particular order for allocating a buffer to a cache memory circuit. As described for methods 1300 and 1400, method 1400 may be performed by processing circuit 901 in 9 , 10 and 12 As described, processing circuitry 901 may include (or access) a non-transitory computer-readable medium having stored thereon program instructions executable by processing circuitry 901 to perform the functions described with reference to 15 With joint reference to 12 and 15 Procedure 1500 begins at block 1510.

At block 1510, method 1500 includes determining the particular order using a desired cache miss rate for the plurality of memory locations 935. As described above, the particular order for allocating buffer 915 may be selected with a goal of distributing cache misses across buffer 915. An agent that will use buffer 915 (e.g., processing circuitry 901) may process data stored in buffer 915 using a linear order. Processing circuitry 901 may begin at an initial memory location such as 935a and proceed through memory locations 935 in sequence, e.g., 935b, 935c, etc., ending with memory location 935i. If memory locations 935 are allocated in the same linear order, more memory locations 935 may not be cached toward the end of buffer 915. Processing data in buffer 915 in the same order may result in an increasing cache miss rate as processing progresses, potentially toward the end of buffer 915. The particular order may be selected to distribute misses of memory locations 935 to be allocated across buffer 915 such that when buffer 915 is processed, a peak cache miss rate remains below the desired cache miss rate.

Method 1500 also includes, at block 1520, accessing, by processing circuitry 901 after caching, the plurality of storage locations 935 using a linear order. As described, processing circuitry 901 may access buffers 915 using a linear order that is different from the particular order. In other embodiments, processing circuitry 901 may use a different order that includes a linear order. In such embodiments, the particular order may be chosen to be different, including, for example, using a linear order to allocate storage locations 935.

At block 1530, the method further includes tracking a cache miss rate associated with using the particular order to cache the plurality of memory locations 935. Since processing circuitry 901 uses buffers 915, an observed cache miss rate may be tracked and may be further compared to the desired cache miss rate. If the particular order for allocating memory locations 935 was effective, the tracked cache miss rate should remain below the desired cache miss rate because the cache miss rate may occur consistently throughout the processing of all data in buffer 915. By distributing cache misses consistently, a peak cache miss rate should remain reasonably low and not exceed the desired cache miss rate.

Method 1500 further includes, at block 1540, in response to determining that the tracked cache miss rate meets a threshold rate, adjusting the particular order for subsequent use. As illustrated, if the tracked cache miss rate meets or exceeds the desired cache miss rate, allocating buffers 915 using the selected particular order does not achieve the desired results. The threshold rate may be equal to the desired cache miss rate, or may be set higher or lower based on overall system operating goals. To adjust the particular order, cache misses that occurred at the time when the cache miss rate met the threshold rate may be analyzed to identify memory locations 935 that were accessed. One or more of these identified memory locations 935 may be selected to be moved closer to the beginning of an adjusted allocation order. Additionally, memory locations 935 that were accessed at a time when the cache miss rate was low may also be identified. One or more of these locations can be selected to be moved toward the end of the customized allocation order.

Method 1500 may end in block 1540 or may be repeated in whole or in part in some embodiments. For example, blocks 1520 and 1530 may be repeated while processing circuitry 901 accesses storage locations 935 in buffer 915. As described for methods 1300 and 1400, method 1500 may also be performed concurrently with other instances of method 1500. Additionally, methods 1300, 1400, and 1500 may be performed concurrently.

1 to 8 illustrate circuits and methods for a system that reallocates a portion of cache memory for use as a directly addressable address range. 9 to 15 illustrate circuits and techniques for caching a buffer located in a system memory in a cache memory circuit. Each embodiment of the disclosed systems may be included in one or more of a variety of computer systems, such as a desktop computer, laptop computer, smartphone, tablet, wearable device, and the like. In some embodiments, the circuits described above may be implemented on a system-on-chip (SoC) or other type of integrated circuit. A block diagram illustrating an embodiment of the computer system 1600 is shown in 16 Computer system 1600 may include any of the disclosed embodiments, such as systems 100, 200, 500, 600, 900, or 1100, in some embodiments.

In the illustrated embodiment, system 1600 includes at least one instance of a system-on-chip (SoC) 1606, which may include multiple types of processing circuitry, such as a central processing unit (CPU), a graphics processing unit (GPU), or others, a communications fabric, and interfaces to memories and input/output devices. In some embodiments, one or more processors in SoC 1606 include multiple execution lanes and an instruction issue queue. In various embodiments, SoC 1606 is coupled to external memory 1602, peripherals 1604, and a power supply 1608.

A power supply 1608 is also provided that supplies the supply voltages to the SoC 1606 and one or more supply voltages to the memory 1602 and/or peripherals 1604. In various embodiments, power supply 1608 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet computer, or other device). In some embodiments, more than one instance of the SoC 1606 is included (and more than one external memory 1602 is also included).

The memory 1602 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR, DDR2, DDR3, etc.) (including mobile versions of SDRAMs such as mDDR3, etc., and/or low power versions of SDRAMs such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form memory modules such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the devices are mounted with a SoC or integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

Peripherals 1604 include any desired circuitry depending on the type of system 1600. For example, in one embodiment, peripherals 1604 include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, peripherals 1604 also include additional storage, including RAM storage, solid state storage, or disk storage. Peripherals 1604 include user interface devices, such as a display screen, including touch display screens or multi-touch display screens, keyboard or other input devices, microphones, speakers, etc.

As illustrated, system 1600 is shown to find application in a wide range of areas. For example, system 1600 may be utilized as part of the chips, circuitry, components, etc. of a desktop computer 1610, laptop computer 1620, tablet computer 1630, cellular or mobile phone 1640, or television 1650 (or a set-top box coupled to a television). Also illustrated are a smart watch and a health monitoring device 1660. In some embodiments, a smart watch may include a variety of general purpose computing-related functions. For example, the smart watch may provide access to email, cellular service, a user calendar, and so on. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. For example, a health monitoring device may monitor a user's vital signs, track a user's proximity to other users for the purpose of epidemiological distancing, contact tracing, provide communication to emergency services in the event of a health emergency, and so on. In various embodiments, the aforementioned smartwatch may include some or no health monitoring-related functionality. Other wearable devices 1660 are also contemplated, such as devices worn around the neck, devices worn on hats or other headwear, devices implantable in the human body, glasses designed to provide an augmented and/or virtual reality experience, and so on.

System 1600 may further be used as part of a cloud-based service(s) 1670. For example, the aforementioned devices and/or other devices may access computing resources in the cloud (i.e., remotely located hardware and/or software resources). Furthermore, system 1600 may be used in one or more other devices of a residence 1680 than those previously mentioned. For example, devices within the residence may monitor and detect conditions that require attention. Various devices within the residence (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device and provide an alert to the residence owner (or, for example, a repair facility) should a particular event be detected. Alternatively, a thermostat may monitor the temperature in the residence and may automate settings of a heating/cooling system based on a history of responses to various conditions by the residence owner. Also in 16 illustrated is the application of system 1600 to various modes of transportation 1690. For example, system 1600 may be used in the control and/or entertainment systems of airplanes, trains, buses, rental cars, passenger vehicles, watercraft, from private boats to cruise ships, scooters (rental or owned), and so on. In various cases, system 1600 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, and others.

It is noted that the wide variety of potential applications for system 1600 may include a variety of performance, cost, and power consumption requirements. Accordingly, a scalable solution that enables the use of one or more integrated circuits to provide an appropriate combination of performance, cost, and power consumption may be advantageous. These and many other embodiments are possible and are contemplated. It is noted that the 16 The devices and applications illustrated are illustrative only and are not intended to be limiting. Other devices are possible and are contemplated.

As with regard to 16 As disclosed, computer system 1600 may include one or more integrated circuits encapsulated within a personal computer, smartphone, tablet computer, or other type of computing device. A process for designing and manufacturing an integrated circuit using design information is described below in 17 shown.

17 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information, in accordance with some embodiments. The embodiment of 17 can be used in a process to design and manufacture integrated circuits, for example, any of the systems 100, 200, 500, 600, 900 or 1100 as in 1 - 15 shown and described. In the illustrated embodiment, semiconductor manufacturing system 1720 is configured to process the design information 1715 stored on the non-transitory computer-readable storage medium 1710 and to manufacture the integrated circuit 1730 (e.g., system 100) based on the design information 1715.

The non-transitory computer-readable storage medium 1710 may comprise any of various suitable types of storage devices or storage devices. The non-transitory computer-readable storage medium 1710 may be an installation medium, e.g., a CD-ROM, floppy disks, or tape device; a computer system memory or random access memory, such as DRAM, DDR-RAM, SRAM, EDO-RAM, Rambus-RAM, etc.; a non-volatile memory, such as flash memory, magnetic media, e.g., a hard disk or optical storage; registers or other similar types of storage elements, etc. The non-transitory computer-readable storage medium 1710 may also comprise other types of non-volatile memory. cher or combinations thereof. The non-transitory computer-readable storage medium 1710 may include two or more storage media that may be located in different locations, e.g., in different computer systems connected via a network.

Design information 1715 may be specified using any of various suitable computer languages, including hardware description languages, such as without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1715 may be usable by semiconductor manufacturing system 1720 to manufacture at least a portion of integrated circuit 1730. The format of design information 1715 may be recognized by at least one semiconductor manufacturing system, such as semiconductor manufacturing system 1720. In some embodiments, design information 1715 may include a netlist specifying elements of a cell library as well as their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit 1730 may also be included in design information 1715. Such cell libraries may include information specifying device or transistor level netlists, mask design data, characterization data, and the like of cells included in the cell library.

Integrated circuit 1730 may, in various embodiments, include one or more user-defined macrocells, such as memory, analog or mixed-signal circuits, and the like. In such cases, design information 1715 may include information related to included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to the Graphics Data System (GDSII) or any other suitable format.

Semiconductor manufacturing system 1720 may include any of various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer, which may include masking), removing materials, changing the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), etc. Semiconductor manufacturing system 1720 may also be configured to perform various tests of manufactured circuits for proper operation.

In various embodiments, integrated circuit 1730 is configured to operate according to a circuit design specified by design information 1715, which may include performing any of the functionality described herein. For example, integrated circuit 1730 may include any of various elements shown or described herein. Furthermore, integrated circuit 1730 may be configured to perform various functions described herein in conjunction with other components.

As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order for the element to be satisfied. Rather, this phrase indicates that the design information describes a circuit that, after manufacture, is configured to perform the specified actions or to include the specified components.

The present disclosure includes references to an "embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are various implementations or instances of the disclosed concepts. References to "embodiment," "an embodiment," "a particular embodiment," and the like do not necessarily refer to the same embodiment. A wide number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the disclosure.

This disclosure may discuss potential benefits that may result from the disclosed embodiments. Not all implementations of these embodiments necessarily have any or all of the potential benefits. Whether a benefit is achieved for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are a number of reasons why an implementation that falls within the scope of the claims may not have some or all of the disclosed benefits. For example, a particular implementation might include different circuitry outside the scope of the disclosure. that, when used in conjunction with any of the disclosed embodiments, cancels or reduces one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation techniques or tools) could also cancel or reduce disclosed benefits. Even assuming a qualified implementation, the achievement of benefits may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring on a particular occasion, thereby potentially failing to achieve the benefit of its solution. Due to the existence of possible factors external to this disclosure, it is expressly intended that any potential benefits described herein should not be construed as claim limitations that must be met to prove infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvement available to designers who have the benefit of this disclosure. The fact that such advantages are described in a permissive sense (e.g. by stating that a particular advantage "may occur") is not intended to cast doubt as to whether such advantages can actually be achieved, but is instead intended to recognise the technical reality that the achievement of such advantages often depends on additional factors.

Unless otherwise specified, embodiments are not limiting. That is, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, unless otherwise stated in the disclosure. Thus, the application is intended to enable claims to cover disclosed embodiments as well as the alternatives, modifications, and equivalents that would be obvious to one skilled in the art having the benefit of this disclosure.

For example, features in this application may be combined in any suitable manner. Accordingly, during the prosecution of this application (or an application claiming priority hereto), new claims may be drafted to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of other dependent claims where appropriate, including claims dependent on other independent claims. Similarly, features from respective independent claims may be combined where appropriate.

Accordingly, while the appended dependent claims may be drafted such that each depends on a single other claim, additional dependencies are also contemplated. All combinations of features in the dependent that are consistent with this disclosure are contemplated and may be claimed in this or another application.

In summary, combinations are not limited to those specifically recited in the appended claims.

Where appropriate, it is also contemplated that claims formulated in one format or statutory type (e.g. facility) should support corresponding claims in another format or statutory type (e.g. method).

Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and legal interpretation. Notice is hereby given that the following paragraphs, as well as definitions provided throughout the disclosure, are to be used in determining how claims made based on this disclosure are to be interpreted.

References to a singular form of an element (i.e., a noun or noun phrase preceded by "a" or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, a reference to "an element" in a claim does not exclude additional instances of the element without an accompanying context. A "plurality" of elements refers to a set of two or more of the elements.

The word “may” is used herein in a permissive sense (i.e. having the potential, being able to) and not in an obligatory sense (i.e. must).

The terms “comprehensive” and “including” and forms thereof are open-ended and mean “including, but not limited to.”

When the term "or" is used in this disclosure in reference to a list of options, it is generally understood to be used in the inclusive sense unless the context indicates otherwise. Thus, a statement of "x or y" is equivalent to "x or y or both" and thus covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, a phrase such as "either x or y but not both" makes it clear that "or" is used in the exclusive sense.

A statement of "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" is intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, for the set [w, x, y, z], these phrases cover any single element of the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "at least one of ... x, y, and z" thus refers to at least one element of the set [w, x, y, z], covering all possible combinations in this list of elements. This phrase should not be interpreted to require that at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z be present.

Various "labels" may appear before nouns or noun phrases in this disclosure. Unless the context indicates otherwise, various labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Additionally, the labels "first," "second," and "third," when applied to a feature, do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

The phrase "based on" or is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on stated factors, or may be based on the stated factors as well as other, unstated factors. Consider the phrase "determine A based on B." This phrase indicates that B is a factor used to determine A or that influences the determination of A. This phrase does not exclude that the determination of A may also be based on another factor, such as C. This phrase is also intended to cover an embodiment in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either together with the specified factors or independently of the specified factors. That is, an effect may occur solely in response to these factors, or may occur in response to the specified factors as well as other, unspecified factors. Consider the phrase “performing A in response to B.” This phrase indicates that B is a factor that triggers the performance of A or that triggers a particular result for A. This phrase does not exclude that performing A may also occur in response to another factor, such as C. This phrase also does not exclude that performing A may occur in response to B and C together. This phrase is also intended to cover an embodiment in which A is performed based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.” Similarly, the phrase “in response to” is synonymous with the phrase “at least in part in response to”.

Within this disclosure, various entities (which may be variously referred to as "units,""circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This phrase - [entity] configured to [perform one or more tasks] - is used herein to refer to a structure (i.e., something physical). In particular, this phrase is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure may be referred to as being "configured to" perform a task even if the structure is not currently operating. Thus, an entity described or claimed as being "configured to" perform a task refers to something physical, such as a device, a circuit, a system having a processing unit and a memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to anything intangible.

In some cases, various entities/circuits/components may be described herein as performing a set of tasks or operations. It is understood that these entities are "configured to" perform these tasks/operations, even if not specifically stated.

The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, that unprogrammed FPGA may be "configurable to" perform that function. After appropriate programming, the FPGA can then be said to be "configured to" perform the particular function.

For purposes of U.S. patent applications based on this disclosure, a claim that a structure is "configured to" perform one or more tasks is expressly intended not to invoke the application of 35 U.S.C. § 112(f) for that claim element. If the applicant wishes to invoke the application of section 112(f) during the prosecution of a U.S. patent application based on this disclosure, the applicant shall specify claim elements using the construct "means for" [performing a function].

Various "circuits" may be described in this disclosure. These circuits or "circuit logic" constitute hardware that includes various types of circuit elements, such as combinational logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, and so on. Circuit logic may be user-defined or taken from standard libraries. In various implementations, circuit logic may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be referred to generally as "units" (e.g., a decoding unit, an arithmetic logic unit (ALU), a functional unit, a memory management unit (MMU), etc.). Such units also refer to circuits or circuit logic.

The disclosed circuits/units/components and other elements illustrated in the drawings and described herein thus include hardware elements such as those described in the preceding paragraph. In many cases, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" can be described as performing the function of "processing an opcode of an instruction and redirecting that instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. This functional specification is sufficient for one skilled in the computer arts to specify a set of possible structures for the circuit.

In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement of these circuits/units/components with respect to one another and the manner in which they interact form a microarchitectural definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, the microarchitectural definition will be recognized by those skilled in the art as a structure from which many physical implementations may be derived, all of which fall within the broader structure described by the microarchitectural definition. That is, those skilled in the art, presented with the microarchitectural definition provided in accordance with this disclosure, may, without undue experimentation and by the exercise of ordinary skill, implement the structure by coding the description of the circuits/units/components in a hardware description language (HDL), such as Verilog or VHDL. The HDL description is often expressed in a manner that may appear functional. However, for those skilled in the art, this HDL description is the manner used to transform the structure of a circuit, device, or component to the next level of implementation detail. Such HDL description may take the form of behavioral code (which is typically not synthesizable), Register Transfer Language (RTL) code (which, unlike behavioral code, is typically synthesizable), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may then be synthesized against a library of cells designed for a given integrated circuit manufacturing technology, and may be customized for timing, power, and other reasons to result in a final design database that is submitted to a foundry to generate masks and ultimately manufacture the integrated circuit. Some hardware circuits, or portions thereof, may also be customized in a schematic editor and incorporated into the integrated circuit design along with synthesized circuit logic. The integrated circuits may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and provide interconnection between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuits, and/or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array, such as a field programmable gate array (FPGA), and may be implemented in the FPGA. This decoupling between the design of a group of circuits and the subsequent low-level implementation of those circuits typically leads to the scenario where the circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuit is configured to do, since that process is performed at a different stage of the circuit implementation process.

The fact that many different low-level combinations of circuit elements can be used to implement the same specification of a circuit results in a large number of equivalent structures for that circuit. As indicated, these low-level circuits may vary according to changes in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methodologies to produce these different implementations may be arbitrary.

Moreover, it is common for a single implementation of a particular functional specification of a circuit to include a large number of devices (e.g., millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete specification of the low-level structure used to implement a single embodiment, let alone the vast array of equivalent possible implementations. For this reason, the present disclosure describes a structure of circuits using the functional shorthand commonly used in the industry.

Claims (20)

Apparatus comprising: a cache memory circuit including a cache memory having a plurality of cache lines; and a cache control circuit configured to: receive a request to reallocate a portion of the cache memory circuit that is currently in use, the request identifying an address range corresponding to one or more of the plurality of cache lines; and in response to the request, converting the one or more cache lines to directly addressable random access memory (RAM) by excluding the one or more cache lines from caching operations. Facility according to Claim 1 wherein the cache control circuit is further configured to: support a real-time virtual channel for memory transactions in the identified address range; and prioritize a memory transaction received over the real-time virtual channel over a memory transaction received over a volume virtual channel. Facility according to Claim 1 wherein the cache control circuit is further configured to: determine that the address range is included in a secure access range; and in response to the determination, ignoring a memory transaction in the address range from an agent that is not authorized to access the secure access range. Facility according to Claim 1 wherein the cache control circuit is further configured to flush the one or more cache lines before converting the one or more cache lines to the directly addressable RAM. Facility according to Claim 1 wherein the cache control circuit is further configured to: in response to data being written to a valid cache line, output a Writeback request for the valid cache line; and excluding the one or more cache lines from writeback requests. Facility according to Claim 1 wherein the cache control circuit is further configured to: receive a different request to declassify the portion of cache memory from the directly addressable RAM; and in response to the different request, including the one or more cache lines in cache operations without copying data stored in the directly addressable RAM while the one or more cache lines are being reallocated. Facility according to Claim 6 wherein the cache control circuit is further configured to generate an error in response to a memory transaction in the directly addressable RAM received after rejecting the portion of the cache memory. A method comprising: receiving, by a cache control circuit, a request to reassign a portion of a cache memory circuit that is currently in use to a directly addressable address range, the request identifying an inactive address range; based on the identified address range, selecting one or more cache lines of the cache memory circuit to convert; and setting, by the cache control circuit, a respective indication for one of the selected cache lines to exclude the selected cache lines from further caching operations. Procedure according to Claim 8 , wherein setting the respective indication includes setting, by the cache control circuit, a real-time storage indicator, the real-time storage indicator indicating that the selected cache lines are associated with real-time transactions having higher priorities than volume transactions. Procedure according to Claim 8 further comprising, in response to determining that the identified address range is part of a secured access range, ignoring, by the cache control circuitry, a memory transaction for the identified address range from an agent that is not authorized to access the secured access range. Procedure according to Claim 8 further comprising, by the cache control circuit, flushing the selected cache lines prior to setting the respective indications. Procedure according to Claim 8 wherein data written to a particular address currently cached in the cache memory circuit is written back to the particular address in a system memory; and wherein data written to a different address located in the identified address range is not written back to the system memory. Procedure according to Claim 8 further comprising: receiving, by the cache control circuit, a different request to declassify the portion of the cache memory circuit from the directly addressable address space; and in response to the different request, including the selected cache lines in cache operations, wherein data stored in the directly addressable address space while the selected cache lines were being reallocated is overwritten without a write-back operation to a system memory circuit. Procedure according to Claim 13 further comprising returning, by the cache control circuit, a default value in response to a read request for an address in the directly addressable address range received after allocating the portion of the cache memory circuit. A system comprising: a cache memory circuit including a cache memory having a plurality of ways; a processor configured to issue memory requests using an address map including active and inactive address ranges; and a cache control circuit configured to: receive a request from the processor to reallocate a portion of the cache memory as directly addressable memory, the request identifying an inactive address range; based on the request, selecting a portion of the ways to convert; and allocating the selected portion of ways for use in the identified address range. System according to Claim 15 , wherein the cache control circuit is configured to convert the selected section of paths is to set respective indications in cache tags corresponding to particular cache lines contained in the selected section, the respective indications removing the particular cache lines from use as cache storage. System according to Claim 16 wherein the cache control circuitry is further configured to set respective real-time indicators in the cache tags corresponding to the particular cache lines, the real-time indicators indicating that the particular cache lines are associated with real-time transactions having higher priorities than volume transactions. System according to Claim 15 wherein the cache control circuit is further configured to include the selected portion of ways in caching operations in response to receiving a request to allocate the directly addressable memory, wherein data stored in the directly addressable memory while the selected portion of ways is being reallocated is not moved in response to the request to allocate the directly addressable memory. System according to Claim 15 wherein the cache control circuit is further configured to flush cache lines in the selected portion of ways prior to allocating the selected portion of ways for use in the identified address range. System according to Claim 15 , where the section of paths is one half of a special path.

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