KR20240034258A - Dynamic allocation of cache memory as RAM - Google Patents

Abstract

The device includes a cache controller circuit and a cache memory circuit further comprising a cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit currently in use. This request may identify an address area corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert one or more cache lines to directly addressable random access memory (RAM) by excluding the one or more cache lines from cache operations.

Description

Dynamic allocation of cache memory as RAM

Embodiments described herein relate to systems-on-a-chip (SoC) and, more specifically, to methods for operating cache memory.

System-on-chip (SoC) integrated circuits (ICs) typically act as central processing units (CPUs) for a system, along with various other components such as memory controllers and other agents. It includes one or more processors that play the role of. As used herein, “agent” refers to a functional circuit that can initiate or be the destination for a transaction over a bus circuit. Accordingly, general purpose processors, graphics processors, network interfaces, memory controllers, and other similar circuits may be referred to as agents. As used herein, “transaction” refers to the exchange of data between two agents over one or more bus circuits. Transactions from an agent to read data from or store data in a memory circuit are a typical type of transaction and can include large amounts of data. Memory circuits can access data within their memory cells using multiple clock cycles.

Cache memories are frequently used in SoCs to support increased performance of processors by reducing delays associated with transactions to system memories and/or non-volatile storage memories. Cache memories can store local copies of information stored at frequently accessed memory addresses. These local copies may have shorter latencies for agents to access cached values compared to performing a memory access to the target memory address. When a memory access is made to a target address that is not currently cached, the addressed memory can be accessed and values from a plurality of sequential addresses containing the target address are read as a group, then reducing future access times. It can be cached to do so. When the cached information in a cache line becomes invalid or it is determined that the cached information has not been accessed frequently, the cached information is invalidated and marked for eviction, thereby preventing other information from being accessed by the SoC's processors. It can be overwritten by:

In one embodiment, the device includes a cache controller circuit and a cache memory circuit further comprising a cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit currently in use. This request may identify an address area corresponding to one or more of the cache lines. The cache controller circuit may also be configured, in response to the request, to convert one or more cache lines to directly addressable random-access memory (RAM) by excluding one or more cache lines from cache operations.

In a further example, the cache controller circuitry is configured to support a real-time virtual channel for memory transactions in the identified address region and to prioritize memory transactions received over the real-time virtual channel over memory transactions received over the bulk virtual channel. It may be configured additionally. In one example, the cache controller circuitry can be further configured to determine that the address area is included in the secure access area. In response to the determination, the cache controller circuitry may be further configured to ignore memory transactions in the address area from agents that are not authorized to access the secure access area.

In another example, the cache controller circuit may also be configured to flush one or more cache lines prior to conversion to directly addressable RAM. In one example, the cache controller circuit can be further configured to issue a write-back request for a valid cache line in response to data in the valid cache line being written. The cache controller circuit may also be configured to exclude one or more cache lines from writeback requests.

In one embodiment, the cache controller circuit may be further configured to receive different requests to deallocate portions of cache memory from directly addressable RAM. In response to a different request, the cache controller circuit may be further configured to include one or more cache lines in cache operations without copying data stored in directly addressable RAM while the one or more cache lines are reallocated. In another embodiment, the cache controller circuit may also be configured to generate an error in response to a memory transaction in directly addressable RAM that is received after deallocating a portion of the cache memory.

The detailed description below refers to the accompanying drawings, which are now briefly described.
1 illustrates a block diagram of one embodiment of a system including a cache memory and an address map, from two viewpoints.
Figure 2 shows a block diagram of one embodiment of a system including a processor, a cache memory with multiple paths, and an address map.
Figure 3 shows a block diagram of one embodiment of the system of Figure 1 at two different viewpoints.
Figure 4 illustrates a block diagram of one embodiment of the system of Figure 1 receiving two write requests.
Figure 5 shows a block diagram of one embodiment of a system including two agents that transfer memory transactions to cache memory, via a network arbiter.
Figure 6 illustrates a block diagram of one embodiment of a system including two agents, one trusted agent and one untrusted agent, that transfer memory transactions to cache memory.
Figure 7 shows a flow diagram of one embodiment of a method for reallocating a portion of a cache memory system to a directly addressable address region.
Figure 8 shows a flow diagram of one embodiment of a method for receiving memory transactions from an unauthorized agent and deallocating a portion of a cache memory system from a directly addressable address area.
Figure 9 illustrates a block diagram of one embodiment of a system in which a buffer located in system memory is allocated to cache memory at two points in time.
Figure 10 shows a block diagram of one embodiment of the system of Figure 9 in which attempts to allocate storage locations to cache memory are repeated, at two different points in time.
Figure 11 shows a block diagram of one embodiment of a system including a processor core and a DMA that allocates buffers to cache memory.
FIG. 12 illustrates a block diagram of one embodiment of the system of FIG. 9 in which bulk transactions and real-time transactions are used with buffer and cache memory, at two different points in time.
Figure 13 shows a flow diagram of one embodiment of a method for allocating buffers to a cache memory system.
Figure 14 shows a flow diagram of one embodiment of a method for using bulk transactions and real-time transactions with buffer and cache memory.
Figure 15 illustrates a flow diagram of one embodiment of a method for determining a cache miss rate when accessing a buffer allocated to cache memory.
16 shows various embodiments of systems including coupled integrated circuits.
Figure 17 shows a block diagram of an example computer-readable medium in accordance with some embodiments.
Although the embodiments described in this disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, the drawings and detailed description thereto are not intended to limit the embodiments to the specific form disclosed; on the contrary, the intent is to make all modifications, equivalents, and modifications within the spirit and scope of the appended claims. It should be understood that it is intended to cover alternatives.

Transactions may be classified into two or more priority levels, such as “real-time” and “bulk.” Real-time transactions may have a higher priority level than bulk transactions, and therefore bus circuits and any It can be processed faster through intermediate agents. Agents can use real-time transactions to meet deadlines for completing processing that, if not met, can lead to poor performance, inaccurate calculations, or even failure in the system. For example, playback of video may stall or glitch if low latency deadlines are not met. Competition from other agents for access to bus circuits and memory circuits is one source of problems in meeting such low latency deadlines.

Cache memories store copies of memory locations closer to the corresponding agent, thereby achieving low latency deadlines by reducing the number of bus circuits and/or intermediate agents that a real-time transaction must traverse when being processed. It can be used to alleviate some of the problems of satisfying Additionally, when multiple cache memories are available, a given cache memory can be accessed by fewer agents, thereby increasing the probability that an agent can access the cache memory while meeting low latency deadlines. However, cached values may be evicted from cache memory if they are not accessed frequently and/or if there is competition from other agents to cache values in cache memory.

Accordingly, techniques are needed for storing values that are/are to be used for real-time transactions using cache memory. Two general approaches are presented herein to implement faster access memory regions using cache memory. In a first approach, a portion of the cache memory may be allocated to a system bus accessible address region, where the addressable cache memory may be accessed in a manner similar to random access memory (RAM). To implement such a technique, control circuitry can be used to allocate a portion of the cache memory as RAM. Cache lines within the allocated portion of cache memory are flushed, and any dirty data (e.g., data that has been modified in cache memory without updating corresponding memory locations in system memory) is written back to system memory. Cache lines within the allocated portion are enabled for access through the memory mapped address area and are removed from the available cache memory lines. Agents can then directly access the memory mapped address region with real-time transactions that can be processed in a similar amount of time as the cached location. Because memory mapped address areas are not treated as part of the cache during allocation, values stored in these areas are not at risk of being evicted if not accessed for extended periods of time. Figures 1-8, described below, illustrate various details of this cache-as-RAM approach.

In a second approach, a buffer is allocated within system memory, where the buffer is intended for use with low latency memory transactions. To reduce latency for accessing values within this buffer, the buffer may also be allocated to cache memory. In some embodiments, the cache may include support for high priority data, including techniques for associating specific cache lines with low latency transactions. Such support may include limiting or eliminating evictions to associated cache lines. However, cache allocations of large buffers (e.g., buffers sized for use with video frames, other images, audio files, etc.) may begin to experience cache misses, which may cause portions of the allocated buffer to be lost near the end of the cache allocation process. This is because there is a higher mapping probability for cache lines that are now occupied by portions of the buffer that were previously cached. If cache allocation starts at one end of the buffer, the opposite end will experience a higher number of cache misses, making cache misses more frequent as accesses to the buffer move toward the last portions to be allocated.

The disclosed techniques attempt to spread cache allocation of portions of a buffer across various locations within the buffer. To achieve this, the buffer can be logically divided into multiple blocks. Attempts may then be made to allocate the first subblock from each block to the cache. Subsequently, further attempts may be made to allocate a second subblock from each block to the cache. This may be repeated for a certain number of subblocks within each block until an attempt is made to cache all subblocks. Such a technique can distribute cache misses for various subblock allocations throughout the buffer so that misses are not concentrated toward the end of the buffer. For example, if a buffer is used to process an image, cache misses may occur during processing of the entire image, rather than having a few misses at the beginning of processing of the image and then more frequent misses as processing near the end of the image. It may occur more consistently across the board, but at a lower intensity. As misses occur more frequently, more real-time transactions can be created to retrieve requested data from system memory. Having a greater number of real-time transactions being processed simultaneously can increase the likelihood that low-latency deadlines will be missed, subsequently increasing the likelihood that poor performance or system failures will be experienced by users of the system. Figures 9-13, described later in this disclosure, illustrate details regarding this distributed caching approach.

1 illustrates a block diagram of one embodiment of a cache memory system from two viewpoints. As illustrated, system 100 includes cache controller circuitry 101, cache memory circuitry 105, and address map 110. Cache memory circuit 105 includes cache lines 120-127. Address map 110 is shown as having four address areas 115a through 115d (collectively, address areas 115). System 100 may correspond to a processor circuit, such as a microprocessor, microcontroller, or other type of system-on-chip (SoC). System 100 may be implemented on a single integrated circuit or by the use of multiple circuit elements combined on a circuit board.

As illustrated, the cache memory circuit 105 may include static random-access memory (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FeRAM or FRAM), magnetoresistive RAM ( It can be implemented using any suitable type of memory circuit design, such as magnetoresistive RAM (MRAM), flash memory, etc. Cache memory circuit 105 may be organized using any suitable cache structure, including the use of multiple paths and/or sets. The cache controller circuit 101 performs cache operations in the cache memory circuit 105, such as maintaining cache tags and determining whether the address associated with a memory transaction is a hit (the cache line corresponds to the current address) or a miss (no cache line circuits for determining whether an address has not been filled with data corresponding to the address, issuing cache line charge requests in response to a miss, marking cache lines for eviction, etc. Address map 110 includes any suitable combination of software, firmware, and hardware circuits for determining physical addresses for memory mapped registers and memory circuits. In some embodiments, address map 110 includes conversion tables for converting logical addresses to physical addresses.

As shown, cache controller circuit 101 receives allocation request 145 at time t0. Cache controller circuit 101 is configured to receive an allocation request 145 to reallocate a portion of cache memory circuit 105 that is currently in use. Allocation request 145 requests one of the address areas 115 (e.g., address area 115b) corresponding to one or more of the cache lines 120 to 127 (e.g., cache line 123). Identify. Cache controller circuit 101 receives allocation request 145 at time t0, at which point cache memory circuit 105 was busy and used cache lines to cache locations in system memory (not shown). One or more of the cache lines (120 to 127) may be in use. The allocation request 145 may indicate the address area 115b by including an address value corresponding to the address area 115b. In other embodiments, other forms of indications, such as an index value corresponding to the address area 115b, may be used to identify the address area 115b.

Each of the address areas 115, when active, may correspond to a plurality of addresses corresponding to memory locations within the cache memory circuit 105, such as one or more of the cache lines 120-127. there is. When a particular address area of address areas 115 is active, the corresponding cache line(s) are not used to cache data, but rather as RAM. When an address area is inactive, the corresponding cache line(s) may be used to cache data values. Addresses associated with an inactive address area may be treated as illegal addresses and, therefore, may generate an exception when included in a transaction. At time t0, address area 115b is not active (as indicated by hashing in Figure 1) and therefore no data values may be stored within the area. Address areas 115c and 115d are also inactive, while address area 115a is currently active. In some embodiments, address area 115a may correspond to main system memory and may include addresses for all memory locations and memory-mapped registers that are always enabled when system 100 is active. .

In response to allocation request 145, cache controller circuitry 101 excludes cache line 123 from cache operations, thereby converting cache line 123 to directly addressable random access memory (RAM) at time t1. It may be additionally configured to do so. Cache line 123 can then be addressed directly using memory transactions addressed to locations within address area 115b. For example, activating address area 115b may include modifying address map 110 such that transactions addressed to locations within address area 115b are routed to memory cells corresponding to cache line 123. You can. Additionally, cache controller circuit 101 may further set an indication that cache line 123 is unavailable and that no cached data is currently stored in cache line 123. For example, cache controller circuit 101 may set one or more bits providing such indications in the cache tag corresponding to cache line 123.

The use of cache-to-RAM techniques allows a process executing in system 100 to cache memory circuitry 105 for use as directly addressable RAM at any time the system is active. It may be possible to allocate a portion of . As described above, such allocation may allow a particular agent to reserve memory space with low latency access times for use with data related to high priority transactions, such as real-time transactions. Allocating this space in the cache memory circuit 105 may further prevent other agents from obtaining use of the allocated portion until a particular agent performs real-time transactions, again as cache line 123. You can deallocate that part for use.

Note that system 100 as shown in FIG. 1 is merely an example. The illustration of FIG. 1 has been simplified to emphasize features relevant to the present disclosure. Various embodiments may include additional elements and/or different configurations of elements. For example, only 8 cache lines and 4 address areas are shown. Any suitable number of cache lines and address areas may be implemented in other embodiments. Although address area 115b is shown as corresponding to a single cache line, in other embodiments, the address area may correspond to any suitable number of cache lines as well as a portion of a cache line.

The system illustrated in Figure 1 is shown in a simplified diagram. Cache memory systems can be implemented in a variety of ways. Another example of a system with cache memory is shown in Figure 2.

2, a block diagram of one embodiment of a cache memory system employing the use of paths in a cache memory circuit is shown. System 200 includes a cache controller circuit 201, a cache memory circuit 205, an address map 210, and a processor 230, as illustrated. Processor 230 may correspond to a general-purpose processing core, or another type of processing circuit capable of processing data and issuing memory requests. Except as described below, elements of system 200 perform functions as described for similarly named and numbered elements of FIG. 1 .

As shown, cache memory circuit 205 includes a cache memory having a plurality of paths 240a through 240d as well as a plurality of sets 250 through 257. Processor 230 is configured to issue memory requests using an address map 210 that includes active and inactive address regions 215. In the illustrated embodiment, address area 215m is always active when system 200 is active and may include addresses for various registers as well as main system memory. When the processor 230 issues a memory request to system memory (e.g., an address within the address area 215m), the fetch address included in the memory fetch is the fetch address of the cache line in the cache memory circuit 205. is used by the cache controller circuit 201 to determine whether it currently holds valid values for the system memory locations corresponding to . To make such a determination, cache controller circuit 201 may use the fetch address to identify a particular set among sets 250-257. For example, cache controller circuit 201 may use at least a portion of the fetch address in a hashing algorithm to determine a particular hash value. This hash value can then be used to identify a particular set of sets 250-257. Each of sets 250 - 257 includes at least one cache line from each of the paths 240 . A memory request is said to “hit” the cache memory circuit 205 if a cache line in any of the paths 240 for a particular set holds valid values corresponding to the fetch address. Otherwise, the memory request is a “miss” in the cache memory circuit 205. The use of multiple paths may allow some flexibility in how the cache controller circuit 201 maps fetched values to cache lines of the cache memory circuit 205.

As described above, cache memory circuitry 205 may provide lower latency access—also referred to as higher quality of service (QoS)—than access to system memory, such as in address region 215m. Under certain conditions, processor 230 may be required to process a block of data with a high QoS deadline. Because processing data from system memory may jeopardize successful processing of data within the limits of the high QoS deadline, the processor 230 may request that a portion of the cache memory circuit 205 be reallocated. A request 245 may be sent to cache controller circuit 201.

Cache controller circuit 201 is configured to receive an allocation request 245 from processor 230 to reallocate a portion of cache memory circuit 205 as directly addressable memory, as shown. Allocation request 245 identifies address areas 215b that are inactive at the time of receiving allocation request 245. For example, allocation request 245 may include a specific address value, or other type of indication identifying address region 215b. Based on the allocation request 245, the cache controller circuit is further configured to select a portion of the paths 240 to convert. As shown, each of the paths 240 may correspond to one of the address ranges 215, with path 240b corresponding to address region 215b, as indicated. In other embodiments, cache memory circuit 205 may include additional paths such that more than one path may be associated with a given address region. Allocation request 245 may also indicate more than one address area, such as address areas 215b and 215c. In some embodiments, a portion of paths 240 may be half or another proportion of a particular path. For example, path 240b may include multiple cache lines in each of sets 250-257, such as two lines per set. In such embodiments, one of the two cache lines from each of sets 250-257 may be reallocated, thereby leaving half of path 240b for use as a cache. , the other half is reallocated to the address area 215b.

To convert path 240b, cache controller circuit 201 may be configured to set respective indications in cache tags corresponding to specific cache lines included in the selected portion of the paths. Cache lines 250b through 257b are included in path 240b and, as shown, are selected for reallocation to address area 215b. Adding respective indications to the cache tags for each of cache lines 250b through 257b removes the corresponding cache line from use as cache memory. Such indications may cause cache controller circuit 201 to ignore cache lines 250b through 257b when determining whether a received memory request is a hit or miss in cache memory circuit 205, and cache controller circuit 201 ) can further prevent mapping an address from a cache miss to any of the cache lines 250b to 257b. Accordingly, cache lines 250b through 257b are effectively eliminated from cache memory usage while these indications in the cache tags are set.

Cache controller circuit 201 is further configured to map cache lines 250b-257b in path 240b for use in identified address region 215b. Address region 215b, as illustrated, contains a number of addresses that can be reserved for use with reallocated cache lines 250b through 257b, and thus any other memory locations or registers. It may not be mapped to . When address area 215b is inactive, attempts to access these addresses may result in the generation of an exception, and/or the return of a default value. Cache controller circuit 201 may be further configured to set respective real-time indicators to cache tags corresponding to specific cache lines 250b-257b. Such real-time indicators may indicate that cache lines 250b-257b, and therefore addresses within address area 215b, are associated with real-time transactions having higher priorities than bulk transactions. Accordingly, memory accesses to any of the reallocated cache lines 250b through 257b may be treated as real-time transactions even if real-time transactions are not explicitly used in the memory access.

Additionally, cache controller circuit 201 is further configured to flush one or more of cache lines 250b through 257b in path 240b prior to mapping path 240b for use in address region 215b. It can be configured. Because cache memory circuitry 205 may be busy before processor 230 issues allocation request 245, one or more of the cache lines in path 240b may be associated with locations within address region 215m. It can be used to cache the same memory locations. If currently cached values match values at respective locations within address area 215m, these values can be simply cleared or ignored when the respective cache line is mapped to address area 215b. . However, if a cached value in path 240b has been modified but has not yet been written back to address area 215m, then such value may be referred to as "corrupt" and corrupts system memory locations within address area 215m. A flush command can be issued to write back the values. For example, cache lines 251b, 254b, and 257b, in the illustrated example, include corrupted data. Cache controller circuit 201 issues a flush command 248 to write back the corrupted values of these cache lines to corresponding locations within address area 215m. One or more flush commands may be issued prior to converting the cache lines of path 240b to directly addressable memory locations within address area 215b.

After processing a block of data with a high QoS deadline, processor 230 may not have an immediate use for the high QoS directly addressable memory in address region 215b and requests to deallocate path 240b. It can be configured to issue. Cache controller circuit 201 may be further configured to include path 240b in cache operations in response to receiving a request to deallocate directly addressable memory in address region 215b. Values stored in directly addressable memory while path 240b was reallocated are not relocated in response to a request to deallocate directly addressable memory. Any values written to address area 215b during reallocation may be deleted or ignored and subsequently overwritten as path 240b is returned for use in the operations of cache memory circuit 205. there is.

The use of paths 240 of the cache memory circuit 205 to reallocate cache memory to directly addressable memory can be performed in an acceptable manner, while allowing operation of the cache memory circuit 205 to continue with little or no interruption. Note that it can be implemented with positive additional logic circuits. In contrast, implementing reallocation of cache memory on an individual cache line basis may require the addition of larger logic circuitry, especially if the cache memory is large and/or has many sets and paths. On the other hand, further limiting the amount of cache memory that can be reallocated may not provide an appropriate solution for managing between ongoing cache operations and the need for high QoS memory locations. For example, if reallocation of the cache memory circuit 205 is limited to half of the cache, the amount of memory allocated may be much larger than required for processing high QoS data, further reducing the capacity of the cache. This can, and possibly reduces the efficiency of agents that utilize the cache.

Additionally, note that the embodiment of Figure 2 is one depiction of a cache memory system. Although only four paths and eight sets are shown, in other embodiments any suitable number of cache paths and sets may be included. Additionally, although five address areas are shown, address map 210 may be divided into any suitable number of areas.

The description of Figure 2 describes deallocation of directly addressable memory locations. Again, deallocation of a directly addressable memory area to cache memory can be implemented in a variety of ways. Figure 3 shows such a scheme.

Referring to Figure 3, the system of Figure 1 is again illustrated from two different viewpoints. System 100 includes a cache controller circuit 101, a cache memory circuit 105, and an address map 110, as described with reference to FIG. At time t0, cache line 123 is mapped to directly addressable memory in address area 115b and is therefore unavailable for cache operations. As illustrated, cache controller circuit 101 may receive an deallocation request (e.g., from an agent, such as processor 230 of FIG. 2) to deallocate cache line 123 from directly addressable memory in address region 115b. 345). In response to deallocation request 345, cache controller circuit 101 may perform cache operations without copying data stored in directly addressable memory while cache line 123 has been reallocated to address region 115b. It is further configured to include a cache line (123). For example, as described above, cache controller circuit 101 may set an indication in the associated cache tag for cache line 123 to indicate that cache line 123 has been reallocated to directly addressable memory. . To deallocate cache line 123, cache controller circuit 101 clears this indication, thereby removing cache line 123 from address area 115b and removing cache line 123 from subsequent cache operations. ) can be included.

Values written to cache line 123 while assigned to address area 115b may be deleted or ignored when the display of the associated cache tag is cleared. Because addresses within address area 115b may not be implemented elsewhere in address map 110, no writeback requests may be issued to copy these values. Values within address area 115b are deallocated unless an agent utilizing address area 115b while active explicitly copies data from address area 115b to other locations within address map 110. may be lost after completion.

At time t1, memory transaction 350 is issued by the agent to access a value within address area 115b. Cache controller circuit 101 is configured to generate an error message 355 in response to a memory transaction 350 being received after deallocating address region 115b. In some embodiments, error message 355 may be generated when memory transaction 350 includes writing to or modifying an address within address area 115b. Alternatively, if memory transaction 350 includes only read accesses to address region 115b, cache controller circuit 101, instead of or in addition to generating error message 355, returns all zero bits. Alternatively, a specific default value, such as all 1 bits, can be returned to the requesting agent. Generating the error message 355 may be implemented using a variety of techniques. For example, error message 355 may be generated by asserting an exception signal that, in turn, causes a particular process to be executed by one or more processor cores within system 100. Generating the error message 355 may include returning a specific value indicating that the address region 115b has been deallocated to the agent that issued the memory transaction 350 .

Figure 3 shows deallocation of cache lines from a directly addressable address region. 4 , system 100 is shown as having address area 115b active (using cache line 123), and how access and cache operations to address area 115b will be handled concurrently. Shows whether it can be done. System 100, in FIG. 4, shows cache controller circuitry 101 receiving write requests 445, 446.

As shown, write request 445 includes a write request to write data to one or more locations currently cached in cache line 121 of cache memory circuit 105. In a similar manner, write request 446 is a write request to write data to one or more locations within address region 115b, which is implemented by reallocating cache lines 123 from cache memory circuit 105 to address map 110. Includes requests. Cache controller circuitry 101 is configured to issue a writeback request 447 for cache line 121 in response to write request 445 . Modified values in cache line 121 are included in writeback request 447, along with corresponding target addresses in system memory. Writeback request 447 causes these modified values to be updated at target addresses in system memory. If cache line 121 is evicted and then mapped to different addresses within system memory, the target addresses within system memory may still have the latest values.

Cache controller circuit 101 is further configured to exclude cache line 123 from writeback requests, as illustrated. Write request 446 may modify one or more values within address area 115b (including cache line 123). Despite the values within cache line 123 being modified, cache controller circuit 101 is configured to ignore these modifications with respect to writeback commands. Address area 115b, despite containing cache lines 123, is treated as an endpoint memory destination. No target address in the system memory corresponds to addresses in the address area 115b. Accordingly, modified values stored in cache line 123 may not be updated in other memory circuits in response to write request 446.

However, note that different cache memories may reside between the cache memory circuitry 105 and the processing circuitry issuing the write request 446. For example, cache memory circuitry 105 may be an L2 cache, and the processing circuitry issuing write request 446 may include an L1 cache. In such an embodiment, the L1 cache may cache at least some values stored in address area 115b (e.g., in cache line 123).

It is further noted that the embodiments of FIGS. 3 and 4 are merely examples to demonstrate the disclosed concepts. The system 100 shown in these figures is simplified for clarity. In other embodiments, additional elements may be included, such as one or more agents issuing memory transactions that result in the described operations. Additionally, although FIGS. 3 and 4 utilize system 100 of FIG. 1, the techniques described can be applied to system 200 of FIG. 2.

The use of real-time transactions, in various capacities, is described above as used with the disclosed techniques. Both real-time and bulk transactions can be used for memory requests targeting cache-based address areas described herein. Figure 5 illustrates an example of how the use of transactions with different QoS levels can be implemented.

Turning now to Figure 5, a system is shown where arbiters are used to schedule transactions across the system network. System 500 includes a cache controller circuit 501 and an address map 510, which may correspond to similarly named and numbered elements of FIGS. 1, 3, and 4, except as described below. . System 500 further includes agents 530a, 530b (collectively, agents 530), network arbiter circuitry 540, and bus circuitry 545. 5 illustrates two memory transactions (one real-time transaction and one bulk transaction, respectively) addressed to address area 515b, implemented using one or more cache lines from cache controller circuit 501, using the technique described above. The flow of transactions 550 and 555 is illustrated.

At a first point in time, agent 530b issues bulk memory transaction 555 to a destination within address area 515b. In a similar manner to address areas 115b and 215b of FIGS. 1 and 2, address area 515b includes a portion of cache memory associated with cache controller circuit 501. As illustrated, memory transaction 555 is received by network arbiter circuit 540 on its path to caching controller circuit 501. Because memory transaction 555 is a bulk transaction, network arbiter circuitry 540 transfers memory transaction 540 until bus circuitry 545 has available bandwidth to forward memory transaction 555 to cache controller circuitry 501. Place 555 in bulk queue 565a.

Bus circuit 545 includes a set of wires that couple cache controller circuit 501 to network arbiter circuit 540. In some embodiments, bus circuit 545 may include a sufficient number of wires to support independent physical bulk and real-time channels. However, as shown, bus circuit 545 does not include such a number of wires, and therefore both real-time and bulk memory transactions are conveyed using the same set of wires, utilizing virtual bulk and real-time channels. Thus, it supports individual QoS levels for each type of transaction. Accordingly, network arbiter circuit 540 uses a prioritization scheme to select between real-time (RT) queue 560a and bulk queue 565a for the next transaction to transmit over bus circuit 545. For example, network arbiter circuitry 540 may first transmit transactions in RT queue 560a and then transmit transactions in bulk queue 565a after RT queue 560a is empty. In other embodiments, additional considerations may be included in the selection process to avoid bulk queue 565a reaching a full state or causing bulk transactions to be stalled in bulk queue 565a for an excessive amount of time. may be included in

As used herein, a “channel” is a medium used to convey information between a source agent (e.g., a processor circuit) and a destination agent (e.g., a memory circuit). Channels may include wires (including conductive traces on a circuit board or integrated circuit) and various other circuit elements. In some embodiments, a channel may further include antennas and electromagnetic waves at a specific frequency or range of frequencies. A “physical” channel refers to the circuit elements that contain the channel. A “virtual” channel refers to two or more different “channels” implemented over the same physical channel. Virtual channels can be implemented using a variety of techniques. For example, channel virtualization can be implemented in the channel interface by including separate queues for each virtual channel. Agents send and receive transactions through a given channel using queues for their respective channels. Other circuits can then control channel arbitration between their respective queues to select specific transactions to transmit when the channel is available. In other embodiments, an agent may be responsible for associating various transactions to corresponding virtual channels. In such embodiments, the agent may maintain appropriate data structures to assign transactions to appropriate virtual channels and then arbitrate to select a given transaction to transmit when the channel is available.

At a second point, network arbiter circuitry 540 selects memory transaction 555 from bulk queue 565a and forwards it to cache controller circuitry 501. Cache controller circuit 501 may then place memory transaction 555 in bulk queue 565b until bandwidth is available to process memory transaction 555 in address area 515b. Meanwhile, at a third time after the second time, agent 530a transmits memory transaction 550 to cache controller circuit 501, via bus circuit 545. Network arbiter circuitry 540 receives real-time memory transaction 550 and places it in RT queue 560a. At a subsequent fourth point in time, the memory transaction 550 is selected by the network arbiter circuit 540 and sent to the cache controller circuit 501 which places the received memory transaction 550 in RT queue 560b.

In the illustrated example, both memory transactions 550 and 555 are in RT queue 560b and bulk queue 565b, respectively. Cache controller circuit 501 is configured to support real-time and bulk virtual channels for memory transactions in address areas 515a through 515d. Accordingly, the cache controller circuit 501 may use a similar selection scheme as the network arbiter circuit 540 to select memory transactions 550 received over the real-time virtual channel over memory transactions 550 received over the bulk virtual channel. Prioritize. At the fifth time point, after the fourth time point, the cache controller circuit 501 skips the memory transaction 555 waiting on the bulk queue 565b and instead selects the memory transaction 550 waiting on the RT queue 560b. do. Thereafter, at a sixth point in time, memory transaction 555 satisfies the selection criteria and is processed in address area 515b.

Note that system 500 is an example for highlighting the disclosed methods. Figure 5 is simplified for clarity. In other embodiments, additional elements may be included, such as additional agents, multiple bus circuits, associated network arbiter circuits, etc.

Figure 5 illustrates how memory transactions with different levels of QoS can be handled using the disclosed techniques. The disclosed cache controller circuit can be further configured to manage address areas within different types of secure memory areas. A description of such an embodiment is presented next.

Referring to Figure 6, an embodiment of a system is shown that includes support for open-access and secure access memory regions. System 600 includes a cache controller circuit 601, an address map 610, a system memory map 620, a trusted agent 630, and an untrusted agent 635. System memory map 620 is divided into two regions, as shown, open access region 623 and secure access region 627. Address area 615b in address map 610 corresponds to reallocated cache memory and is mapped within secure access area 627, as described above. Trusted agent 630 and untrusted agent 635 issue memory transactions 650 and 655, respectively, both targeting a destination address in address area 615b.

System memory map 620, as illustrated, includes a memory map of all address areas included in system 600. These address areas can be classified into two types of security areas: open access area 623 and secure access area 627. The open access area includes all memory ranges in which any agent within system 600 (including both trusted agents 630 and untrusted agents 635) can issue memory transactions. The open access area may include memory used for general application use, including, for example, memory used for processing images, audio files, and execution of general applications. Secure access area 627 contains memory ranges with restricted access. Only agents classified as trusted, such as trusted agent 630, can access memory locations within secure access area 627. Memory transactions from untrusted agents to addresses within the secure access area 627 may be ignored, or may result in the generation of an error indication, such as an exception.

In the illustrated example, both trusted agent 630 and untrusted agent 635 issue their respective memory transactions 650, 655 to destination addresses within address area 615b. To support secure access areas, cache controller circuitry 601 is configured to determine that address area 615b is included in secure access area 627. In response to the determination, cache controller circuitry 601 is configured to ignore memory transaction 655 from an untrusted agent 635 that is not authorized to access secure access area 627. However, trusted agent 630 is authorized to access secure access area 627, and therefore cache controller circuitry 601 is configured to process memory transaction 650 in address area 615b.

In response to receiving memory transaction 655, cache controller circuit 601 may be further configured to generate an error indication. For example, cache controller circuit 601 may return an error code to untrusted agent 635, where the error code includes a specific value indicating access to an unauthorized address. Cache controller circuit 601 may instead or additionally be further configured to assert one or more exception signals, such as an illegal address exception and/or a security violation exception.

Note that system 600 is only an example. Various elements may be omitted from system 600 for clarity. In other embodiments, system 600 may include additional secure access zones. For example, a plurality of different secure access areas may be implemented, with each area corresponding to a different level of security access and therefore accessible by different combinations of trusted agents.

The circuits and techniques described above with respect to Figures 1-6 describe various techniques for reallocating portions of cache memory to directly addressable address areas. A variety of methods may be utilized to implement these disclosed techniques. Two such methods are described below with reference to FIGS. 7 and 8.

Referring now to Figure 7, a flow diagram is shown for one embodiment of a method for reallocating a portion of a cache memory circuit to a directly addressable address region. Method 700 may be performed by a cache controller circuit, such as cache controller circuits 101, 201, 501, and 601 of FIGS. 1, 2, 5, and 6, respectively. Method 700 may be performed by processing circuitry executing software or firmware, by hardware circuits including, for example, logic gates, or a combination thereof. Referring collectively to Figures 1 and 7, method 700 begins at block 710.

At block 710, method 700 receives, by cache controller circuit 101, an allocation request 145 to reallocate a portion of cache memory circuit 105 currently in use into directly addressable memory space. Includes steps. As shown, allocation request 145 identifies inactive address area 115b. Allocation request 145 may be received at time t0, at which point cache memory circuitry 105 was busy and one or more of cache lines 120-127 were busy caching locations in system memory. may be in use for The address area 115b may be indicated by including an address value within the address area 115b or an index value corresponding to the address area 115b at the time of the allocation request 145.

The method 700 further includes selecting, at block 720, a cache line 123 of the cache memory circuit 105 to convert based on the identified address region 115b. As illustrated, cache line 123 may be associated with address area 115b due to software executing on system 100, such as an operating system. In other embodiments, cache lines 123 may be hardcodes to address area 115b based on the circuit design of system 100. Although only one cache line is shown as being selected for use in address area 115b, any suitable number of cache lines may be selected. For example, as described with reference to Figure 2, a cache memory circuit may include multiple paths, and either an entire path or multiple paths may be selected for use in a directly addressable address region.

At block 730, the method 700 further includes setting, by the cache controller circuit 101, a respective indication for the selected cache line 123 to exclude the cache line 123 from further cache operations. Includes steps. For example, cache controller circuit 101 may set a particular bit or group of bits in the cache tag corresponding to cache line 123 to indicate use of cache line 123 within address area 115b. Additionally, cache controller circuit 101 may set a real-time memory indicator to indicate that cache line 123 is associated with real-time transactions that have higher priorities than bulk transactions. Such an indication may prevent the cache controller circuit 101 from performing eviction of the contents of the cache line 123 after it has been reallocated to the address area 115b. The real-time indication may further prioritize any transactions with addresses within address area 115b as destinations over any bulk transactions in the queue for cache controller circuitry 101.

In some embodiments, method 700 may further include flushing, by cache controller circuit 101, cache line 123 prior to setting the respective indication. Because the cache memory circuit 105 was in use prior to receipt of the allocation request 145, valid data may be cached in cache line 123. If any value cached in cache line 123 has been modified and this modification has not been written back to a destination location in system memory, a writeback request is made to any location that has modified values currently cached in cache line 123. A flush command that generates a flush command may be issued by the cache controller circuit 101. After writeback requests are issued, cache line 123 may be available for use in address area 115b.

The use of a portion of cache memory as a directly addressable address area allows memory accesses with high QoS deadlines that may not be achievable by direct accesses to system memory, even if typical caching techniques are employed for system memory accesses. This may enable a range of low-latency memory that can be used by specific agents to perform tasks. By creating low-latency memory regions using cache memory circuits, a particular agent can buffer data to be processed in these low-latency memory regions without risking the buffered data being evicted from the cache if not accessed within a certain time frame. can do.

While address region 115b is active, cache lines 120-122 and 124-127 may be used for cache operations in cache memory circuit 105. For example, data written to a specific address that is currently cached in the cache memory circuit 105 may be written back to a specific address in the system memory. However, cache line 123 is not used for cache operations. For example, data written to a different address in the cache line 123 in the address area 115b is not written back to the system memory. Instead, cache line 123 may be used as the final destination for data written to address area 115b.

Method 700 may end at block 730 or may repeat some or all of the operations. For example, method 700 may return to block 710 in response to another allocation request being received by cache controller circuitry 101. In some embodiments, multiple instances of method 700 may be performed simultaneously. For example, cache controller circuitry 101 may process a second allocation request while still performing the first allocation request. If system 100 includes multiple cache controller circuits (e.g., for respective cache memory circuits), each cache controller circuit may perform method 700 in parallel. Note that the method of Figure 7 is only an example for allocating a portion of the cache memory as a directly addressable address area.

Referring now to Figure 8, a flow diagram is shown for one embodiment of a method for operating and deallocating a directly addressable address region utilizing a portion of cache memory. In a similar manner to method 700, method 800 includes cache controller circuits such as cache controller circuits 101, 201, 501, and 601 as shown in FIGS. 1, 2, 5, and 6, respectively. It can be performed by . Method 800 may also be performed by processing circuitry executing software or firmware, by hardware circuitry, or a combination thereof. Referring collectively to Figures 1, 3, and 8, method 800 begins at block 810, where cache line 123 has already been reallocated to address area 115b.

The method 800 includes, at block 810, receiving, by the cache controller circuit 101, a memory transaction for the address area 115b from an unauthorized agent. As described above with reference to Figure 6, the system memory map for system 100 may include an open access area and one or more secure access areas. Various agents may attempt to access address area 115b, some of which may be authorized to access one or more of the secure areas, while other agents may attempt to access any addresses except those within the open access area. may not have approval for it.

At block 820, method 800 causes cache controller circuitry 101 to ignore memory transactions from unauthorized agents in response to determining that address region 115b is part of a secure access region. Includes steps. As illustrated, the address included in the received memory transaction targets a location within address area 115b. Address region 115b may be determined to be within a secure access region of the system memory map that is not accessed by unauthorized agents. In response to this decision, the received memory transaction is ignored. As described above, an error message may be returned to the unauthorized agent and/or an exception signal may be asserted to indicate, for example, to an operating system, that unauthorized access has been attempted.

At block 830, the method also includes a deallocation request 345 to deallocate, by the cache controller circuit 101, the cache line 123 of the cache memory circuit 105 from the directly addressable address region 115b. It includes the step of receiving. An agent that was using address area 115b may complete the activities that initiated the request to reallocate cache line 123 to address area 115b. For example, the processor may have requested activation of address area 115b in response to initiation of a specific application or process within the application. Once the application or process has completed, the address area 115b may not be needed and is therefore returned to use by the cache memory circuit 105, thereby increasing the amount of data that can be cached at any given time. You can.

The method 800 further includes, at block 840, including cache line 123 in cache operations in response to deallocation request 345. As illustrated, cache line 123 is returned to cache memory circuit 105 for use as cache memory. For example, if one or more bits in the cache tag corresponding to the cache line 123 are set to include the cache line 123 in the address area 115b, these bits are used to connect the cache line 123 to the cache memory circuit 105. ) can be cleared to return to ). Data stored in the address area 115b while the cache line 123 was reallocated can be overwritten without writeback to the system memory circuit. Values stored in address area 115b may need to be explicitly copied to other memory locations through the use of respective memory transactions before cache line 123 is deallocated. Otherwise, any values from address area 115b may be lost after deallocation.

The method further includes, at block 850, returning a default value in response to a read request for an address within the address region 115b received after deallocating the cache line 123 of the cache memory circuit 105. Included as. As illustrated, when memory transaction 350 is directed to an address within address region 115b after deallocation request 345 is performed, a default value indicating an access to an inactive address causes memory transaction 350 to be It is returned to the issuing agent.

At block 860, the method 800 also includes generating an error by the cache controller circuit 101 in response to a write request for an address in the address region 115b received after deallocation. In addition to block 850, or in some embodiments, instead of block 850, an error, such as an assertion of an exception signal, may be generated. Such an error may provide an indication to the supervisory processor, security circuit, exception handler circuit or process, and/or other hardware circuits or software processes that an access to an inactive address has been made. In some cases, such access may indicate an improper operating system and initiate recovery actions such as a system reset or exception routine.

In some embodiments, method 800 may end at block 860, or in other embodiments, may repeat some or all of the operations. For example, the method 800 may return to block 830 to deallocate a different address region in response to a different deallocation request. Note that the operations of method 800 may be performed in whole or in part in a different order. For example, blocks 810 and 820 may be performed one or more times before block 830 is performed at an initial time. Blocks 830 to 860 may be performed without blocks 810 and 820 being performed.

Performance of the various operations of methods 700 and 800 may be performed simultaneously and/or in an interleaved manner. For example, cache controller circuit 101 may be configured to manage multiple address areas simultaneously, thereby allowing different processor circuits to utilize different directly addressable address areas in an overlapping manner. Accordingly, method 800 may be performed in whole or in part while method 700 is in progress.

1-8 illustrate various embodiments of a cache-as-RAM technique in which a portion of the cache memory is allocated to a system bus accessible address region, thereby enabling a low-latency memory region for a given agent or group of agents. do. Figures 9-15, described below, illustrate a distributed buffer technique in which buffers are allocated within system memory and then allocated to cache memory using a specific order that attempts to distribute cache misses across the buffer.

Turning to Figure 9, a block diagram of one embodiment of a system including cache memory is illustrated from two perspectives. As shown, system 900 includes processing circuitry 901, cache memory circuitry 905, and system memory circuitry 910. Cache memory circuit 905 includes cache lines 920a through 920h (collectively, cache lines 920). System memory circuit 910 is shown as having nine storage locations 935a - 935i (collectively, locations 935). System 900 may correspond to a processor, such as a microprocessor, microcontroller, or other type of system-on-chip (SoC). System 900 may be implemented on a single integrated circuit or by the use of multiple circuit elements combined on a circuit board.

As illustrated, processing circuit 901 may be a processor core within a single or multi-core processor complex. System 900 may include a non-transitory computer-readable medium having instructions executable by processing circuit 901 to perform operations described below with respect to FIGS. 9-15. Such non-transitory computer-readable media may include non-volatile memory circuits included in and/or coupled to system memory circuitry 910. Non-volatile memory circuitry may include, for example, flash memory arrays, solid state drives, hard disk drives, universal serial bus (USB) drives, optical disk drives, floppy disk drives, etc. System memory circuit 910 and cache memory circuit 905 may each include one or more types of RAM, such as SRAM, DRAM, etc.

Processing circuit 901 is configured to assign storage locations 935 within system memory circuit 910 of system 900 to buffer 915, as shown. In various embodiments, processing circuitry 901 and/or other agents within system 900 (not shown) may use buffer 915 to process information related to applications running on system 900. there is. To meet the desired performance of the present application, access to buffer 915 may have specific quality of service (QoS) requirements. To increase the probability of meeting QoS needs, processing circuitry 901 is further configured to assign storage locations 935 to cache memory circuitry 905. Accesses to cache memory circuitry 905 may typically have a higher QoS level than accesses to system memory circuitry 910.

To assign the buffer 915 to the cache memory circuit 905, the processing circuit 901 is configured to select a specific order for assigning the storage locations 935 to the cache memory circuit 905. This specific ordering can increase the uniformity of cache miss rates compared to linear ordering. Assigning storage locations 935 in a linear order, e.g., starting with assigning location 935a and proceeding sequentially through storage locations 935b, 935c, 935d, etc., to storage location 935i This may result in cache misses occurring more frequently for storage locations at the end of buffer 915. For example, storage locations 935g, 935h, 935i may have a higher probability of being unallocated due to the corresponding cache line having already been assigned to a different storage location. Accordingly, the cache memory circuit 905 allocates storage locations 935 in a more fair manner that increases the likelihood that locations at the end of the buffer 915 can be successfully assigned to the cache memory circuit 905. A specific order for performing allocations of storage locations 935 is selected.

After the specific order is selected, the processing circuit 901 is further configured to cache the storage locations among the storage locations 935 of the buffer 915 within the cache memory circuit 905 in the specific order. In some embodiments, processing circuitry 901 may be further configured to select and assign subsets of storage locations 935, each having multiple storage locations, rather than selecting and assigning individual storage locations.

As an example, at time t0, processing circuitry 901 allocates buffer 915 containing storage locations 935 to system memory circuitry 910. At time t1, the processing circuitry 901 is configured to segment the buffer 915 into a plurality of blocks based on a specific order. These plurality of blocks correspond to storage locations 935 and have a serial logical order as shown.

Each storage location 935 may contain any suitable number of bytes of system memory circuitry 910, such as 1 byte, 16 bytes, 128 bytes, etc. In some embodiments, different storage locations 935 may contain different numbers of bytes. For this example, one storage location 935 has the same number of bytes as one cache line 920. The sizes for storage locations 935 may be determined by processing circuitry 901 based on a specific order. As shown, buffer 915 is divided into nine storage locations, and the specific order includes assigning every third storage location, starting with storage location 935a, followed by 935d, and then 935g. . The order wraps back to storage location 935b, then 935e, and then 935h. The final three storage locations are then assigned, starting with 935c, followed by 935f, and ending with 935i.

The processing circuitry 901 is further configured to cache the storage locations 935 using increments to select storage locations among the storage locations 935 in a specific order that is different from the serial order. In the illustrated example, this increment is 3, but any suitable number may be used. Storage location 935a is assigned to cache line 920c, followed by storage location 935d to cache line 920f, and then 935g to cache line 920h. Cache memory circuit 905 is configured to map a given storage location 935 to a corresponding cache line 920 based on a specific system address contained in the given storage location 935, as shown. For example, cache memory circuitry 905 may perform a hash of a particular address or a portion thereof, and the resulting hash value may be used to map the particular address to a corresponding cache line 920. Because the cache memory circuit 905 may be much smaller than the system memory circuit 910, two different system addresses may result in hash values being mapped to the same cache line 920. In such a case, the second of the two addresses may not be assigned.

In the example of Figure 9, storage locations 935b, 935f, and 935i are mapped to cache lines 920h, 920e, and 920c, respectively. However, these three cache lines 920 have already been assigned to storage locations 935a, 935h, and 935g, respectively. Therefore, the storage locations 935b, 935f, and 935i cannot be assigned. As shown by the italic, bold text in buffer 915, unallocated storage locations are spread throughout buffer 915. Then, when the contents of buffer 915 are traversed by the agent in a logical order starting at storage location 935a, cache misses occur one at a time, separated by two or more cache hits before reaching the next cache miss. do.

However, if storage locations 935 had been assigned in the same linear order as buffer 915 was traversed, storage location 935b would have been assigned rather than storage location 935g, and storage location 935f would have been assigned storage location ( 935h) would have been assigned instead. This would have resulted in all of the storage locations (935g, 935h, 935i) being unallocated. In this scenario, when the agent traverses buffer 915, three cache misses occur in the row at the end of buffer 915, with no cache hits between the misses. Three fetches to system memory circuit 910 in a row may cause delays because the second and third fetches may have to wait for previous fetches to be processed. Accordingly, allocating buffers 915 using a specific order rather than a linear order may reduce the overall time to traverse through buffers 915.

After allocation of the buffer 915 to the cache memory circuit 905 is complete, the processing circuit 901, or other agents within the system 900, use the cache memory circuit (915) as a low-latency path for the values stored in the buffer 915. 905) can be accessed. Locations 935 that have been successfully cached may provide faster access to the contents of buffer 915 compared to direct access to locations 935 within system memory circuitry 910.

Note that the embodiment in Figure 9 is merely illustrative. 9 includes only elements for illustrating the disclosed techniques. In other embodiments, additional embodiments may be included. For example, one or more bus circuits, memory management units, etc. may be included in other embodiments. The number of cache lines and storage locations is limited for clarity. In other embodiments, any suitable number of cache lines and storage locations may be included.

In the description of Figure 9, failure to successfully allocate a location for a buffer is briefly discussed. If a particular location in the buffer maps to a cache line that has already been assigned to a different location in the buffer, the allocation fails. In some embodiments, a specific location within the buffer may be mapped to a cache line that is currently assigned to a different location in system memory that is not associated with the buffer. A technique for handling such cases is now presented.

Referring now to Figure 10, a block diagram of one embodiment of system 900 of Figure 9 is again illustrated from two viewpoints. As shown, system 900 is identical to that shown in Figure 9, except that the cache memory circuit is shown as having four additional cache lines, namely cache lines 920i through 920l. . As mentioned above, cache memory circuit 905 is shown in Figure 9 as having a limited number of cache lines for clarity. In various embodiments, cache memory circuit 905 may include any suitable number of cache lines, including, for example, additional cache lines beyond the 12 shown in FIG. 10 . Processing circuit 901 is shown assigning storage locations 935b, 935e, 935h of buffer 915 to cache memory circuit 905. At time t0, processing circuitry 901 attempts to assign storage location 935b to cache line 920k.

As shown in Figure 9, storage location 935b has been mapped to cache line 920h that was previously assigned to storage location 935g of buffer 915. In the embodiment of Figure 10, storage location 935b may be further mapped to cache line 920k. For example, cache memory circuitry 905 may be set associative and may include multiple paths, allowing a given system memory address to be mapped to two or more cache lines 920 . Accordingly, cache line 920k may be in a different path than cache line 920h, thereby providing an alternative cache line to assign storage location 935b.

However, cache line 920k is assigned, at time t0, to storage location 1035y, which may be a location in system memory circuit 910 that is not associated with buffer 915. In response to a failure to cache storage location 935b in cache line 920k, processing circuitry 901 is configured to retry caching storage location 935b before caching a different storage location. As shown, processing circuit 901 generates a new allocation request to cache storage location 935b. In some embodiments, processing circuitry 901 may include a specific amount of delay or number of instruction cycles or bus cycles between the original attempt to allocate storage location 935b and a retry.

At time t1, storage location 1035y can be evicted from cache line 920k, and thus storage location 935b can be successfully cached in cache line 920k. Subsequently, processing circuitry 901 may further attempt caching of storage location 935e, followed by storage location 935h.

By retrying the cache allocation attempt for storage location 935b, processing circuitry 901 may increase the number of storage locations in buffer 915 that are successfully cached. The more storage locations of buffer 915 that can be assigned to cache memory circuit 905, the better the probability of meeting the QoS needs of the application that will utilize buffer 915.

Note that the system 900 shown in FIG. 10 is an example to demonstrate the disclosed techniques. Only elements intended to illustrate these techniques are illustrated. As discussed above, additional elements may be included in other embodiments, such as additional cache lines and storage locations, as well as additional processing circuits and other bus and memory management circuits.

The system of Figure 9 illustrates the processing circuitry as performing many of the actions associated with caching storage locations in the cache memory circuitry. Various types of processing circuits may be utilized to perform such actions. One such processing circuit includes a direct-memory access (DMA) circuit such as that shown in FIG. 11.

Referring now to Figure 11, one embodiment of a system is shown that includes DMA circuitry for caching buffers of system memory in cache memory. System 1100 includes a processor core 1190 coupled to a DMA circuit 1101, which is further coupled to a cache memory circuit 905 and a system memory circuit 910. In various embodiments, the DMA circuit 1101, the processor core 1190, or a combination of the two may correspond to the processing circuit 901 of FIGS. 9 and 10.

Processor circuit 1190 may be a general-purpose processor that performs computational operations. In some embodiments, processor core 1190 may be a special-purpose processing core, such as a graphics processor, audio processor, or neural processor. Processor core 1190 may, in some embodiments, include a plurality of general-purpose and/or special-purpose processor cores, as well as support circuits for managing power signals, clock signals, memory requests, etc. there is. DMA circuitry 1101 is configured to issue memory transactions to copy or move values between various memory addresses across the memory map of system 1100, as shown. DMA circuit 1101 may be implemented as a specialized circuit, a general-purpose circuit programmed to perform such tasks, or a combination thereof. DMA circuit 1101 is programmable by at least processor core 1190, so that it can perform multiple memory transactions in a desired sequence.

As described above, processing circuit 901 selects a particular order for caching storage locations in buffer 915 into cache memory circuit 905. As shown in system 1100, selecting a particular order may be performed by processor core 1190, for example, based on the size of buffer 915 and/or availability of cache lines within cache memory circuit 905. ) is performed by. Processor core 1190 programs a specific order into DMA circuitry 1101 and uses DMA circuitry 1101 to cache storage locations among storage locations 935 of buffer 915 within cache memory circuitry 905. It is configured to do so. For example, the DMA circuit 1101 may include providing a specific order for the processor core 1190 to issue memory transactions corresponding to one of the storage locations 935 . ) and destination addresses for caching the storage locations 935 in the cache memory circuit 905.

As illustrated, processor core 1190 is further configured to track the cache miss rate in cache memory circuit 905 for memory transactions involving accesses to storage locations 935. After buffer 915 is allocated to cache memory circuit 905, processor core 1190, or a different agent within system 1100, may issue various memory transactions accessing one of the storage locations 935. You can. Depending on how many of the storage locations 935 are successfully assigned to the cache memory circuit 905, a specific cache miss rate will be determined for those memory transactions targeting addresses within the storage locations 935. You can. For example, if 10% of the storage locations 935 are unallocated, and the storage locations 935 are equally accessed by a particular agent using the buffer 915, the cache miss would be at or near 10%. will be. However, if a particular agent accesses certain of the storage locations 935 more frequently than others, the cache miss rate may be greater than 10% depending on whether the more frequently accessed storage locations are successfully allocated. It could be higher or it could be lower.

In response to determining that the tracked cache miss rate satisfies the threshold rate, processor core 1190 may be further configured to modify a particular order in DMA circuitry 1101. For example, if the critical miss rate is 15% and the tracked miss rate is 18%, processor core 1190 can identify storage locations 935 that were not cached but were frequently targeted in memory transactions. In addition, it is possible to identify successfully cached storage locations 935 that were not frequently targeted. The modified order adjusts the order for allocating these identified storage locations so that more frequently accessed locations are allocated sooner in the modified order and less frequently accessed locations are moved toward the end of the modified order. can do. When subsequent buffers need to be allocated to the cache memory circuit 905, a modified order may be selected beyond the original specific order. In some embodiments, various orders may be determined and associated with specific agents, tasks, processes, etc., such that the selected order for allocation takes into account past performance of similar tasks.

With regard to determining the allocation order, a technique is disclosed above in which subsequent storage locations are selected using specific increments between successive locations. 11 , a technique that includes partitioning the buffer 915 into a plurality of blocks 1130a - 1130c (collectively, blocks 1130) each having a respective series of adjacent storage locations 935. This is illustrated. The nine illustrated storage locations 935 are divided into three blocks 1130, with each block 1130 containing three consecutive storage locations 935. Although blocks 1130 are shown as containing the same number of storage locations 935 per block, in other embodiments, the number of storage locations 935 included in each block 1130 may vary. You can. For example, the usage for buffer 915 may be known, and based on the known usage, certain storage locations 935, or groups of locations, may be known to be accessed infrequently, while others may be more frequently accessed. It is known to be easily accessed. Accordingly, the number of storage locations 935 assigned to each block may be adjusted, for example, such that the initial storage location 935 for each block is a location that is known to be accessed more frequently.

After the storage locations 935 are divided into respective blocks 1130, the processor core 1190 stores the first storage location 935 of each series of blocks 1130 in a cache memory circuit ( 905), and then to allocate the second storage location 935 of blocks 1130. As shown, block 1130a includes an initial storage location 935a, followed by storage locations 935c, 935c. Similarly, block 1130b includes an initial storage location 935d followed by storage locations 935e and 935f, while block 1130c includes an initial storage location 935g followed by storage locations 935h and 935i. Includes.

In the first pass, processor core 1190 causes DMA circuitry 1101 to cache the initial storage location from each of blocks 1130, namely storage locations 935a, 935d, and 935g. Subsequently, the DMA circuit 1101 caches a second storage location (storage locations 935b, 935e, 935h) from each block 1130 in a second pass and then in a third pass, respectively. Cache the third location (storage locations 935c, 935f, 935i) from block 1130 of .

As mentioned above, processor core 1190 may modify certain orders based on monitored cache miss rates. These modifications may include adjusting the number of locations included in each block, the number of locations stored at a time from each block, or the order for assigning locations within each block. For example, processor core 1190 may determine at block 1130b that storage location 935e is accessed more frequently than storage location 935d. In the modified order, the initial storage location allocated from block 1130b may be 935e rather than 935d.

Note that system 1100 is only an example. Figure 11 has been simplified for clarity. Although nine storage locations and three blocks are shown, buffer 915 may include any suitable number of storage locations, and these locations may be divided into any suitable number of blocks. The number of locations included in each block may vary between blocks. Additionally, the number of positions from each block assigned at any given time may vary between passes.

Various types of QoS levels are discussed in conjunction with Figures 1-8. Transactions used to cache buffers from system memory to cache memory may also utilize different QoS levels for different tasks. Figure 12 illustrates the use of bulk and real-time transactions by the disclosed techniques.

Turning now to Figure 12, one embodiment of the system 900 from Figures 9 and 10 is shown at two different times: during buffer allocation to the cache and during use of the allocated buffer. System 900 includes elements as previously shown in FIGS. 9 and 10 . Additionally, the cache memory circuit 905 and the system memory circuit 910 are configured to support bulk and real-time channels 1240 and 1245, respectively. In some embodiments, bulk and real-time channels 1240, 1245 may utilize separate physical connections between various agents and memory circuits to complete their respective transactions. In other embodiments, at least a portion of real-time channel 1245 and bulk channel 1240 are shared and, in some embodiments, may be implemented as virtual bulk and real-time channels as described above.

At time t0, buffer 915 is cached in cache memory circuit 905. In this embodiment, buffer 915 is a real-time buffer. “Real-time buffer,” as used herein, refers to a memory buffer that real-time transactions primarily use to access locations in the buffer. Real-time buffers may be used with agents and/or tasks, where failure to meet certain QoS demands may result in inappropriate behavior of the agent or task. For example, processing frames of video for playback needs to be completed within a certain amount of time, otherwise video playback may produce freezes or glitches that are noticeable to the viewer.

Although buffer 915 is a real-time buffer, the initial allocation of buffer 915 to the cache may not be time sensitive. Accordingly, caching the storage locations 935 of the buffer 915 is performed using bulk transactions 1242 across the bulk channel 1240 to store the plurality of storage locations 935 in the cache memory circuit 905. ) can be assigned to. As shown at time t0, bulk channel 1240 carries bulk transactions 1242a, 1242b, and 1242c to allocate storage locations 935a, 935d, and 935g, respectively, in cache memory circuit 905. It is used. During this buffer allocation task, the agent that would be using buffer 915, i.e., processing circuit 901, may not have values ready to read from or write to buffer 915, for example. Accordingly, bulk transactions 1242 may be used to allocate buffer 915.

However, since buffer 915 is expected to be used with real-time transactions, bulk transactions 1242 may be stored in successfully cached storage locations 935, indicating that these cached storage locations are associated with real-time transactions. It may include a sign having . For example, the cache tags associated with each successfully cached storage location 935 may have a specific bit or group of sets of bits indicating that the associated cache line 920 will be used with real-time transactions. Cache lines 920 that have real-time indications in their respective cache tags may receive higher priority when cache lines are identified for eviction. For example, when a certain number of cache lines 920 in the cache memory circuit 905 reaches a threshold level, e.g., approaching a certain percentage of maximum storage capacity, cache lines 920 that have not been accessed frequently Certain cache lines in the cache may be selected for eviction. Cache lines 920 with a set of real-time indications may be omitted from consideration for eviction, or may be placed very low in the order for selection, e.g., at a higher level where other cache lines will be selected for eviction. There will be possibilities.

Cache memory circuitry 905 may also reserve a certain amount of bandwidth for fetching data from system memory circuitry 910 in response to cache misses associated with real-time memory transactions. Cache memory circuitry 905 may limit the number of bulk transactions issued and active at any given time to ensure that bandwidth is maintained for issuing real-time transactions. For example, bus circuits between cache memory circuit 905 and system memory circuit 910 may include a credit-based arbiter circuit. In order for an issued transaction to be selected by this arbiter circuit, the cache memory circuit 905 may need to maintain a certain number of bus credits. In such an embodiment, cache memory circuitry 905 may delay issuing a bulk transaction if the number of bus credits is at or near a certain number. Bulk transactions may be transmitted after the cache memory circuit 905 has accumulated a sufficient number of bus credits.

At time t1, buffer 915 has been assigned to cache memory circuit 905. As indicated by the bold italic text, locations 935f and 935i were not cached successfully. For example, storage locations 935f and 935i may have been mapped to cache lines 920i and 920l, which were previously assigned to storage locations 1235x and 1235y, respectively. Processing circuitry 901 is further configured to access successfully cached storage location 935c using real-time transaction 1250a. Cache memory circuit 905 may be configured to process real-time transaction 1250a using values stored in cache line 920a.

Cache memory circuitry 905 is configured to generate fetch requests to system memory circuitry 910 in response to a cache miss associated with a respective memory transaction, the generated fetch requests having a QoS level compatible with the corresponding memory transaction. . For example, cache memory circuitry 905 may generate bulk fetches 1265a, 1265b in response to bulk transactions from a given agent. Processing circuitry 901 may be further configured to access unsuccessfully cached storage location 935f using real-time transaction 1250b. Cache memory circuitry 905 is configured to perform real-time transaction 1250b using real-time fetch 1290 in response to a cache miss for storage location 935f. Because the cache memory circuit 905 is configured to reserve bandwidth for real-time fetches, a real-time fetch may be processed before other bulk fetches that have not been issued. For example, bulk fetch 1265b may be queued waiting for bulk fetch 1265a to complete. If real-time fetch 1290 is generated before bulk fetch 1265b is issued, real-time fetch 1290 may be processed prior to bulk fetch 1265b.

Use of such real-time and bulk QoS levels can reduce access times for the agent using the real-time buffer allocated to cache memory. Use of a real-time QoS level can also reduce memory access times in the event that part of the real-time buffer is not allocated to the buffer.

Note that the embodiment in Figure 12 is an example used for demonstration purposes. For clarity, the number of elements shown in Figure 12 has been minimized. Although the number of storage locations and cache lines is illustrated, any suitable number of storage locations and cache lines may be included in other embodiments. Although only real-time and bulk transactions are shown, any suitable number of QoS levels may be used in other embodiments.

The circuits, processes, and techniques described above with respect to FIGS. 9-12 describe various techniques for allocating buffers in system memory to cache memory. Various methods can be used to implement these various techniques. Three such methods are described below with reference to Figures 13-15.

Referring now to Figure 13, a flow diagram is shown for one embodiment of a method for caching a buffer within system memory in a cache memory circuit. In various embodiments, method 1300 is performed by processing circuit 901 of FIGS. 9, 10, and 12 as part of a process for caching buffer 915 within cache memory circuit 905. It can be. For example, processing circuit 901 may include (or be accessible to) a non-transitory computer-readable medium having stored program instructions executable by the processing circuit to cause the operations described with reference to FIG. 13. ). Referring collectively to Figures 9 and 13, method 1300 begins at block 1310.

At block 1310 , method 1300 includes allocating, by processing circuitry 901 , a plurality of storage locations 935 within system memory circuitry 910 to a buffer 915 . As shown, processing circuitry 901, or different agents within system 900, may have buffers 915 allocated in system memory circuitry 910 for use with the particular process or task the agent is preparing to perform. You can request. For example, tasks may involve processing images, audio files, encrypting or decrypting files, analyzing input from sensors, etc. In some embodiments, buffer 915 may be a real-time buffer that accesses storage locations 935 using real-time transactions. As described above, real-time transactions have a higher QoS level than other transactions such as bulk transactions.

Method 1300 further includes, at block 1320, determining a specific order for assigning storage locations 935 to cache memory circuit 905. This specific ordering may be chosen to increase uniformity of cache miss rates compared to the use of a linear ordering. As described above, allocating storage locations 935 using a linear sequence can result in storage locations 935 near the start of the linear sequence being cached successfully, while stores at the end of the linear sequence Locations 935 are not cached successfully due to being mapped to the same cache lines 920 as previously cached storage locations 935 . If the data in buffer 915 is accessed from storage locations 935 in the same order in which they were assigned, more cache misses would be expected as processing moves toward the end of the sequence. Accordingly, a specific order is selected so that caching occurs in an order that attempts to evenly distribute cache misses during use of buffer 915. Accordingly, during use of buffer 915, cache misses may not be concentrated during any particular portion of buffer accesses.

At block 1330, method 1300 also includes caching storage locations 935 of buffer 915 using a particular order. After a specific order for assigning storage locations 935 is selected, processing circuitry 901 begins assigning storage locations among storage locations 935 to cache memory circuitry 905. In some embodiments, as shown in FIG. 10 , method 130 may, in response to failure to cache a particular storage location 935 (e.g., storage location 935b), cache a storage location 935e, such as storage location 935e. This may include retrying caching of storage location 935b before caching a different storage location 935.

Method 1300 may end at block 1330. In some embodiments, at least a portion of method 1300 may be repeated. For example, method 1300 may repeat in response to receiving a request to allocate a different buffer in system memory circuit 910. In some cases, method 1300 may be performed concurrently with other instances of the method. For example, two or more instances of processing circuitry 901 or multiple process threads in a single instance of processing circuitry 901 may each perform method 1300 independently of one another.

Referring now to Figure 14, a flow diagram of one embodiment of a method for using various QoS levels with a buffer allocated to a cache memory circuit is illustrated. In a similar manner to method 1300, method 1400 may be performed by processing circuitry 901 of FIGS. 9, 10, and 12. As described above, processing circuit 901 may include (or may include) a non-transitory computer-readable medium having program instructions executable by processing circuit 901 to cause the operations described with reference to FIG. 14 stored thereon. accessible). Referring collectively to Figures 12 and 14, method 1400 begins at block 1410.

At block 1410, method 1400 includes assigning a plurality of locations to a cache memory circuit using bulk transactions. As illustrated, the allocation process of buffer 915 may not have significant QoS demands. Accordingly, caching of the storage locations 935 of the buffer 915 may be performed using bulk transactions 1242 to assign the storage locations 935 to the cache memory circuit 905. As shown at time t0 in FIG. 12, bulk channel 1240 initiates bulk transactions 1242a, 1242b, and 1242c to allocate storage locations 935a, 935d, and 935g, respectively, to cache memory circuit 905. It is used to convey.

The method 1400 also includes, at block 1420, including an indication of having successfully cached storage locations 935, indicating use with real-time transactions. Although the allocation process for buffer 915 may not have a real-time demand, buffer 915 can be expected to be accessed using real-time transactions. Accordingly, when a particular storage location 935 is successfully cached to its respective cache line 920, the corresponding cache tag for the cache line may include an indication that the cached contents are associated with real-time transactions. As described above, such indications can help avoid eviction of cache lines 920 that had been allocated to buffer 915.

At block 1430, method 1400 further includes accessing, by an agent (e.g., processing circuitry 901), successfully cached storage locations 935 using real-time transactions. After allocation of buffer 915 is complete, processing circuitry 901 may access one of storage locations 935 using real-time transactions 1250a and 1250b, as shown in FIG. 12. there is. Real-time transaction 1250a hits cache line 920a where storage location 935c was cached. If real-time transaction 1250a includes a read request, data from cache line 920a, corresponding to the requested address, may be transferred from cache memory circuit 905 to processing circuit 901 using a real-time transaction. there is.

The method 1400, at block 1440, also includes, in response to a cache miss for a particular one of the uncached storage locations 935, using real-time transactions, by the cache memory circuitry 905. and accessing, in circuit 910, a specific storage location 935 within buffer 915. As shown in Figure 12, real-time transaction 1250b is targeted to storage location 935f. However, storage location 935f was not successfully cached in cache memory circuit 905. Accordingly, cache memory circuit 905 generates a real-time fetch 1290 and issues it to system memory circuit 910 to retrieve values from storage location 935f. If either of the bulk fetches 1265a, 1265b, also generated by the cache memory circuit 905, has not been issued when the real-time fetch 1290 is ready to be issued, then the real-time fetch 1290 will May be prioritized ahead of fetches.

Method 1400 may end at block 1440, or, in some embodiments, may be repeated in whole or in part. For example, block 1430 may be repeated while processing circuit 901 is processing values in buffer 915. Similarly, block 1440 may be repeated when processing circuitry 901 accesses storage location 935 that was not successfully cached. In a similar manner to method 1300, method 1400 may be performed concurrently with other instances of method 1400.

Turning now to Figure 15, a flow diagram of one embodiment of a method for selecting and coordinating a particular order for allocating buffers to cache memory circuits is illustrated. As described for methods 1300 and 1400, method 1400 may be performed by processing circuitry 901 of FIGS. 9, 10, and 12. As described, processing circuit 901 may include (or may include) a non-transitory computer-readable medium having program instructions executable by processing circuit 901 to cause the operations described with reference to FIG. 15 stored thereon. accessible). Referring collectively to Figures 12 and 15, method 1500 begins at block 1510.

At block 1510, method 1500 includes determining a specific order using a desired cache miss rate for a plurality of storage locations 935. As described above, a specific order for allocating buffers 915 may be selected with the goal of distributing cache misses across buffers 915. An agent that will use buffer 915 (e.g., processing circuit 901) may process data stored in buffer 915 using a linear order. Processing circuit 901 may start at an initial storage location, such as 935a, sequentially progress through storage locations 935, such as 935b, 935c, etc., and end at storage location 935i. If storage locations 935 are allocated in this same linear order, more storage locations 935 may not be cached toward the end of buffer 915. Processing the data in buffer 915 in the same order can result in a cache miss rate that increases as processing progresses, potentially peaking toward the end of buffer 915. A specific order may be chosen to distribute allocation failures of storage locations 935 across buffer 915 such that the peak cache miss rate remains below the desired cache miss rate as buffer 915 is processed.

The method 1500 includes accessing, at block 1520, the plurality of storage locations 935 using a linear order by processing circuitry 901 after caching. As described, processing circuitry 901 may access buffer 915 using a linear order that differs from the specific order. In other embodiments, processing circuit 901 may use an ordering other than a linear ordering. In such embodiments, the specific order may be selected to be different from a different order, including, for example, using a linear order to assign storage locations 935.

At block 1530, the method further includes tracking a cache miss rate associated with the use of a particular order for caching the plurality of storage locations 935. As processing circuitry 901 uses buffer 915, the observed cache miss rate can be tracked and further compared to the desired cache miss rate. If the particular order for allocating storage locations 935 was effective, the tracked cache miss rate should remain below the desired cache miss rate, which would result in cache misses being more consistent throughout the processing of all data in buffer 915. Because it can happen. By distributing cache misses consistently, the peak cache miss rate should be kept reasonably low and not exceed the desired cache miss rate.

The method 1500 further includes, at block 1540, in response to determining that the tracked cache miss rate satisfies the threshold rate, adjusting the particular order for subsequent use. As illustrated, when the tracked cache miss rate reaches or exceeds the desired cache miss rate, allocating buffers 915 using the specific order selected did not achieve the desired results. The threshold rate may be equal to the desired cache miss rate, or may be adjusted higher or lower based on overall system operating goals. To tune a particular order, cache misses that occurred at a time when the cache miss rate met a threshold rate can be analyzed to identify the storage locations 935 that were being accessed. One or more of these identified storage locations 935 may be selected to be moved closer to the start of the adjusted allocation order. Additionally, storage locations 935 that were accessed at times when the cache miss rate was low can also be identified. One or more of these storage locations may be selected to be moved toward the end of the adjusted allocation order.

Method 1500 may end at block 1540, or, in some embodiments, may be repeated in whole or in part. For example, blocks 1520 and 1530 may be repeated while processing circuit 901 is accessing storage locations 935 within buffer 915. As described for methods 1300 and 1400, method 1500 may also be performed concurrently with other instances of method 1500. Additionally, methods 1300, 1400, and 1500 may be performed concurrently with each other.

1-8 illustrate circuits and methods for a system that reallocates a portion of cache memory for use as a directly addressable address area. 9-15 illustrate circuits and techniques for caching a buffer within system memory in a cache memory circuit. Any embodiment of the disclosed systems may be included in one or more of a variety of computer systems, such as desktop computers, laptop computers, smartphones, tablets, wearable devices, etc. In some embodiments, the circuits described above may be implemented on a system-on-chip (SoC) or other type of integrated circuit. A block diagram illustrating one embodiment of computer system 1600 is illustrated in FIG. 16. Computer system 1600 may, in some embodiments, include any of the disclosed embodiments, such as systems 100, 200, 500, 600, 900, or 1100.

In the illustrated embodiment, system 1600 includes multiple types of processing circuits, such as a central processing unit (CPU), graphics processing unit (GPU), etc., a communication fabric, and memories and input/output devices. Includes at least one instance of a system-on-chip (SoC) 1606, which may include interfaces. In some embodiments, one or more processors of SoC 1606 include multiple execution lanes and an instruction issue queue. In various embodiments, SoC 1606 is coupled to external memory 1602, peripherals 1604, and power supply 1608.

A power supply 1608 is also provided that supplies supply voltages to the SoC 1606 as well as one or more supply voltages to the memory 1602 and/or peripherals 1604. In various embodiments, power supply 1608 represents a battery (e.g., a rechargeable battery in a smart phone, laptop or tablet computer, or other device). In some embodiments, more than one instance of SoC 1606 is included (and more than one external memory 1602 is also included).

Memory 1602 may include dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (mobile versions of SDRAM, such as mDDR3, and/or low-power versions, such as LPDDR2). It is any type of memory, such as RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are combined on a circuit board to form memory modules, such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the devices are mounted with SoCs or integrated circuits in a chip-on-chip configuration, package-on-package configuration, or multi-chip module configuration.

Peripherals 1604 include any desired circuitry depending on the type of system 1600. For example, in one embodiment, peripherals 1604 include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, peripherals 1604 also include additional storage, including RAM storage, solid state storage, or disk storage. Peripherals 1604 include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc.

As illustrated, system 1600 is shown to have a wide range of areas of application. For example, system 1600 may operate on a desktop computer 1610, a laptop computer 1620, a tablet computer 1630, a cellular or mobile phone 1640, or a television 1650 (or a set-top box coupled to a television). It can be utilized as parts of chips, circuits, components, etc. Smartwatch and health monitoring device 1660 are also illustrated. In some embodiments, a smartwatch may include various general-purpose computing-related functions. For example, a smartwatch can provide access to email, cell phone service, the user's calendar, etc. In various embodiments, a health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functionality. For example, health monitoring devices can monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, and identify health risks. This may include providing communications to emergency services. In various embodiments, the above-mentioned smartwatch may or may not include some or any health monitoring-related features. Other wearable devices 1660 are also contemplated, such as devices worn around the neck, devices attached to a hat or other headgear, devices implantable in the body, glasses designed to provide augmented and/or virtual reality experiences, etc. do.

System 1600 may further be used as part of cloud-based service(s) 1670. For example, the previously mentioned devices, and/or other devices, may access computing resources (i.e., remotely located hardware and/or software resources) within the cloud. Still further, system 1600 may be utilized in one or more devices of home 1680 other than those previously mentioned. For example, devices in the home can monitor and detect conditions that require attention. Various devices within the home (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and provide alerts to the homeowner (or, e.g., a repair facility) when certain events are detected. Alternatively, a thermostat can monitor the temperature within the home and automate adjustments to the heating/cooling system based on a history of responses to various conditions by the homeowner. Additionally, application of system 1600 to various modes of transportation 1690 is illustrated in FIG. 16 . For example, system 1600 can be used on aircraft, trains, buses, rental cars, personal automobiles, watercraft from personal boats to cruise liners, scooters (for rental or ownership), etc. It can be used in control and/or entertainment systems. In various instances, system 1600 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc.

Note that the wide variety of potential applications for system 1600 may include varying performance, cost, and power consumption requirements. Accordingly, a scalable solution that can provide a suitable combination of performance, cost and power consumption using one or more integrated circuits may be advantageous. These and many other embodiments are possible and contemplated. Note that the devices and applications illustrated in FIG. 16 are illustrative only and are not intended to be limiting. Other devices are possible and contemplated.

As disclosed with respect to FIG. 16 , computer system 1600 may include one or more integrated circuits included within a personal computer, smartphone, tablet computer, or other type of computing device. A process for designing and creating an integrated circuit using design information is presented below in Figure 17.

Figure 17 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information, according to some embodiments. The embodiment of FIG. 17 may be used to design and use integrated circuits, e.g., any of the systems 100, 200, 500, 600, 900, or 1100 as shown and described throughout FIGS. 1-15. It can be used in the manufacturing process. In the depicted embodiment, semiconductor manufacturing system 1720 processes design information 1715 stored on non-transitory computer-readable storage medium 1710 and creates an integrated circuit 1730 (e.g., It is configured to manufacture system 100).

Non-transitory computer-readable storage medium 1710 may include any of a variety of suitable types of memory devices or storage devices. Non-transitory computer-readable storage media 1710 may include installation media, such as CD-ROM, floppy disks, or tape devices; Computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; Non-volatile memory such as flash, magnetic media, such as hard drives, or optical storage; These may be registers, or other similar types of memory elements, etc. Non-transitory computer-readable storage medium 1710 may also include other types of non-transitory memory or combinations thereof. Non-transitory computer-readable storage medium 1710 may include two or more memory media that may reside in different locations, for example, different computer systems that are connected through a network.

Design information 1715 may be specified using any of a variety of suitable computer languages, including, without limitation, hardware description languages such as VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1715 may be usable by semiconductor manufacturing system 1720 to manufacture at least a portion of integrated circuit 1730. The format of design information 1715 may be recognized by at least one semiconductor manufacturing system, such as semiconductor manufacturing system 1720, for example. In some embodiments, design information 1715 may include a netlist that specifies the elements of the cell library as well as their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit 1730 may also be included in design information 1715. Such cell libraries may include information representing device or transistor level netlist, mask design data, characterization data, etc. of cells included in the cell library.

In various embodiments, integrated circuit 1730 may include one or more custom macrocells, such as memories, analog or mixed signal circuits, etc. In such cases, design information 1715 may include information related to the included macrocells. Such information may include, without limitation, coarse capture database, mask design data, behavior models, and device or transistor level netlists. As used herein, mask design data may be formatted according to the Graphics Data System (gdsii), or any other suitable format.

Semiconductor manufacturing system 1720 may include any of a variety of suitable elements configured to fabricate integrated circuits. This may include, for example, depositing semiconductor materials (e.g., on a wafer, which may include masking), removing the materials, changing the shape of the deposited materials, removing the materials (e.g. , doping materials, or modifying dielectric constants using ultraviolet processing), etc. Semiconductor manufacturing system 1720 may also be configured to perform various tests on fabricated circuits to ensure correct operation.

In various embodiments, integrated circuit 1730 is configured to operate according to a circuit design specified by design information 1715, which may include performing any of the functions described herein. For example, integrated circuit 1730 may include any of the various elements shown or described herein. Additionally, integrated circuit 1730 may be configured with other components to perform various functions described herein.

As used herein, phrases of the form “design information specifying the design of a circuit configured to” do not imply that the circuit must be manufactured for the element to be met. Rather, this phrase indicates that the design information describes a circuit that, when manufactured, will be configured or will include specified components to perform the indicated actions.

***

This disclosure includes references to “an embodiment” or groups of “embodiments” (e.g., “some embodiments” or “various embodiments”). Embodiments are different implementations or instances of the disclosed concepts. References to “one embodiment,” “one embodiment,” “particular embodiment,” etc. do not necessarily refer to the same embodiment. Many possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the disclosure.

This disclosure may discuss potential advantages that may arise from the disclosed embodiments. All implementations of these embodiments will not necessarily exhibit any or all of the potential advantages. Whether a benefit is realized for a particular implementation depends on many factors, some of which are beyond the scope of this disclosure. In fact, there are many reasons why implementations that fall within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of the disclosure, along with one of the disclosed embodiments, that negates or diminishes one or more of the disclosed advantages. Moreover, suboptimal design implementation (e.g., implementation techniques or tools) of a particular implementation may also negate or diminish the disclosed advantages. Even assuming a skillful implementation, realization of the benefits may still depend on other factors such as the environmental circumstances in which the implementation unfolds. For example, inputs supplied to a particular implementation may prevent one or more problems addressed in the disclosure from occurring at a particular opportunity, and as a result, the benefits of the solution may not be realized. Given the existence of possible factors outside the present disclosure, it is expressly intended that any potential advantages described herein should not be construed as claim limitations that must be met to establish infringement. Rather, the identification of such potential advantages is intended to illustrate the type(s) of improvement available to designers having the benefit of the present disclosure. That such benefits are acceptably described (e.g., by stating that a particular benefit "could occur") is not intended to convey doubt as to whether such benefits can in fact be realized, but rather that the realization of those benefits is It is intended to recognize the technical reality that this often depends on additional factors.

Unless otherwise stated, the examples are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure, even if only a single example is described for a particular feature. The disclosed embodiments are intended to be illustrative rather than restrictive, without any statement of the disclosure to the contrary. Accordingly, this application is intended to admit not only the claims that cover the disclosed embodiments, but also such alternatives, modifications and equivalents that will be apparent to those skilled in the art having the benefit of this disclosure.

For example, features in the present application may be combined in any suitable way. Accordingly, new claims may be made during examination of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of other dependent claims, where appropriate, including claims that rely on other independent claims. Similarly, features from individual independent claims may be combined where appropriate.

Accordingly, although attached dependent claims may be written so that each depends on a single other claim, additional dependencies are also contemplated. Any combination of features consistent with this disclosure is contemplated and may be claimed in this or other application. In short, the combinations are not limited to those specifically recited in the appended claims.

Where appropriate, claims written in one format or statutory type (e.g., device) are also considered to be intended to support corresponding claims in another format or statutory type (e.g., method).

***

Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Notice is given herein that the following paragraphs, as well as the definitions provided throughout this disclosure, will be used in determining how to interpret claims made based on this disclosure.

References to the singular form of an article (i.e., a noun or noun phrase preceded by “a”, “an” or “the”) are intended to mean “one or more” unless the context clearly dictates otherwise. do. Accordingly, reference to “an item” in a claim does not exclude additional instances of the item without accompanying context. “Plural” items refer to two or more sets of items.

The word “may” is used in this specification not in a mandatory sense (i.e., must) but in a permissive sense (i.e., having the possibility of doing, being able to do).

The terms “comprising” and “including” and their forms are open-ended and mean “including but not limited to.”

When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense, unless the context provides otherwise. Accordingly, reference to “x or y” is equivalent to “x or y, or both” and thus covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is being used in an exclusive sense.

Reference to "w, x, y, or z, or any combination thereof" or "... at least one of w, It is intended to cover possibilities. For example, given a set [w, x, y, z], these phrases refer to any single element of the set (e.g., w but not for example w and x but not y or z), any three elements (e.g. w, x and y but not z) and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element of the set [w, x, y, z], thereby exhausting all possible combinations within this list of elements. Cover. These phrases should not be interpreted to require that there is at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

Various “labels” may precede nouns or noun phrases in this disclosure. Unless the context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. refers to Additionally, when applied to features, the “first,” “second,” and “third” labels do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise noted. .

The phrase “based on” is used to describe one or more factors that influence a decision. These terms do not exclude the possibility that additional factors may influence the decision. That is, the decision may be based solely on the specified factors or may be based on the specified factors as well as other, unspecified factors. Consider the statement “Decide A based on B.” These phrases specify that B is used to determine A or is a factor influencing A's decision. This phrase does not exclude that A's decision may also be based on some other factors, such as C. Additionally, this phrase is intended to cover embodiments in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part.”

The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect jointly with or independently of the specified factors. That is, the effect may respond only to these factors or may respond to the specified factors as well as other unspecified factors. Consider the statement “Do A in response to B.” These phrases specify that B is an argument that triggers the execution of A or triggers a specific result for A. This phrase does not exclude that performing A may also respond to some other argument, such as C. This phrase also does not exclude that performing A may be performed jointly in response to B and C. This phrase is also intended to cover embodiments in which A is performed in response only to B. As used herein, the phrase “in response” is synonymous with the phrase “at least in part in response.” Similarly, the phrase “in response to” is synonymous with the phrase “at least in part in response to.”

Within this disclosure, different entities (which may be variously referred to as “units,” “circuits,” other components, etc.) are described as being “configured” to perform one or more tasks or operations. may be or may be charged. This expression - [entity] configured to [perform one or more tasks] - is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure can be said to be "configured" to perform some task even if the structure is not currently performing it. Accordingly, an entity described or referred to as being “configured” to perform some task refers to something physical, such as a device, circuit, system having a processor unit and memory that stores executable program instructions to implement the task. This phrase is not used herein to refer to something intangible.

In some cases, various units/circuits/components may be described herein as performing a task or set of operations. It is understood that these entities, even if not specifically stated, are “configured” to perform such tasks/actions.

The term “configured to” is not intended to mean “configurable to”. For example, an unprogrammed FPGA would not be considered “configured” to perform a specific function. However, these unprogrammed FPGAs can be “configurable” to perform their functions. After appropriate programming, the FPGA can then be said to be “configured” to perform a specific function.

For purposes of U.S. patent applications based on this disclosure, a statement in a claim that a structure is “configured” to perform one or more tasks expressly means that a claim element is within the meaning of 35 U.S.C. §112(f) is not intended to apply. If an applicant seeks to invoke section 112(f) during prosecution of a U.S. patent application based on this disclosure, the claim elements will be recited using a “means for performing a function” structure.

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Different “circuits” may be described in this disclosure. These circuits or “circuitry” may include combinational logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random access memory, embedded It constitutes hardware that includes various types of circuit elements such as dynamic random access memory, programmable logic arrays, etc. The circuitry can be custom designed or taken from standard libraries. In various implementations, the circuitry may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as “units” (eg, decode unit, arithmetic logic unit (ALU), functional unit, memory management unit (MMU), etc.). Such units also refer to circuits or circuit sections.

Accordingly, the disclosed circuits/units/components and other elements illustrated in the drawings and described herein include hardware elements such as those described in the previous paragraph. In many cases, the internal arrangement of hardware elements within a particular circuit can be specified by describing the functionality of that circuit. For example, a particular “decode unit” may be described as performing the function of “processing the opcode of an instruction and routing that instruction to one or more of a plurality of functional units,” which means that the decode unit means “configured” to perform these functions. This functional specification is sufficient to suggest to those skilled in the computer arts the set of possible structures for the circuit.

In various embodiments, as discussed in the previous paragraph, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement of such circuits/units/components with respect to each other and the way they interact form the microarchitectural definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to form the physical implementation of the microarchitectural definition. Accordingly, the microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, a person skilled in the art, given the microarchitecture definition provided in accordance with the present disclosure, will be able, without undue experimentation and by the application of ordinary skill, to describe the circuits/units/components in a hardware description language (HDL) such as Verilog or VHDL. ) You can implement the structure by coding. HDL descriptions are often expressed in a way that may appear functional. However, for those skilled in the art, this HDL description is the method used to translate the structure of a circuit, unit or component to the next level of implementation details. Such HDL descriptions can be either behavior code (which is typically not synthesizable), register transfer language (RTL) code (which, as opposed to behavior code, is typically synthesizable), or structural code (e.g., logic gates and their connections). It can take the form of a netlist specifying . The HDL description can be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology and modified for timing, power and other reasons to create the final design database, which can be sent to the foundry. can be used to create masks and ultimately create integrated circuits. Some hardware circuits or portions thereof can also be custom designed with a schematic editor and captured together with the synthesized circuitry into an integrated circuit design. Integrated circuits may include transistors and other circuit elements (eg, passive elements such as capacitors, resistors, inductors, etc.) and interconnections between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits combined together to implement a hardware circuit and/or in some embodiments discrete elements may be used. Alternatively, the HDL design can be synthesized into a programmable logic array, such as a Field Programmable Gate Array (FPGA), and implemented on the FPGA. This decoupling between the design of a group of circuits and the subsequent low-level implementation of those circuits is generally a scenario in which the circuit or logic designer does not specify a particular set of structures for the low-level implementation beyond a description of what the circuit is configured to do. This is because these processes are performed at different stages of the circuit implementation process.

The fact that many different low-level combinations of circuit elements can be used to implement the same specification of a circuit results in a large number of equivalent structures for that circuit. As mentioned, these low-level circuit implementations may vary depending on changes in manufacturing technology, the foundry selected to fabricate the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methodologies to create these different implementations may be arbitrary.

Moreover, it is common for a single implementation of a particular functional specification of a circuit to include a large number of devices (e.g., millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete description of the low-level structures used to implement a single embodiment, let alone the vast array of equivalent possible implementations. For this reason, this disclosure describes the structure of circuits using functional shorthand commonly used in the industry.

Claims (20)

As a device,
a cache memory circuit including a cache memory having a plurality of cache lines; and
a cache controller circuit, the cache controller circuit comprising:
receive a request to reallocate a portion of the cache memory circuit currently in use, the request identifying an address region corresponding to one or more cache lines of the plurality of cache lines; and
In response to the request, the apparatus is configured to convert the one or more cache lines to directly addressable random-access memory (RAM) by excluding the one or more cache lines from cache operations. 2. The method of claim 1, wherein the cache controller circuit:
to support a real-time virtual channel for memory transactions in the identified address region; and
The apparatus further configured to prioritize memory transactions received via the real-time virtual channel over memory transactions received via the bulk virtual channel. 2. The method of claim 1, wherein the cache controller circuit:
determine that the address area is included in a secure access area; and
In response to the determination, the apparatus is further configured to ignore memory transactions in the address area from agents that are not authorized to access the secure access area. The apparatus of claim 1, wherein the cache controller circuit is further configured to flush the one or more cache lines prior to converting the one or more cache lines to the directly addressable RAM. 2. The method of claim 1, wherein the cache controller circuit:
In response to data in a valid cache line being written, issue a write-back request for the valid cache line; and
The apparatus further configured to exclude the one or more cache lines from writeback requests. 2. The method of claim 1, wherein the cache controller circuit:
receive a different request to deallocate a portion of the cache memory from the directly addressable RAM; and
In response to the different request, the apparatus further configured to include the one or more cache lines in cache operations without copying data stored in the directly addressable RAM while the one or more cache lines are reallocated. 7. The apparatus of claim 6, wherein the cache controller circuit is further configured to generate an error in response to a memory transaction in the directly addressable RAM received after deallocating a portion of the cache memory. As a method,
Receiving, by a cache controller circuit, a request to reallocate a portion of the cache memory circuit currently in use to a directly addressable address area, the request identifying an inactive address area;
based on the identified address region, selecting one or more cache lines of the cache memory circuit to convert; and
Setting, by the cache controller circuit, respective indications for cache lines among the selected cache lines to exclude the selected cache lines from further cache operations. 9. The method of claim 8, wherein setting the respective indication comprises setting, by the cache controller circuit, a real-time memory indicator, wherein the real-time memory indicator determines that the selected cache lines are higher than bulk transactions. A method of indicating that a method is associated with real-time transactions having priorities. 9. The method of claim 8, wherein in response to determining that the identified address region is part of a secure access region, the cache controller circuit, in response to determining that the identified address region is part of a secure access region, A method further comprising the step of ignoring a memory transaction. 9. The method of claim 8, wherein the cache controller circuit:
The method further comprising flushing the selected cache lines prior to setting the respective indications. The method of claim 8, wherein data written to a specific address currently cached in the cache memory circuit is written back to the specific address in system memory;
Wherein data written to a different address within the identified address range is not written back to the system memory. According to clause 8,
receiving, by the cache controller circuit, a different request to deallocate a portion of the cache memory circuit from the directly addressable address region; and
In response to the different request, further comprising including the selected cache lines in cache operations, wherein while the selected cache lines are reallocated, data stored in the directly addressable address region is stored in a write to a system memory circuit. Method to be overwritten without a back. 14. The method of claim 13, further comprising, by the cache controller circuit, returning a default value in response to a read request for an address within the directly addressable address region received after deallocating a portion of the cache memory circuit. Including, method. As a system,
a cache memory circuit including a cache memory having a plurality of paths;
A processor configured to issue memory requests using an address map including active and inactive address areas; and
a cache controller circuit, the cache controller circuit comprising:
receive a request from the processor to reallocate a portion of the cache memory as directly addressable memory, the request identifying an inactive address region;
based on the request, select a portion of the paths to convert; and
A system configured to map a selected portion of the paths for use in the identified address region. 16. The method of claim 15, wherein to convert the selected portion of the paths, the cache controller circuit is configured to set respective indications on cache tags corresponding to specific cache lines included in the selected portion of the paths, The system wherein the respective indications remove the specific cache lines from use as cache memory. 17. The method of claim 16, wherein the cache controller circuit is further configured to set respective real-time indicators to the cache tags corresponding to the specific cache lines, the real-time indicators being configured to determine whether the specific cache lines are associated with bulk transactions. Indicating that the system is associated with real-time transactions with higher priorities. 16. The method of claim 15, wherein the cache controller circuit is further configured to include a selected portion of the paths in cache operations in response to receiving a request to deallocate the directly addressable memory. and wherein data stored in the directly addressable memory while a selected portion is reallocated is not relocated in response to the request to deallocate the directly addressable memory. 16. The system of claim 15, wherein the cache controller circuit is further configured to flush cache lines in a selected portion of the paths prior to mapping the selected portion of the paths for use in the identified address region. 16. The system of claim 15, wherein the portion of paths is half of a particular path.

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