DE112021006520T5 - GRAPHENE HALL SENSOR, PRODUCTION AND USE THEREOF - Google Patents

Abstract

A graphene Hall sensor (10) for operation at cryogenic temperatures (below 120 K), a dielectric layer (12), preferably made of aluminum oxide or silicon dioxide, provided on a graphene film (18) formed on a substrate, a first pair of electrical contacts (14, 15) and a second pair of electrical contacts (16, 17) on continuous outer edge surfaces of a (cross-shaped) structured dielectric layer/graphene film structure spaced along two perpendicular directions (x, y). The graphene film has a layer support density in the range of 2 x 1011cm-2 to 1 x 1013cm-2. A corresponding manufacturing process involves structuring a dielectric layer on a section of the graphene film and then (oxygen) plasma etching the graphene film.

Description

FIELD OF REVELATION

The present disclosure relates to the measurement of magnetic fields using Hall sensors.

In particular, the present disclosure relates to the measurement of magnetic fields at cryogenic temperatures using a Hall sensor.

STATE OF THE ART

Hall effect sensors (Hall sensors) are sensors used to measure a magnetic field. A Hall sensor is typically formed from a foil of a conductor. The “Hall effect” occurs when a current flowing through the conductor interacts with a magnetic field oriented perpendicular to the direction of the current. Charge carriers flowing through the conductor experience a Lorentz force due to the magnetic field. The Lorentz force is perpendicular to the direction of current flow and perpendicular to the magnetic field. This force causes the flow of charge carriers through the conductor to bend so that charge carriers accumulate on one side of the conductor. By separating the charge carriers across the conductor, an electric field is created that counteracts further charge separation. This potential is the Hall voltage that can be measured across the conductor. Thus, measuring the Hall voltage enables the determination of the magnetic field.

For many applications it is desirable to provide a Hall sensor with high sensitivity. In general, the sensitivity of a Hall sensor depends on the mobility of the carriers of the material used as a conductor. For example, the electron mobility of silicon in silicon-based Hall sensors is approximately 1,500 cm ² /Vs.

In order to provide Hall sensors with improved sensitivity, other materials have been considered for use in Hall sensors. For example, graphene is known to have an electron mobility at room temperature of about 15,000 cm ² /Vs. GB-A-2585842 discloses a method for manufacturing Hall effect sensors comprising a graphene layer (a graphene Hall effect sensor) using a laser etching process.

While it is desirable to provide a Hall sensor with high sensitivity, another property of interest is operating temperature. Hall sensors, which consist of e.g. B. silicon are typically only operable at temperatures of around 230 K to 350 K. At lower temperatures, for example cryogenic temperatures below 120 K, many Hall sensors are not operational or alternatively the response is so non-linear that operating performance is significantly reduced.

Two-dimensional (2D) materials, particularly graphene, are currently the focus of intensive research and development worldwide. 2D materials have been shown to have extraordinary properties, both in theory and in practice, which has led to a flood of products containing such materials, including coatings, batteries and sensors, to name a few. Graphene is the best known and is currently being investigated for a number of potential applications. Most importantly, graphene is used in electronic devices and their components, including transistors, LEDs, photovoltaic cells, Hall effect sensors (also called “Hall sensors”), diodes, and the like.

Accordingly, there are a wide range of electronic devices known in the art that incorporate integrated graphene layer structures (as single layer or multilayer graphene) and/or other 2D materials as primary materials to provide improvements in such devices compared to previous devices and electronic products. This includes structural improvements through the use of thinner and lighter materials (which can produce flexible electronics), as well as performance improvements such as increased electrical and thermal conductivity, resulting in increased operational efficiency.

Due to the sensitivity of 2D materials exposed to atmospheric interaction and contamination, it is necessary to encapsulate the 2D materials and/or the device containing such materials with a protective layer or layers. The inventors have discovered that the metal present in ohmic contacts and required to make electrical connections to the 2D material can result in undesirable doping. Doping 2D materials leads to a modification of the electronic properties. For devices such as Hall effect sensors, the operation is very sensitive to the change in electronic structure because it relies as much as possible on maintaining charge neutrality in the 2D material. Nevertheless, contamination by oxygen or water vapor in the atmosphere may result in gradual deterioration of device performance, which may be detrimental to customers/consumers is undesirable for those who expect electronic devices to maintain specified performance many years after manufacture. Furthermore, electronic components, particularly microelectronic components, can be impossible or at least very difficult to replace, so even minor improvements in lifespan and performance stability are highly valued.

While fabricating electronic devices, inventors have discovered that standard lithographic processes, such as those that use polymer coatings such as PMMA to create the desired configurations of the underlying 2D materials, have a number of disadvantages. The PMMA coating may dope the 2D material and may not be suitable for variable temperature applications or specifically high or low temperature applications. Standard processing to remove such polymer coatings by dissolving them in an organic solvent can also introduce impurities and contaminations that hinder reliable device fabrication with consistent properties essential to electronic devices such as microelectronics. It is also known that polymer residues can remain which hinder subsequent processing steps.

Alternatively, it is known that 2D materials can be easily etched from a substrate without using such photolithographic materials to avoid contamination. Such methods include using a laser beam to ablate the substrate and 2D material outside the active region to obtain a patterned 2D material layer. Such a revelation can be in GB 2570124 A which discloses the use of a laser with a wavelength above 600 nm and a power of less than 50 watts to selectively ablate graphene from a substrate that has a thermal resistance greater than that of sapphire. This process has been found to work well at patterning without damaging the graphene sheet structure or underlying substrate, but the process can produce large particles of dirt that land on the 2D material surface. The residue acts as a contaminant or at least prevents the formation of an effective and/or hermetic coating on the 2D material.

Accordingly, it is desirable to produce electronic devices comprising: 2D materials (or indeed the manufacture of an electronic device precursor for use as an electronic device in providing the required electrical connections) by methods that involve fewer processing steps, thereby eliminating unnecessary and disadvantageous ones Contamination and/or doping can be avoided. Consequently, there is also a need for electronic devices and their precursors that provide long-term stability and/or improvements in temperature stability over the prior art. Improvements are needed to enable the use of 2D material-based devices in extreme conditions to benefit from the unique electronic properties of the 2D material.

There is a need for a method that enables the fabrication of an electronic device precursor that includes a 2D material layer and avoids surface contamination and doping by ohmic contact deposition. There is also a need for a process that can encapsulate the 2D material while also allowing for the provision of at least one ohmic contact. It is an object of the present invention to provide a method and a number of specific embodiments, each of which, together with the electronic device precursors available through such methods, overcome or substantially overcome the various problems associated with the prior art reduce or at least provide a commercially useful alternative.

Against this background, it is an object of the invention to provide an improved or at least commercially useful alternative Hall sensor.

SHORT PRESENTATION

According to a first aspect of the invention, a graphene Hall sensor for operation at cryogenic temperatures is provided. The graphene Hall sensor includes a substrate, a graphene sheet, a dielectric layer, a first pair of electrical contacts, and a second pair of electrical contacts. The graphene film is provided on the substrate. The dielectric layer is provided on the graphene sheet. The graphene and dielectric layer share a continuous outer edge surface. The first pair of electrical contacts are in electrical contact with the graphene sheet and are spaced apart along a first direction. The second pair of electrical contacts are in electrical contact with the graphene sheet and are spaced along a second direction. The first direction is perpendicular to the second direction, and a path along it the first direction between the first pair of electrical contacts crosses a path along the second direction between the second pair of electrical contacts. The graphene film has a layer support density in the range of 2 × 10 ¹¹ cm ^-2 to 1 × 10 ¹³ cm ^-2 .

According to this disclosure, the layer carrier density is understood to mean the net amount of charge carriers per area in the graphene film. This means that the layer charge carrier density is the absolute difference between the hole density and the electron density. Furthermore, it is understood that the sheet support density for graphene may vary to some extent with temperature. As such, in accordance with this disclosure, all references to sheet support density for graphene are to be understood as the sheet support density of graphene 4 K (i.e., the sheet support density at a cryogenic temperature).

According to the first aspect, the graphene Hall sensor formed from a graphene strip having a sheet carrier density in the specified range is formed. The present inventors have discovered that by forming the graphene Hall sensor from graphene with the specified carrier density, the devices exhibit improved performance at cryogenic temperatures. In particular, the graphene Hall sensors with such plate carrier density can achieve sensitivity comparable to the sensitivity of commercially available silicon-based Hall effect sensors while operating at cryogenic temperatures well outside the operating temperature ranges for silicon-based Hall effect sensors.

According to this disclosure, reference to a cryogenic temperature is understood to mean any temperature not greater than 120 K. The present disclosure is particularly concerned with the operation of Hall sensors at cryogenic temperatures not greater than: 20 K, 10 K, 5K, 4K, 3K, 2K, 1.5K or 1K.

While many Hall sensors show signs of nonlinear behavior at cryogenic temperatures, the inventors of the present invention have found that graphene Hall sensors with the specified carrier density exhibit improved linearity. In particular, the linear behavior of the graphene Hall sensors of the first aspect is not only present at room temperature but is also maintained at cryogenic temperatures (e.g. 3 K).

Additionally, many Hall sensors show signs of nonlinear behavior as the applied magnetic field is increased. Such non-linear behavior can be further exacerbated by operation at cryogenic temperatures. The present inventors have discovered that graphene Hall sensors with the specified carrier density exhibit improved linearity at relatively high magnetic fields. For example, the graphene Hall sensors can have improved linearity for magnetic fields ranging from -30T to +30T, -22T to +22T, -16T to +16T, -9T to +9T or -7T to +7T range. This linear behavior is maintained even at cryogenic temperatures. Such areas of improved linearity correspond to the magnetic field strength of commonly available magnets.

As mentioned above, the graphene film has a sheet support density of at least 2 × 10 ¹¹ cm ^-2 (at a temperature of 4 K). Such a sheet support density provides an upper limit on the sensitivity of the graphene Hall sensor at cryogenic temperatures, so that the graphene

Hall sensors can measure magnetic fields in the range of at least -1 T to +1 T without saturation of the graphene Hall sensor.

As mentioned above, the graphene film has a carrier density of no more than 1 × 10 ¹³ cm ^-2 . Such a sheet support density provides a lower limit on the sensitivity of the graphene Hall sensor, such that the resolution achievable by the graphene Hall sensor at cryogenic temperatures is comparable to silicon-based devices used e.g. B. work at room temperature.

The inventors have also discovered that contact deposition after device encapsulation prevents the metal from electrically contacting the 2D material, which is essential to the function of the final electronic device. However, contact deposition prior to an encapsulant or coating can cause problems due to the height difference between the height difference between the 2D material and the contacts on it, resulting in a non-conformal coating that is more easily damaged.

Accordingly, the inventors present a method that includes protecting a graphene layer on a substrate using a plasma-resistant dielectric to both define an etching pattern of the graphene layer and to serve as a protective coating in the final device precursor (and of course ultimately in a device). The inventors have found that by using a plasma-resistant dielectric to define the etch pattern of the plasma-etchable layer structure comprising the graphene, an intermediate product is provided which leaves only the edges of the graphene layer exposed, and an ohmic contact can be formed in direct contact with a portion of the exposed edge.

In some embodiments, the substrate density of the graphene Hall sensor may be further optimized to provide a balance between the sensitivity of the graphene Hall sensor and the magnetic field operating range of the graphene Hall sensor.

In some embodiments, a ply support density of at least 1.25 x 10 ¹² cm ^-2 may be provided. In such embodiments, the graphene Hall sensor can operate at magnetic fields between -7 T and +7 T without saturation.

In some embodiments, a ply support density of at least 3 × 10 ¹² cm ^-2 may be provided. In such embodiments, the graphene Hall sensor can be operated at magnetic fields between -22 T and +22 T or at least -30 T and +30 T without saturation of the graphene Hall sensor occurring.

In some embodiments, the first pair of electrical contacts is provided on the substrate adjacent the graphene sheet such that the first pair of electrical contacts are in direct contact with the graphene sheet via the continuous outer edge surface. In some embodiments, the second pair of electrical contacts is provided on the substrate adjacent the graphene sheet such that the second pair of electrical contacts are in direct contact with the graphene sheet via the continuous outer edge surface.

In some embodiments, the graphene Hall sensor further includes a continuous air-resistant coating layer covering the substrate, the dielectric layer, and the graphene film, and the first and second pairs of electrical contacts.

In some embodiments, the continuous air-resistant coating layer comprises an inorganic oxide, nitride, carbide, fluoride or sulfide, preferably aluminum oxide or silicon dioxide.

In some embodiments, the substrate comprises sapphire, silicon, silicon dioxide, silicon nitride, silicon carbide, germanium, or a Group HI-V semiconductor.

In some embodiments, the dielectric layer comprises an inorganic oxide, nitride, carbide, fluoride or sulfide, preferably aluminum oxide or silicon dioxide.

In some embodiments, the dielectric layer has a thickness in a direction perpendicular to the graphene sheet of at least 10 nm. Accordingly, the dielectric layer can be provided on the graphene sheet with a thickness such that it forms a conformal coating over the graphene layer. The dielectric layer is preferably formed by a thermal evaporation technique, for example e-beam evaporation, or preferably by an atomic layer deposition (ALD) technique. Forming the dielectric layer by thermal evaporation ensures the formation of the dielectric layer on the graphene sheet without damaging the graphene layer.

In some embodiments, the graphene Hall sensor may be formed as part of a graphene Hall sensor array. Thus, a graphene Hall sensor array can be provided for operation at cryogenic temperatures. The graphene Hall sensor array includes a substrate, a graphene layer and a dielectric layer. The graphene film is provided on the substrate. The graphene sheet has multiple broken graphene sections, each broken graphene section defining a graphene Hall sensor of the graphene Hall sensor array. The dielectric layer is provided on the graphene sheet, the dielectric layer having a plurality of discontinuous dielectric sections provided on the discontinuous graphene sections. Each discontinuous graphene section of the graphene sheet and a corresponding discontinuous dielectric section share a continuous outer edge surface. Each graphene Hall sensor of the graphene Hall sensor array further includes: a first pair of electrical contacts and a second pair of electrical contacts. The first pair of electrical contacts are in electrical contact with the discontinuous graphene section and are spaced along a first direction. The second pair of electrical contacts are in electrical contact with the discontinuous graphene section and are spaced along a second direction. The first direction is perpendicular to the second direction. A path along the first direction between the first pair of electrical contacts intersects a path along the second direction between the second pair of electrical contacts. The graphene film has a layer support density in the range of 2 × 10 ¹¹ cm ^-2 to 1 × 10 ¹³ cm ^-2 .

According to a second aspect of the invention, a magnetic field measuring system is provided. The system includes a graphene Hall sensor sor according to the first aspect and a Hall measurement controller connected to the first and second pairs of electrical contacts. The Hall measurement controller is configured to perform Hall effect measurement using the graphene Hall sensor.

Thus, the graphene Hall sensor of the first aspect may be provided as part of a system configured to perform magnetic field measurements. In particular, the system can be configured to perform magnetic field measurements with high accuracy at cryogenic temperatures.

• Aussetzen eines Graphen-Hall-Sensors gemäß dem ersten Gesichtspunkt der Erfindung auf eine kryogene Umgebung, die eine Temperatur von nicht mehr als etwa 100 K hat; und
• Durchführen einer Hall-Effekt-Messung unter Verwendung des Graphen-Hall-Sensors.

According to a third aspect of the invention, a method for determining a magnetic field at cryogenic temperatures is provided. The procedure includes:

• exposing a graphene Hall sensor according to the first aspect of the invention to a cryogenic environment having a temperature of no more than about 100 K; and
• Performing a Hall effect measurement using the graphene Hall sensor.

Thus, the method according to the third aspect uses the graphene Hall sensor according to the first aspect (or the magnetic field measurement system according to the second aspect) to perform a Hall effect measurement at a cryogenic temperature.

• Bilden einer Graphenschicht auf einem Substrat;
• Strukturieren einer plasmabeständigen dielektrischen Schicht auf einem Abschnitt der Graphenfolie, um ein Zwischenprodukt zu bilden, das mindestens einen bedeckten Bereich und mindestens einen unbedeckten Bereich der Graphenfolie aufweist;
• Aussetzen des Zwischenprodukts einer Plasmaätzung, wodurch der mindestens eine unbedeckte Bereich der Graphenfolie weggeätzt wird, um eine geätzte Schichtstruktur mit einer oder mehreren freiliegenden Randoberflächen zu bilden;
• Ausbilden eines ersten Paares elektrischer Kontakte in elektrischem Kontakt mit der Graphenfolie und beabstandet entlang einer ersten Richtung; und
• Ausbilden eines zweiten Paares elektrischer Kontakte in elektrischem Kontakt mit der Graphenfolie und beabstandet entlang einer zweiten Richtung,
• wobei die erste Richtung senkrecht zu der zweiten Richtung verläuft und ein Pfad entlang der ersten Richtung zwischen dem ersten Paar elektrischer Kontakte einen Pfad entlang der zweiten Richtung zwischen dem zweiten Paar elektrischer Kontakte kreuz, und
• die Graphenfolie eine Lagenträgerdichte im Bereich von 2 × 10¹¹ cm^-2 bis 1 × 10¹³ cm^-2 hat.

According to a fourth aspect of the invention, a method of manufacturing a graphene Hall sensor is provided. The procedure includes:

• forming a graphene layer on a substrate;
• patterning a plasma-resistant dielectric layer on a portion of the graphene sheet to form an intermediate product having at least a covered area and at least an uncovered area of the graphene sheet;
• subjecting the intermediate product to a plasma etch, thereby etching away the at least one uncovered region of the graphene sheet to form an etched layer structure having one or more exposed edge surfaces;
• forming a first pair of electrical contacts in electrical contact with the graphene sheet and spaced apart along a first direction; and
• forming a second pair of electrical contacts in electrical contact with the graphene sheet and spaced apart along a second direction,
• wherein the first direction is perpendicular to the second direction and a path along the first direction between the first pair of electrical contacts crosses a path along the second direction between the second pair of electrical contacts, and
• the graphene film has a layer support density in the range of 2 × 10 ¹¹ cm ^-2 to 1 × 10 ¹³ cm ^-2 .

As such, the method of the fourth aspect can be used to form a graphene Hall sensor according to the first aspect of the invention.

In some embodiments, the first pair of electrical contacts is formed on the substrate adjacent the graphene sheet such that the first pair of electrical contacts are in direct contact with the graphene sheet via one or more of the exposed edge surfaces. In some embodiments, the second pair of electrical contacts is provided on the substrate adjacent the graphene sheet such that the second pair of electrical contacts are in direct contact with the graphene sheet via one or more of the outer edge surfaces.

In some embodiments, the method of the fourth aspect further includes forming a continuous air-resistant coating over the etched layer structure and the first and second pairs of electrical contacts.

In some embodiments, patterning the plasma resistant dielectric layer includes patterning a plasma resistant dielectric by thermal evaporation, preferably using a mask. In some embodiments, the plasma resistant dielectric layer is patterned using e-beam evaporation. Accordingly, the dielectric layer (e.g., an aluminum oxide dielectric layer) can be formed on the graphene sheet so that the carrier density of the graphene sheet is not adversely affected.

According to a fifth aspect of the invention, using a graphene Hall sensor according to the first aspect to provide a magnetic field with a magnitude of at least 1 T at a temperature of not more than 120 K. In some embodiments, the magnetic field may have a magnitude of at least: 3T, 5T, 7T, 9T, 11T, 13T, 16T, 19T, 22T, 30T, or 40T.

1. (i) Bereitstellen einer plasmaätzbaren Schichtstruktur auf einem plasmabeständigen Substrat, wobei die Schichtstruktur eine freiliegende obere Oberfläche aufweist;
2. (ii) Strukturieren eines plasmabeständigen Dielektrikums auf der freiliegenden oberen Oberfläche, um ein Zwischenprodukt mit mindestens einem bedeckten Bereich und mindestens einem unbedeckten Bereich der Schichtstruktur zu bilden,
3. (iii) Unterziehen des Zwischenprodukts einer Plasmaätzung, wobei der mindestens eine unbedeckte Bereich der Schichtstruktur weggeätzt wird, um mindestens einen bedeckten Bereich der Schichtstruktur mit einer freiliegenden Randoberfläche zu bilden;
4. (iv) Bilden eines ohmschen Kontakts in direktem Kontakt mit einem Abschnitt der freiliegenden Kantenoberfläche,

wobei die plasmaätzbare Schichtstruktur eine oder mehrere Graphenschichten umfasst, die sich über die bedeckten Regionen der Schichtstruktur zu der freiliegenden Randoberfläche erstrecken.The present invention also relates to a method of forming graphene structures suitable for use in the graphene Hall sensors of the first aspect. Thus, according to a sixth aspect of the present invention, there is provided a method of manufacturing a precursor to electronic devices, the method comprising:

1. (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed top surface;
2. (ii) patterning a plasma-resistant dielectric on the exposed top surface to form an intermediate product having at least one covered area and at least one uncovered area of the layered structure,
3. (iii) subjecting the intermediate product to a plasma etch, wherein the at least one uncovered region of the layered structure is etched away to form at least a covered region of the layered structure with an exposed edge surface;
4. (iv) forming an ohmic contact in direct contact with a portion of the exposed edge surface,

wherein the plasma-etchable layered structure comprises one or more graphene layers extending beyond the covered regions of the layered structure to the exposed edge surface.

The present invention will now be further described. In the following passages, various aspects/embodiments of the invention are defined in more detail. Each aspect/embodiment thus defined may be combined with any other aspect/embodiment or aspects/embodiments unless clearly stated to the contrary. In particular, any feature specified as preferred or advantageous can be combined with any/all other features specified as preferred or advantageous! Features are combined.

The method disclosed herein therefore uses a plasma resistant dielectric to define an etch pattern and protect the surface of the 2D material from doping by the ohmic contact. This solution is particularly elegant because the inventors have found that charge injection at the edges of a 2D material layer is significantly greater than on the surface, avoiding doping while allowing improved current flow.

As described above, the present invention provides a method of manufacturing a precursor to electronic devices. A precursor is intended to refer to a component capable of being incorporated into an electrical or electronic circuit, usually by wire bonding to further circuit logic or by other methods known in the art, such as soldering using "flip chip" -Solder balls as described herein. Thus, an electronic device is a functioning device that provides power to the precursor when installed and during operation.

The method includes a first step of providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed top surface and the plasma-etchable layer structure comprising one or more graphene layers.

The plasma-etchable layer structure is one that can be etched during the plasma etching step, as is common in electronic device manufacturing, to remove the layer structure rather than the underlying substrate. Plasma etching is described in more detail herein. In the present invention, the plasma-etchable layer structure comprises and preferably consists of one or more graphene layers. Preferably, at least a top layer of the plasma-etchable layer structure is a graphene layer, thereby ensuring that at least the top graphene layer is etched during plasma etching to form an exposed edge surface.

The plasma-etchable layer structure preferably consists of one or more 2D material layers. 2D materials are well known in the art and are sometimes referred to as single-layer materials, which consist of a single layer of atoms commonly known as transition metal dichalcogenides. And 2D materials are also known that include a layer of metal atoms arranged between the layers of chalcogen atoms (i.e. a compound of type MX2 consisting of three atomic planes). Similarly, graphene (CH) _n and graphene oxide are 2D materials, where graphene has terminal hydrogen atoms and graphene oxide has bridging oxygen atoms and terminal hydroxyl groups. Silicene is wrinkled rather than perfectly flat. In all circumstances, 2D materials can be viewed as plates or layers of virtually infinite size in two dimensions and include, for example, graphene, graphyne, silicene, germanene, borophene, phosphorene, antimonene, hexagonal boron nitride (h-BN), boron carbonitrides and TMDCs (such as MoS ₂ , WS ₂ , MoSe ₂ , WSe ₂ and MoTe ₂ ). Thus, in some embodiments, the plasma-etchable layer structure consists of one or more layers of graphene and one or more layers of silicene, germanene, h-BN, borophene and/or a TMDC. In such embodiments, the plasma-etchable layer structure can be referred to as a heterostructure. Even more preferably, the plasma-etchable layer structure consists of one or more graphene layers, which can be referred to as a graphene layer structure.

The present invention provides at least one ohmic contact in direct contact with the exposed edge surface of the at least one graphene layer of the plasma-etchable layer structure. The plasma-etchable layer structure includes graphene and optionally silicene, germanene, borophene, h-BN and/or a TMDC. Accordingly, any reference herein to graphene applies equally to other 2D materials unless the context clearly requires otherwise.

The layer structure can consist of 1 to 10 individual layers of 2D material layers, with at least one layer being a graphene layer. For example, the plasma-etchable layer structure consists of a graphene monolayer. If the layered structure consists of multiple 2D material layers, 2 to 5 layers are preferred, and 2 or 3 layers are even more preferred. However, a single layer is also preferred because some of the unique properties attributed to 2D materials are most pronounced when provided as a monolayer. For example, monolayer graphene is a zero bandgap semiconductor (i.e., a semimetal), with the density of states at the Fermi level being zero, located at the point where the top of the valence band reaches the bottom of the conduction band (forming a Dirac cone) . Due to the low density of states near the Dirac, a shift in the Fermi level is particularly susceptible to charge transfer into such pristine graphene. The electronic structure also leads to the quantum Hall effect, for example. For certain embodiments, particularly the Hall sensor configurations described herein, a graphene monolayer is therefore particularly preferred and benefits most from the present invention. However, two or more layers of graphene (a so-called graphene layer structure) can be used.

In the first step of the method, providing the graphene of the plasma-etchable layer structure can be achieved by any method known in the art. However, the plasma-etchable layer structure including graphene is synthesized directly on the surface of the substrate and therefore does not involve any physical transfer steps. Preferably, the graphene and any other 2D material layer are formed by CVD or MOCVD growth. The graphene is particularly preferably formed by XLPE or MOCVD. MOCVD is a term used to describe a system used for a specific process of depositing layers on a substrate. While the acronym stands for organometallic chemical vapor deposition, MOCVD is a term in the art and refers to the general process and devices used for it and is not necessarily considered to be limited to the use of organometallic reactants or to produce organometallic materials, but would require only the use of a carbon-containing precursor in the formation of graphene. Instead, the use of this term directs those skilled in the art to a general set of process and device characteristics. Furthermore, MOCVD differs from CVD techniques due to system complexity and accuracy. While CVD techniques enable reactions to be carried out with simple stoichiometries and structures, MOCVD enables the production of complicated stoichiometries and structures. A MOCVD system differs from a CVD system at least in the gas distribution systems, the heating and temperature control systems, and the chemical control systems. A MOCVD system typically costs at least 10 times more than a typical CVD system. MOCVD is particularly preferred to achieve high quality graphene layer structures.

MOCVD can also be easily distinguished from atomic layer deposition (ALD) techniques. ALD relies on stepwise reactions of reagents with intermediate rinsing steps used to remove unwanted byproducts and/or excess reagents. It is not based on decomposition or dissociation of the reagent in the gas phase. It is particularly unsuitable when using reagents with low vapor pressures such as silanes, which would take too much time to remove from the reaction chamber. The MOCVD growth of graphene is described in the patent specification WO 2017/029470 discussed, which is incorporated by reference and provides the preferred method.

The procedure of WO 2017/029470 provides a chamber having a plurality of cooled inlets arranged so that the inlets are distributed throughout the substrate in use and have a constant separation from the substrate. The flow comprising a precursor compound may be provided as a horizontal laminar flow or may be provided substantially vertically. The inlets suitable for such reactors are well known and include the planetary and Showerhead® reactors available from Aixtron®. Other suitable growth chambers include the Turbodisc K series or Propel® MOCVD systems available from Veeco® Instruments Inc.

• Bereitstellen des plasmabeständigen Substrats auf einem beheizten Suszeptor in einer Reaktionskammer, wobei die Kammer eine Vielzahl von gekühlten Einlässen aufweist, die so angeordnet sind, dass die Einlässe im Gebrauch über das Substrat verteilt sind und eine konstante Trennung von dem Substrat aufweisen,
• Zuführen einer Strömung, die eine Vorläuferverbindung umfasst, durch die Einlässe und in die Reaktionskammer, um dadurch die Vorläuferverbindung zu zersetzen und das Graphen auf dem Substrat zu bilden,
• wobei die Einlässe auf weniger als 100 °C, vorzugsweise von 50 °C bis 60 °C, gekühlt werden und der Suszeptor auf eine Temperatur von mindestens 50 °C über einer Zersetzungstemperatur des Vorläufers erwärmt wird.

Accordingly, in a particularly preferred embodiment, the step of providing a plasma-etchable layer structure on a plasma-resistant substrate is a step of forming a graphene layer structure, comprising:

• Providing the plasma resistant substrate on a heated susceptor in a reaction chamber, the chamber having a plurality of cooled inlets arranged such that the inlets are distributed throughout the substrate in use and have a constant separation from the substrate,
• supplying a flow comprising a precursor compound through the inlets and into the reaction chamber to thereby decompose the precursor compound and form the graphene on the substrate,
• wherein the inlets are cooled to less than 100°C, preferably from 50°C to 60°C, and the susceptor is heated to a temperature of at least 50°C above a decomposition temperature of the precursor.

Such a process enables the production of exceptionally high-quality, naturally pure graphene that is scalable to large substrates and the fabrication of an array of electronic device precursors. As described herein, such pristine graphene is advantageous for use in Hall sensor applications due to the resulting quantum Hall effect resulting from a unique electronic structure of the pristine graphene.

As described herein, sapphire and silicon are preferred substrates, particularly for graphene produced by the process of WO 2017/029470. It is understood that a silicon substrate may include a CMOS substrate, which is a silicon-based substrate with graphene deposited on a silicon surface, although a CMOS substrate may include various additional layers or circuitry embedded therein. Sapphire is a particularly preferred substrate. Most preferred is R-plane sapphire. As is known in the art, r-plane refers to the crystallographic orientation of the surface of the substrate (i.e., the surface on which graphene is deposited). Such a substrate is particularly suitable for providing high quality graphene, particularly for sensors such as Hall effect sensors as described herein. This is due in part to the effect of the substrate on the resulting carrier density of the graphene deposited on it. The inventors have found that r-plane sapphire provides graphene with a particularly low carrier density. Preferably, the charge carrier density of the one or more graphene layers is less than 10 ¹² cm ^-2 , preferably less than 8 × 10 ¹¹ cm ^-2 .

For example, when using r-plane sapphire, a carrier density of less than 6 × 10 ¹¹ cm ^-2 can be obtained, preferably less than 5 × 10 ¹¹ cm ^-2 .

The 2D material of the plasma-etchable layer structure can be a doped 2D material. By way of example only, if the 2D material is graphene and is doped, the graphene is preferably doped with one or more elements selected from the group consisting of silicon, magnesium, zinc, arsenic, oxygen, boron, bromine and nitrogen . Likewise, the method may then preferably include introducing a doping element into the reaction chamber and selecting a temperature of the substrate, a pressure of the reaction chamber and a gas flow rate to produce a doped graphene. Preferably, the doped graphene growth precursor contains the dopant element. Alternatively, the precursor comprising the species (which is, for example, carbon for graphene growth and silicon for silicene growth) and one or more further precursors comprising the doping element are introduced into the substrate within the reaction chamber, the second precursor being a Gas is or is suspended in gas to produce doped graphene. The deposition of a plasma-resistant dielectric can itself lead to doping of the 2D material. Accordingly, the provision of a doped 2D material can be used to compensate for any doping effect by patterning on a dielectric.

The plasma-etchable layer structure is provided on a plasma-resistant substrate. In other words, the layer structure lies directly on the substrate without an intermediate layer. The layered structure of 2D material layers provides the layered structure with two opposing surfaces, a first or bottom surface is the surface that is in direct contact with the substrate. Thus, a second or upper surface is exposed and preferably at least this layer is a graphene layer.

Plasma resistant substrates are well known in the art. Ceramic materials such as silicon carbide, silicon nitride and silicon oxide are particularly plasma resistant. Standard crystalline silicon wafers can be considered ceramic and are plasma resistant. Crystalline 111V semiconductors are also plasma resistant and may be preferred as substrates for specific applications such as LEDs. In a preferred embodiment, the plasma-resistant substrate is sapphire, silicon, silicon dioxide, silicon nitride, silicon carbide, germanium or a III-V semiconductor, even more preferably sapphire or silicon.

In a preferred embodiment, the etching rate of the layer structure and the substrate differs by at least a factor of 10, preferably 10 ² and even more preferably 10 ³ . Thus, regardless of the resistivity of the substrate for a given plasma treatment, the layer structure is etched significantly faster than the substrate, resulting in complete etching of the exposed layer structure and negligible loss of substrate surface over the time required for the plasma etching.

Preferably, the plasma-etchable layer structure has an etching rate that is greater than 0.345 nm per minute. The plasma etching rate can be measured using oxygen plasma etching with 40 W power and a flow rate of O ₂ of 6 sccm. Therefore, a graphene layer (with an ideal thickness of 0.345 nm) is etched in one minute under these conditions. Preferably the etch rate is greater than 0.5 nm per minute. Accordingly, the plasma-resistant substrate may preferably have an etch rate of less than 0.1 nm per minute, preferably less than 0.01 nm per minute.

The method further includes a step of patterning a plasma-resistant dielectric onto the exposed top surface to form an intermediate product having at least one covered area and at least one uncovered area of the layered structure. As described herein with respect to the plasma resistant substrate, a plasma resistant dielectric may be any known in the art and its plasma resistance measured by the same parameter (i.e., in terms of layer structure and/or an etch rate). Typically this is an inorganic dielectric (i.e. one that does not involve a carbon-hydrogen bond), such as a ceramic. A ceramic can be considered an inorganic oxide, nitride, carbide, fluoride or sulfide and often has a crystalline structure. In a preferred embodiment, the plasma-resistant dielectric is an inorganic oxide, nitride, carbide, fluoride or sulfide and is preferably aluminum oxide (alumina), silica (silicon dioxide) or silicon nitride.

Inorganic dielectrics are particularly preferred, especially ceramic dielectrics, since these provide significantly improved barrier properties compared to organic dielectric materials such as PMMA. Thus, the dielectric layer may be retained in the precursor of the final electronic device to protect the layer structure from contamination from atmospheric contaminants, particularly oxygen and water vapor. This air and moisture resistant coating provides a barrier to inadvertent doping over a significantly longer period of time, resulting in improved device life. In addition, inorganic materials such as ceramics can withstand wide temperature fluctuations as well as operation at very high temperatures, allowing the electronic device to be used under extreme conditions without risk of damage and eventual contamination of the layered structure, which would otherwise result in device performance drift (which is a may require recalibration or could simply result in device failure).

The plasma-resistant dielectric is patterned onto the exposed upper surface of the plasma-etchable layer structure. That is, the plasma-resistant dielectric is simultaneously patterned, being deposited on the exposed top surface of the plasma-etchable layer structure. As described herein, it is particularly preferred that this be achieved by physical vapor deposition (PVD). PVD is a well-known technique. Patterning results in the formation of the dielectric over a portion of the surface, thereby forming one or more covered regions and one or more uncovered regions of the layered structure (providing an intermediate in the fabrication of the device precursor). In a preferred embodiment, the method includes forming an array of covered regions, each corresponding to a precursor of an electronic device. Such patterning to form an array of covered regions may include using a mask (ie, a shadow mask) to thereby form the dielectric in a plurality of regions. The formation of at least one covered region results in the uncovered regions forming the remainder of the layered structure. Accordingly, this offers in the Typically, if an array of covered regions is patterned on the layered structure, at least a single continuous uncovered region separating the covered regions. In a preferred embodiment, only one uncovered region is formed during the patterning step, since the plasma etching step described herein then results in the formation of a continuous outer edge surface of the layered structure for each electronic device precursor (ie, the formation of a "filled" 2D shape with a outer edge). However, in some embodiments, the 2D shaped and patterned dielectric may have an uncovered portion therein that provides an inner and an outer edge to the graphene layer after etching.

Accordingly, in a preferred embodiment, the structuring step includes forming one or more rectangular regions of the plasma-resistant dielectric. Such structuring of the dielectric and subsequently the 2D material means that the electronic device precursor is particularly preferred for forming a transistor. The precursor of the electronic device can then preferably further comprise a third contact, a gate contact. A gate contact can be provided, for example, on the plasma-resistant dielectric or the coating (if present) as a so-called “front gate” or alternatively on the underside of the substrate as a so-called “back gate”. When provided at the bottom of the substrate, the 2D material is provided on an insulating area of the substrate surface. SiO ₂ , SiO ₂ /Si, and silicon substrates with "embedded" SiO ₂ regions (as well as silicon nitride equivalents) are exemplary substrates that can be used to fabricate the transistor of the present invention. Alternatively, in a preferred embodiment, the structuring step includes forming one or more regions with “Hall Bar” and/or “Van der Pauw geometries” (such geometries or shapes are well known in the art and, for example, close a circle , a “cloverleaf”, square, rectangle and cross), preferably cross-shaped areas, of the plasma-resistant dielectric. These geometries are known in the art for Hall sensors (which require at least 4 contacts), with the cross being the most preferred geometry and thus the precursor of the electronic device is preferably used to form a Hall sensor.

In embodiments that include forming an array of covered regions, the method preferably further comprises a step of dicing the substrate to separate electronic device precursors from the array. Thus, multiple device precursors can be fabricated simultaneously on a single substrate and then divided for individual use. This dividing step is preferably carried out towards the end of the process.

In a preferred embodiment of the present invention, the step of structuring includes structuring the plasma-resistant dielectric by physical vapor deposition, such as. B. e-jet evaporation or thermal evaporation. Preferably, e-beam evaporation is used to pattern the plasma resistant dielectric and is preferably performed using a mask (i.e., a shadow mask). Such a process is particularly suitable for the deposition of an aluminum oxide or silicon dioxide resistant dielectric layer on 2D material layers.

Preferably, the thickness of the structured dielectric is less than 200 nm, preferably less than 100 nm, more preferably less than 50 nm and/or greater than 1 nm, preferably greater than 3 nm, more preferably greater than 5 nm. Accordingly, the dielectric layer have a thickness between 1 nm and 200 nm, preferably between 3 nm and 100 nm and even more preferably between 5 nm and 50 nm.

The method further comprises subjecting the intermediate product to a plasma etching, wherein the at least one uncovered region of the layer structure is etched away to form at least one covered region of the layer structure with an exposed edge surface. The plasma etching step results in all uncovered regions of the plasma etchable layer structure being etched, exposing the underlying substrate in those areas. The plasma resistant dielectric prevents etching of the layered structure in the covered regions and therefore the plasma etching results in the formation of an exposed edge of the layered structure simultaneously with the shape of the patterned dielectric thereon. Thus, as described herein, 2D material layers extend above (and below) the covered regions of the layered structure to the exposed edge surface. Accordingly, the shape or pattern of the dielectric defines the shape of the etched 2D material layer.

Plasma etching is a typical process used in the manufacturing of electronic devices and integrated circuits. Plasma etching involves the flow of a plasma of a suitable gas mixture over the substrate, the plasma being formed from the application of an RF across two electrodes, typically under low pressure. With oxygen plasma ionization, the RF radiation ionizes the gas to form oxygen radicals that etch the layered structure. The by-products, also known in the art as "ash", are removed by a pump, which are predominantly carbon monoxide and carbon dioxide, when a graphene layer structure is etched by oxygen plasma etching. In a preferred embodiment, the plasma etching comprises oxygen plasma etching. In a preferred embodiment, the oxygen plasma etching comprises using at least 5 W of RF power, preferably at least 10 W and more preferably at least 20 W, and preferably less than 200 W, preferably less than 100 W. The flow rate of O ₂ may be at least 1 sccm, preferably at least 3 sccm and/or less than 50 sccm, preferably less than 30 sccm. The chamber pressure is preferably at least 0.1 mbar and/or a maximum of 100 mbar, preferably at least 0.2 mbar and/or a maximum of 10 mbar. Accordingly, the time required for plasma etching can be as short as possible, about 1 second and/or up to 5 minutes. Preferably the time required is at least 10 seconds and/or less than 2 minutes.

Finally, the method of the present invention further includes a step of forming an ohmic contact (i.e., at least one ohmic contact) in direct contact with a portion of the exposed edge surface. Additional contacts can also be formed and formed at the same time. In this case, additional contacts are also provided in direct contact with the exposed edge surface, but separate from other contacts (i.e., the contacts are not in contact with each other). Preferably, the one or more ohmic contacts are metal contacts, preferably comprising one or more of titanium, aluminum, and chromium. Preferably the contacts are titanium and/or gold metal contacts. The contacts can be formed by any standard technique such as electron beam deposition, preferably using a mask.

The inventors have found that the dielectric layer not only protects the underlying 2D material from atmospheric contamination, but also prevents the contacts from forming on the surface of the 2D material. Therefore, the 2D material is essentially protected from metal doping since contact occurs only at the exposed edge and by avoiding wet lithography techniques, including avoiding etchants such as BOE, improved contact between the ohmic contact and the graphene can be achieved. Furthermore, the inventors have found that charge injection at the edge of the 2D material is significantly more efficient as a result.

While the protective dielectric layer serves to limit contamination of the graphene surface and is still very effective, especially over long periods of time, the inventors have found that the exposed edges can provide a pathway for contamination and doping of the 2D material. While this process is significantly slower than surface doping and can only occur on a limited scale, the inventors have found that stability and durability can be further improved by providing a further protective layer or a coating that is air (and moisture) resistant. is consistent. As described herein, for devices such as Hall sensors, the operation of devices based on 2D materials can be very sensitive to changes in carrier density (i.e., due to doping by impurities, primarily oxygen and water vapor, which are atmospheric contaminants). The inventors have found that devices based on shapes with many edges, such as the cross-sectional shape of a Hall sensor, are more susceptible to contamination and therefore benefit greatly from further coating. Consequently, the method provides more robust devices than those of the prior art.

Accordingly, the method described herein preferably further comprises, either before or after forming the one or more ohmic contacts, a step of forming a coating to provide the layered structure (and its patterned dielectric) with a continuous air-resistant coating. The continuous air-resistant coating therefore coats at least the layered structure (comprising the etched 2D material layers and patterned dielectric) and adjacent regions of the substrate to enclose the layered structure and protect any remaining portions of the exposed edge (i.e., any edges that are not in direct contact with the ohmic contact). As described herein, the coating may be structured to leave a portion of the contact exposed for connection to circuitry. Alternatively, the coating may be formed over the substrate and coat the entire substrate, through the entire layer structure (and edges) and all of the one or more contacts.

The air-resistant coating can be called a hermetic coating. The coating can have an oxygen transfer rate of less than 10 ^-1 cm ³ /m ² /day/atm, preferably less than 10 ^-3 cm ³ /m ² /day/atm and more preferably be characterized as less than 10 ^-5 cm ³ /m ² /day/atm. The air-resistant coating may also be characterized by a water vapor transmission rate of less than 10 ^-2 g/m ² /day, preferably less than 10 ^-4 g ^/ m ² /day, more preferably less than 10 ^-5 g/m ² /day. Such transmission rates are generally accepted as required for use in electronic devices such as LEDs, with the more preferred transmission rates required for OLED and Hall sensors.

The inventors have also found that the use of plasma etching to etch the layer structure in the uncoated areas is particularly advantageous when combined with further coating. This is because the plasma etching step does not cause deposits to form on the layer structure or substrate and does not affect the substrate surface roughness (for example, through pitting), which can result from alternative techniques such as laser etching. This in turn leads to a significant improvement in the properties of the coating.

Preferably the coating is an inorganic oxide, nitride, carbide, fluoride or sulfide, preferably aluminum oxide or silicon dioxide. Preferably the thickness of the coating is greater than 10 nm, preferably greater than 25 nm and more preferably greater than 50 nm. There is no specific upper limit, although thicknesses greater than 10 pm or greater than 1 pm may provide only limited further protective properties, while the weight and thickness of the device precursor is simply increased. Additionally, deposition rates by ALD, for example, can be a slow process and thicker coatings would unduly increase manufacturing time. Accordingly, an ALD layer thickness of not greater than 500 nm or not greater than 100 nm is also preferred.

The inventors have found different solutions to various problems encountered in the manufacture of such electronic device precursors that include coating, each solution having its own advantages and disadvantages as described herein.

A preferred embodiment of the present invention includes forming the coating after the ohmic contact and thus forming the ohmic contact on the plasma-resistant substrate. In this embodiment, the coating is formed by Atomic Layer Deposition (ALD) over the plasma resistant substrate to provide the at least one covered area of the layer structure, the ohmic contact and the remaining exposed edge surface with a continuous air resistant coating.

ALD is a technique known in the art and involves reacting at least two precursors in a sequential, self-limiting manner. Repeated cycles to the separate precursors allow the growth of a thin film in a conformal manner (i.e., with uniform thickness across the entire substrate) due to the layer-by-layer growth mechanism. Aluminum oxide is a particularly preferred coating material and can be formed by sequential exposure to trimethyl aluminum (TMA) and an oxygen source, preferably one or more of water (H ₂ O), O ₂ and ozone (O ₃ ), preferably with water. ALD is particularly advantageous because a coating can be reliably formed over the entire substrate (ie, it provides a conformal coating). However, the inventors have also found that while an excellent protective coating layer can be formed by ALD, complete coating can lead to problems in cutting where an array of electronic device precursors is fabricated on the substrate. Dicing (or cutting) then necessarily involves dicing through the coating to separate the individual device precursors, and this process can be prone to introducing microcracks in the coating.

Such a coating also coats the entire contact, sealing the contact. The inventors have nevertheless discovered that wire bonding can be used to pierce the coating and attach a wire to the contact. Thus, the method preferably includes wire bonding to the ohmic contacts of the device precursor through the coating. While ALD provides a particularly uniform protective layer, the coating can be damaged when piercing to make the wire bond contact.

The inventors thus developed a further preferred embodiment in which ohmic contact is formed before the coating and thus on the plasma-resistant substrate, but the coating is formed by structuring a coating on the plasma-resistant substrate in order to cover the at least one covered area of the layer structure and the to provide remaining exposed edge surface with a continuous air-resistant coating.

The coating is preferably carried out using the same as described herein Technology structured in terms of dielectric structuring. One difference is that the pattern is geometrically larger to cover the exposed edges of the layer structure and thus the adjacent portion of the substrate as well as a portion of the contact, thereby exposing a portion of the contact. Structuring of, for example, aluminum oxide can again be carried out using e-beam evaporation.

This embodiment is therefore advantageous because the portions of the substrate between adjacent layer structures of an array (or simply portions of the substrate) are exposed (and may be referred to as "roads" or "die strips"). The substrate can therefore be divided without damaging the coating. Additionally, because the contact is exposed, the contact can be wire bonded without risk of damage or cracking in the coating, or alternatively a solder ball can be deposited on the contact.

In contrast to the use of ALD, evaporation is less conformal and there is a risk of leaving the edges exposed. In particular, e-beam evaporation in these shadows is directional, particularly those generated by contact, limiting uniform growth of the coating. However, it is known in the art to rotate the substrate during coating to minimize this effect.

Another preferred embodiment instead provides the coating prior to forming the contact and includes selectively etching one or more portions of the coating to expose corresponding portions of the edge surface. The step of forming a contact then includes forming an ohmic contact in direct contact with each exposed portion of the edge surface.

The coating can therefore be provided by ALD or e-beam evaporation. Since this embodiment involves forming the coating in front of any ohmic contacts, even better coatings can be achieved even with e-beam evaporation, keeping the roads clear. The inventors have determined that the coating must be etched in selective portions to expose the corresponding portions of the underlying edge surface to allow the ohmic contact to be formed. The selective etching is preferably performed using laser etching, reactive ion etching (in a so-called “dry etching”), chemical etching (in a so-called “wet etching”) and/or photolithography. Since the 2D material is essentially protected from contamination, such methods can be used without significant adverse effects. However, laser etching and reactive ion etching are preferred as these are “dry” processes with reduced doping of the 2D material, with reactive ion etching being the most preferred. In some embodiments, the selective etching may be performed for a time sufficient to etch away the coating to expose the corresponding edge surface of the plasma-etchable structure.

This process then requires the formation of the ohmic contact in direct contact with the edge surfaces exposed by the selective etching in each etched section. This is advantageous because the contact is therefore exposed for connection to an electronic circuit. In particular, the method may further comprise depositing a solder ball (or a solder ball) on the ohmic contact. This allows the precursor of the electronic device to be used as a so-called “flip chip”. However, wire bonding is also preferred. Wire bonding is known in the art and may include ball bonding, wedge bonding, or compatible bonding.

However, the inventors have discovered that this embodiment introduces additional complexity in the alignment required for selective etching and contact deposition within the selectively etched portion. Etching still involves the risk of cracks forming in the coating.

• ein Substrat mit einer Schichtstruktur darauf, wobei die Schichtstruktur umfasst:
  • eine untere Schicht auf einer ersten Region des Substrats, wobei die untere Schicht eine oder mehrere Graphenschichten umfasst, die sich über die untere Schicht erstrecken, und
  • eine obere Schicht auf der unteren Schicht, die aus einem dielektrischen Material gebildet ist,
  • wobei die untere und obere Schicht gemeinsam eine durchgehende Außenrandoberfläche nutzen,
• einen ohmschen Kontakt, der auf einer weiteren Region des Substrats bereitgestellt ist und in direktem Kontakt mit der einen oder den mehreren Graphenschichten über die durchgehende Außenrandoberfläche steht, und
• eine durchgehende luftbeständige Beschichtung auf dem Substrat, die Schichtstruktur und mindestens einen ohmschen Kontakt.

In a seventh aspect of the present invention there is provided an electronic device precursor comprising:

• a substrate having a layer structure thereon, the layer structure comprising:
  • a bottom layer on a first region of the substrate, the bottom layer comprising one or more graphene layers extending over the bottom layer, and
  • an upper layer on the lower layer formed from a dielectric material,
  • whereby the lower and upper layers share a continuous outer edge surface,
• an ohmic contact provided on another region of the substrate and in direct contact with the one or more graphene layers via the continuous outer edge surface, and
• a continuous air-resistant coating on the substrate, the layer structure and at least one ohmic contact.

• ein Substrat mit einer Schichtstruktur darauf, wobei die Schichtstruktur umfasst:
  • eine untere Schicht auf einer ersten Region des Substrats, wobei die untere Schicht eine oder mehrere Graphenschichten umfasst, die sich über die untere Schicht erstrecken, und
  • eine obere Schicht auf der unteren Schicht, die aus einem dielektrischen Material gebildet ist,
  • wobei die untere und obere Schicht gemeinsam eine durchgehende Außenrandoberfläche nutzen,
• einen ohmschen Kontakt, der auf einer weiteren Region des Substrats bereitgestellt ist und in direktem Kontakt mit der einen oder den mehreren Graphenschichten über die durchgehende Außenrandoberfläche steht, und
• eine durchgehende luftbeständige Beschichtung, die die Schichtstruktur umschließt.

In an eighth aspect of the present invention there is provided an electronic device precursor comprising:

• a substrate having a layer structure thereon, the layer structure comprising:
  • a bottom layer on a first region of the substrate, the bottom layer comprising one or more graphene layers extending over the bottom layer, and
  • an upper layer on the lower layer formed from a dielectric material,
  • whereby the lower and upper layers share a continuous outer edge surface,
• an ohmic contact provided on another region of the substrate and in direct contact with the one or more graphene layers via the continuous outer edge surface, and
• a continuous air-resistant coating that encloses the layered structure.

• ein Substrat mit einer Schichtstruktur darauf, wobei die Schichtstruktur umfasst:
  • eine untere Schicht auf einer ersten Region des Substrats, wobei die untere Schicht eine oder mehrere Graphenschichten umfasst, die sich über die untere Schicht erstrecken, und
  • eine obere Schicht auf der unteren Schicht, die aus einem dielektrischen Material gebildet ist,
  • wobei die untere und obere Schicht gemeinsam eine durchgehende Außenrandoberfläche nutzen,
• einen ohmschen Kontakt, der in direktem Kontakt mit der einen oder den mehreren Graphenschichten über die durchgehende Außenrandoberfläche steht; und
• eine durchgehende luftbeständige Beschichtung, die die Schichtstruktur umschließt.

In a ninth aspect of the present invention there is provided an electronic device precursor comprising:

• a substrate having a layer structure thereon, the layer structure comprising:
  • a bottom layer on a first region of the substrate, the bottom layer comprising one or more graphene layers extending over the bottom layer, and
  • an upper layer on the lower layer formed from a dielectric material,
  • whereby the lower and upper layers share a continuous outer edge surface,
• an ohmic contact in direct contact with the one or more graphene layers via the continuous outer edge surface; and
• a continuous air-resistant coating that encloses the layered structure.

The electronic device precursor of the further aspects of the invention disclosed herein is preferably obtainable by the method described herein. Accordingly, all features described with respect to the sixth aspect can be equally applied to the other aspects of the invention. The features described with respect to the sixth aspect can also be applied to the first to fifth aspects of the invention.

Accordingly, the electronic device precursor of further aspects of the invention shares the feature of a layered structure comprising a lower layer comprising one or more graphene layers and an upper layer formed of a dielectric material, the lower and upper layers being each other share a continuous outer edge surface. This therefore provides the graphene with excellent protection from atmospheric contamination, resulting in improved stability of device performance over longer periods of time and through the lifetime.

Furthermore, an ohmic contact is provided for connection to an electronic circuit, and the ohmic contact is only in direct contact with the edge of the graphene layer and not the upper (or lower) flat surface. The edge contact provides improved charge injection relative to surface contacts and essentially avoids doping of the graphene. This is particularly useful when the device precursor is intended for use at high temperatures, where the elevated temperature may result in doping of the 2D material by, for example, the metal of an ohmic contact after fabrication and during subsequent use.

In a preferred embodiment of the present invention, the precursor of the electronic device is a transistor or a Hall sensor, preferably a Hall sensor (e.g. a graphene Hall sensor according to the first aspect). However, many other electronic devices can be fabricated using the method described herein and/or from the electronic device precursors described herein and include capacitors, diodes and inductors.

1. (i) Bereitstellen einer plasmaätzbaren Schichtstruktur auf einem plasmabeständigen Substrat, wobei die Schichtstruktur eine freiliegende obere Oberfläche aufweist;
2. (ii) Strukturieren eines plasmabeständigen Dielektrikums auf der freiliegenden oberen Oberfläche, um ein Zwischenprodukt mit mindestens einem bedeckten Bereich und mindestens einem unbedeckten Bereich der Schichtstruktur zu bilden,
3. (iii) Unterziehen des Zwischenprodukts einer Plasmaätzung, wobei der mindestens eine unbedeckte Bereich der Schichtstruktur weggeätzt wird, um mindestens einen bedeckten Bereich der Schichtstruktur mit einer freiliegenden Randoberfläche zu bilden;
4. (iv) Bilden eines ohmschen Kontakts auf dem plasmabeständigen Substrat in direktem Kontakt mit einem Abschnitt der freiliegenden Randoberfläche;
5. (v) Bilden der Beschichtung durch ALD über dem plasmabeständigen Substrat, um den mindestens einen bedeckten Bereich der Schichtstruktur, den ohmschen Kontakt und die verbleibende freiliegende Randoberfläche mit einer durchgehenden luftbeständigen Beschichtung;

wobei die plasmaätzbare Schichtstruktur eine oder mehrere Graphenschichten umfasst oder aus diesen besteht, die sich über die bedeckten Regionen der Schichtstruktur zu der freiliegenden Randoberfläche erstrecken. Somit wird der elektronische Vorrichtungsvorläufer des hierin beschriebenen siebten Gesichtspunkts vorzugsweise durch dieses Verfahren erhalten, noch stärker bevorzugt erhalten.In a particularly preferred embodiment of the present invention, the method described herein comprises the following:

1. (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed top surface;
2. (ii) patterning a plasma resistant dielectric on the exposed top surface to form an intermediate product with at least one covered area and at least to form at least one uncovered area of the layer structure,
3. (iii) subjecting the intermediate product to a plasma etch, wherein the at least one uncovered region of the layered structure is etched away to form at least a covered region of the layered structure with an exposed edge surface;
4. (iv) forming an ohmic contact on the plasma resistant substrate in direct contact with a portion of the exposed edge surface;
5. (v) forming the coating by ALD over the plasma resistant substrate to surround the at least one covered region of the layered structure, the ohmic contact and the remaining exposed edge surface with a continuous air resistant coating;

wherein the plasma-etchable layer structure comprises or consists of one or more graphene layers extending over the covered regions of the layer structure to the exposed edge surface. Thus, the electronic device precursor of the seventh aspect described herein is preferably obtained, more preferably obtained, by this method.

The device precursor of the seventh aspect includes a continuous air-resistant coating over the substrate, the layered structure and the at least one ohmic contact, and may also be considered to comprise the layered structure according to the eighth and ninth aspects disclosed herein.

1. (i) Bereitstellen einer plasmaätzbaren Schichtstruktur auf einem plasmabeständigen Substrat, wobei die Schichtstruktur eine freiliegende obere Oberfläche aufweist;
2. (ii) Strukturieren eines plasmabeständigen Dielektrikums auf der freiliegenden oberen Oberfläche, um ein Zwischenprodukt mit mindestens einem bedeckten Bereich und mindestens einem unbedeckten Bereich der Schichtstruktur zu bilden,
3. (iii) Unterziehen des Zwischenprodukts einer Plasmaätzung, wobei der mindestens eine unbedeckte Bereich der Schichtstruktur weggeätzt wird, um mindestens einen bedeckten Bereich der Schichtstruktur mit einer freiliegenden Randoberfläche zu bilden;
4. (iv) Bilden eines ohmschen Kontakts auf dem plasmabeständigen Substrat in direktem Kontakt mit einem Abschnitt der freiliegenden Randoberfläche;
5. (v) Strukturieren der Beschichtung auf dem plasmabeständigen Substrat, um den mindestens einen bedeckten Bereich der Schichtstruktur und die verbleibende freiliegende Randoberfläche mit einer durchgehenden luftbeständigen Beschichtung bereitzustellen;

wobei die plasmaätzbare Schichtstruktur eine oder mehrere Graphenschichten umfasst oder aus diesen besteht, die sich über die bedeckten Regionen der Schichtstruktur zu der freiliegenden Randoberfläche erstrecken. Somit wird der elektronische Vorrichtungsvorläufer des hierin beschriebenen achten und/oder neunten Gesichtspunkts vorzugsweise durch dieses Verfahren erhalten, noch stärker bevorzugt erhalten.In a particularly preferred embodiment of the present invention, the method described herein comprises the following:

1. (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed top surface;
2. (ii) patterning a plasma-resistant dielectric on the exposed top surface to form an intermediate product having at least one covered area and at least one uncovered area of the layered structure,
3. (iii) subjecting the intermediate product to a plasma etch, wherein the at least one uncovered region of the layered structure is etched away to form at least a covered region of the layered structure with an exposed edge surface;
4. (iv) forming an ohmic contact on the plasma resistant substrate in direct contact with a portion of the exposed edge surface;
5. (v) patterning the coating on the plasma resistant substrate to provide the at least one covered region of the layered structure and the remaining exposed edge surface with a continuous air resistant coating;

wherein the plasma-etchable layer structure comprises or consists of one or more graphene layers extending over the covered regions of the layer structure to the exposed edge surface. Thus, the electronic device precursor of the eighth and/or ninth aspects described herein is preferably obtained, even more preferably obtained, by this method.

1. (i) Bereitstellen einer plasmaätzbaren Schichtstruktur auf einem plasmabeständigen Substrat, wobei die Schichtstruktur eine freiliegende obere Oberfläche aufweist;
2. (ii) Strukturieren eines plasmabeständigen Dielektrikums auf der freiliegenden oberen Oberfläche, um ein Zwischenprodukt mit mindestens einem bedeckten Bereich und mindestens einem unbedeckten Bereich der Schichtstruktur zu bilden,
3. (iii) Unterziehen des Zwischenprodukts einer Plasmaätzung, wobei der mindestens eine unbedeckte Bereich der Schichtstruktur weggeätzt wird, um mindestens einen bedeckten Bereich der Schichtstruktur mit einer freiliegenden Randoberfläche zu bilden;
4. (iv) Bilden der Beschichtung auf dem plasmabeständigen Substrat, um den mindestens einen bedeckten Bereich der Schichtstruktur und die freiliegende Randoberfläche mit einer durchgehenden luftbeständigen Beschichtung bereitzustellen;
5. (v) selektives Ätzen eines oder mehrerer Abschnitte der Beschichtung, um entsprechende Abschnitte der Randoberfläche freizugeben;
6. (vi) Bilden eines ohmschen Kontakts in direktem Kontakt mit jedem freiliegenden Abschnitt der Randoberfläche;

wobei die plasmaätzbare Schichtstruktur eine oder mehrere Graphenschichten umfasst oder aus diesen besteht, die sich über die bedeckten Regionen der Schichtstruktur zu der freiliegenden Randoberfläche erstrecken. Somit wird der elektronische Vorrichtungsvorläufer des hierin beschriebenen neunten Gesichtspunkts vorzugsweise durch dieses Verfahren erhalten, noch stärker bevorzugt erhalten.In a particularly preferred embodiment of the present invention, the method described herein comprises the following:

1. (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed top surface;
2. (ii) patterning a plasma-resistant dielectric on the exposed top surface to form an intermediate product having at least one covered area and at least one uncovered area of the layered structure,
3. (iii) subjecting the intermediate product to a plasma etch, wherein the at least one uncovered region of the layered structure is etched away to form at least a covered region of the layered structure with an exposed edge surface;
4. (iv) forming the coating on the plasma resistant substrate to provide the at least one covered region of the layered structure and the exposed edge surface with a continuous air resistant coating;
5. (v) selectively etching one or more portions of the coating to expose corresponding portions of the edge surface;
6. (vi) forming an ohmic contact in direct contact with each exposed portion of the edge surface;

wherein the plasma-etchable layer structure comprises or consists of one or more graphene layers extending over the covered regions of the Layer structure extend to the exposed edge surface. Thus, the electronic device precursor of the ninth aspect described herein is preferably obtained, more preferably obtained, by this method.

1. (i) Bereitstellen einer Monoschicht von Graphen auf einem Saphirsubstrat durch MOCVD, wobei die Monoschicht von Graphen eine freiliegende obere Oberfläche aufweist;
2. (ii) Strukturieren von Aluminiumoxid als einen oder mehrere kreuzförmige Regionen auf der freiliegenden oberen Oberfläche, um ein Zwischenprodukt mit mindestens einem bedeckten Bereich und mindestens einem unbedeckten Bereich des Graphenmonomers zu bilden;
3. (iii) Unterziehen des Zwischenprodukts einer Sauerstoffplasmaätzung, wobei der mindestens eine unbedeckte Bereich der Monoschicht von Graphen weggeätzt wird, um mindestens einen abgedeckten Bereich von Monoschicht-Graphen mit einer freiliegenden Randoberfläche zu bilden;
4. (iv) Bilden von vier ohmschen Gold-Kontakten für jeden kreuzförmigen Bereich, der in Schritt (ii) auf dem Saphirsubstrat ausgebildet ist, wobei jeder Kontakt in direktem Kontakt mit einem distalen Abschnitt der freiliegenden Randoberfläche der vier Arme des Kreuzes steht;
5. (v) Bilden einer Aluminiumoxidbeschichtungsschicht durch ALD über dem Saphirsubstrat, um den mindestens einen abgedeckten Bereich von Monoschicht-Graphen, den ohmschen Kontakten und verbleibenden freiliegenden Randoberflächen mit einer kontinuierlichen luftbeständigen Beschichtung bereitzustellen;

wobei sich die Monoschicht von Graphen über den mindestens einen abgedeckten Bereich zu der freiliegenden Randoberfläche erstreckt und der Vorläufer der elektronischen Vorrichtung zum Bilden eines Hall-Sensors dient.In a more preferred embodiment of the present invention, the method described herein comprises the following:

1. (i) providing a monolayer of graphene on a sapphire substrate by MOCVD, the monolayer of graphene having an exposed top surface;
2. (ii) patterning alumina as one or more cross-shaped regions on the exposed top surface to form an intermediate having at least one covered region and at least one uncovered region of the graphene monomer;
3. (iii) subjecting the intermediate product to an oxygen plasma etch, wherein the at least one uncovered region of the monolayer of graphene is etched away to form at least one covered region of monolayer graphene with an exposed edge surface;
4. (iv) forming four gold ohmic contacts for each cross-shaped region formed on the sapphire substrate in step (ii), each contact being in direct contact with a distal portion of the exposed edge surface of the four arms of the cross;
5. (v) forming an aluminum oxide coating layer by ALD over the sapphire substrate to provide the at least one covered region of monolayer graphene, the ohmic contacts and remaining exposed edge surfaces with a continuous air-resistant coating;

wherein the monolayer of graphene extends over the at least one covered area to the exposed edge surface and the precursor of the electronic device serves to form a Hall sensor.

• ein Saphirsubstrat mit einer Schichtstruktur darauf, wobei die Schichtstruktur umfasst:
  • eine Monoschicht aus Graphen auf einer ersten Region des Saphirsubstrats, und
  • eine Aluminiumoxidschicht auf der Graphen-Monoschicht,
  • wobei das Graphen und das Aluminiumoxid kreuzförmig sind und eine gemeinsame durchgehende Außenrandoberfläche aufweisen,
• vier ohmsche Goldkontakte, wobei jeder Kontakt auf einer weiteren Region des Saphirsubstrats bereitgestellt ist und in direktem Kontakt mit einem distalen Abschnitt der Randfläche jedes der vier Arme eines jeden Kreuzes steht, und
• eine kontinuierliche Aluminiumoxidbeschichtungsschicht über dem Saphirsubstrat, der Schichtstruktur und den Kontakten.

Accordingly, a preferred precursor for electronic devices is one for a Hall sensor and includes:

• a sapphire substrate having a layered structure thereon, the layered structure comprising:
  • a monolayer of graphene on a first region of the sapphire substrate, and
  • an aluminum oxide layer on the graphene monolayer,
  • wherein the graphene and the aluminum oxide are cross-shaped and have a common continuous outer edge surface,
• four ohmic gold contacts, each contact being provided on a further region of the sapphire substrate and in direct contact with a distal portion of the edge surface of each of the four arms of each cross, and
• a continuous aluminum oxide coating layer over the sapphire substrate, layer structure and contacts.

1. (i) Bereitstellen einer Monoschicht von Graphen auf einem Saphirsubstrat durch MOCVD, wobei die Monoschicht von Graphen eine freiliegende obere Oberfläche aufweist;
2. (ii) Strukturieren von Aluminiumoxid als einen oder mehrere kreuzförmige Regionen auf der freiliegenden oberen Oberfläche, um ein Zwischenprodukt mit mindestens einem bedeckten Bereich und mindestens einem unbedeckten Bereich des Graphenmonomers zu bilden;
3. (iii) Unterziehen des Zwischenprodukts einer Sauerstoffplasmaätzung, wobei der mindestens eine unbedeckte Bereich der Monoschicht von Graphen weggeätzt wird, um mindestens einen abgedeckten Bereich von Monoschicht-Graphen mit einer freiliegenden Randoberfläche zu bilden;
4. (iv) Bilden von vier ohmschen Gold-Kontakten für jeden kreuzförmigen Bereich, der in Schritt (ii) auf dem Saphirsubstrat ausgebildet ist, wobei jeder Kontakt in direktem Kontakt mit einem distalen Abschnitt der freiliegenden Randoberfläche der vier Arme eines jeden Kreuzes steht;
5. (v) Strukturieren einer Aluminiumoxidbeschichtungsschicht durch e-Strahlverdampfung über dem Saphirsubstrat, um den mindestens einen bedeckten Bereich von Monoschicht-Graphen und verbleibenden freiliegenden Randoberflächen mit einer kontinuierlichen luftbeständigen Beschichtung bereitzustellen;

wobei sich die Monoschicht von Graphen über den mindestens einen abgedeckten Bereich zu der freiliegenden Randoberfläche erstreckt und der Vorläufer der elektronischen Vorrichtung zum Bilden eines Hall-Sensors dient.In a further, even more preferred embodiment of the present invention, the method described herein comprises the following:

1. (i) providing a monolayer of graphene on a sapphire substrate by MOCVD, the monolayer of graphene having an exposed top surface;
2. (ii) patterning alumina as one or more cross-shaped regions on the exposed top surface to form an intermediate having at least one covered region and at least one uncovered region of the graphene monomer;
3. (iii) subjecting the intermediate product to an oxygen plasma etch, wherein the at least one uncovered region of the monolayer of graphene is etched away to form at least one covered region of monolayer graphene with an exposed edge surface;
4. (iv) forming four gold ohmic contacts for each cross-shaped region formed on the sapphire substrate in step (ii), each contact being in direct contact with a distal portion of the exposed edge surface of the four arms of each cross;
5. (v) patterning an aluminum oxide coating layer by e-beam evaporation over the sapphire substrate to provide the at least one covered region of monolayer graphene and remaining exposed edge surfaces with a continuous air-resistant coating;

wherein the monolayer of graphene extends over the at least one covered area to the exposed edge surface and the precursor of the electronic device serves to form a Hall sensor.

1. (i) Bereitstellen einer Monoschicht von Graphen auf einem Saphirsubstrat durch MOCVD, wobei die Monoschicht von Graphen eine freiliegende obere Oberfläche aufweist;
2. (ii) Strukturieren von Aluminiumoxid als einen oder mehrere kreuzförmige Regionen auf der freiliegenden oberen Oberfläche, um ein Zwischenprodukt mit mindestens einem bedeckten Bereich und mindestens einem unbedeckten Bereich des Graphenmonomers zu bilden;
3. (iii) Unterziehen des Zwischenprodukts einer Sauerstoffplasmaätzung, wobei der mindestens eine unbedeckte Bereich der Monoschicht von Graphen weggeätzt wird, um mindestens einen abgedeckten Bereich von Monoschicht-Graphen mit einer freiliegenden Randoberfläche zu bilden;
4. (v) Bilden einer Aluminiumoxidbeschichtungsschicht auf dem Saphirsubstrat, um den mindestens einen bedeckten Bereich von Monoschicht-Graphen und der freiliegenden Randoberfläche mit einer kontinuierlichen luftbeständigen Beschichtung bereitzustellen;
5. (v) selektives Laserätzen von vier Abschnitten der Aluminiumoxidbeschichtungsschicht, um entsprechende Abschnitte der Randoberfläche der Graphenschicht freizulegen, um die distalen Abschnitte der Randoberfläche der vier Arme jedes Kreuzes freizugeben;
6. (vi) Bilden eines ohmschen Gold-Kontakts in direktem Kontakt mit jedem der vier freiliegenden Abschnitt der Randoberfläche;

wobei sich die Monoschicht von Graphen über den mindestens einen abgedeckten Bereich zu der freiliegenden Randoberfläche erstreckt und der Vorläufer der elektronischen Vorrichtung zum Bilden eines Hall-Sensors dient.Similarly, in a further, even more preferred embodiment, the above includes underlying invention, the method described herein is as follows:

1. (i) providing a monolayer of graphene on a sapphire substrate by MOCVD, the monolayer of graphene having an exposed top surface;
2. (ii) patterning alumina as one or more cross-shaped regions on the exposed top surface to form an intermediate having at least one covered region and at least one uncovered region of the graphene monomer;
3. (iii) subjecting the intermediate product to an oxygen plasma etch, wherein the at least one uncovered region of the monolayer of graphene is etched away to form at least one covered region of monolayer graphene with an exposed edge surface;
4. (v) forming an aluminum oxide coating layer on the sapphire substrate to provide the at least one covered region of monolayer graphene and the exposed edge surface with a continuous air-resistant coating;
5. (v) selectively laser etching four portions of the aluminum oxide coating layer to expose corresponding portions of the edge surface of the graphene layer to expose the distal portions of the edge surface of the four arms of each cross;
6. (vi) forming a gold ohmic contact in direct contact with each of the four exposed portions of the edge surface;

wherein the monolayer of graphene extends over the at least one covered area to the exposed edge surface and the precursor of the electronic device serves to form a Hall sensor.

• ein Saphirsubstrat mit einer Schichtstruktur darauf, wobei die Schichtstruktur umfasst:
  • eine Monoschicht aus Graphen auf einer ersten Region des Saphirsubstrats, und
  • eine Aluminiumoxidschicht auf der Graphen-Monoschicht,
  • wobei das Graphen und das Aluminiumoxid kreuzförmig sind und eine gemeinsame durchgehende Außenrandoberfläche aufweisen,
• vier ohmsche Goldkontakte, wobei jeder Kontakt auf einer weiteren Region des Saphirsubstrats bereitgestellt ist und in direktem Kontakt mit einem distalen Abschnitt der Randfläche jedes der vier Arme eines des Kreuzes steht, und
• eine durchgehende Aluminiumoxidschicht, die die Schichtstruktur umschließt.

Accordingly, a preferred precursor for electronic devices is one for a Hall sensor and includes:

• a sapphire substrate having a layered structure thereon, the layered structure comprising:
  • a monolayer of graphene on a first region of the sapphire substrate, and
  • an aluminum oxide layer on the graphene monolayer,
  • wherein the graphene and the aluminum oxide are cross-shaped and have a common continuous outer edge surface,
• four ohmic gold contacts, each contact being provided on a further region of the sapphire substrate and in direct contact with a distal portion of the edge surface of each of the four arms of one of the cross, and
• a continuous aluminum oxide layer that encloses the layer structure.

Thus, a preferred precursor for electronic devices includes an aluminum oxide coating layer that encapsulates the layered structure and protects the edges of the graphene layer. The contact of the device precursor is at least partially exposed, i.e. H. not coated by the aluminum oxide coating layer, and the sapphire substrate is at least partially exposed. Typically, at least portions of the substrate are arranged between adjacent device precursors as part of an array to allow dicing of the common substrate to provide a plurality of device precursors without risk of damaging the coating during cutting.

In embodiments in which the coating is first deposited to expose the edge surface of the graphene to provide such an electronic device precursor, the contact is vertically exposed by depositing into a laser-etched opening in the coating.

In embodiments in which the coating is patterned after forming contacts, partially coating the contact during patterning may expose a top surface of the contact. However, it is also possible to pattern the coating over the top surface of the contact and at least one edge surface is exposed by the patterning of the coating. In other words, the contacts in the final electronic device precursor are not completely encapsulated by the coating, allowing easy wire bonding or soldering to connect to an electronic circuit without having to puncture the coating.

BRIEF DESCRIPTION OF DRAWINGS

• - 1 zeigt ein schematisches Planansichtsdiagramm eines Graphen-Hall-Sensors gemäß einer Ausführungsform der vorliegenden Erfindung.
• - 2 ist ein Diagramm, das die Leistung zweier Graphen-Hall-Sensoren mit unterschiedlichen Lagenträgerdichten bei 4 K vergleicht;
• - 3 ist ein Diagramm, das die Linearitätsfehler für die zwei Graphen-Hall-Sensoren mit unterschiedlichen Lagenträgerdichten vergleicht;
• - 4 ist ein Flussdiagramm, das das Verfahren der vorliegenden Erfindung veranschaulicht;
• - 5 ist eine Querschnittsansicht eines elektronischen Vorrichtungsvorläufers gemäß einer Ausführungsform der vorliegenden Erfindung;
• - 6 ist eine Querschnittsansicht eines anderen Vorläufers der elektronischen Vorrichtung gemäß einer Ausführungsform der vorliegenden Erfindung;
• - 7 ist eine Draufsicht eines anderen Vorläufers der elektronischen Vorrichtung gemäß einer Ausführungsform der vorliegenden Erfindung;
• - 8 ist eine Draufsicht eines anderen Vorläufers der elektronischen Vorrichtung gemäß einer Ausführungsform der vorliegenden Erfindung;
• - 9 ist eine perspektivische Ansicht eines Arrays von elektronischen Vorrichtungsvorläufern gemäß einer Ausführungsform der vorliegenden Erfindung;
• - 10a ist ein Diagramm, das den Hall-Widerstand eines Graphen-Hall-Sensors gemäß einer Ausführungsform der Erfindung darstellt
• - 10b ist ein Diagramm, das den Vollskala-Linearitätsfehler des Graphens für den Graphen-Hall-Sensor von 10a zeigt;
• - 11 ist ein Diagramm, das einen Vergleich der Hall-Spannung des Graphen-Hall-Sensors von 10a mit einem Hall-Sensor mit nicht-Graphen bei einer Temperatur von 4 K zeigt;
• - 12 ist ein Diagramm, das einen Vergleich der Vollskala-Linearitätsfehler der Hall-Sensoren in 11 zeigt; und
• - 13 zeigt ein Diagramm der Hall-Spannung für den Graphen-Hall-Sensor von 10a unter einem Magnetfeld mit 1,5 K.

Embodiments of the present invention will now be described with reference to the following non-limiting figures, in which:

• - 1 shows a schematic plan view diagram of a graphene Hall sensor according to an embodiment of the present invention.
• - 2 is a graph comparing the performance of two graphene Hall sensors with different sheet carrier densities at 4K;
• - 3 is a graph comparing the linearity errors for the two graphene Hall sensors with different sheet carrier densities;
• - 4 is a flowchart illustrating the method of the present invention;
• - 5 is a cross-sectional view of an electronic device precursor according to an embodiment of the present invention;
• - 6 is a cross-sectional view of another precursor of the electronic device according to an embodiment of the present invention;
• - 7 is a top view of another precursor of the electronic device according to an embodiment of the present invention;
• - 8th is a top view of another precursor of the electronic device according to an embodiment of the present invention;
• - 9 is a perspective view of an array of electronic device precursors in accordance with an embodiment of the present invention;
• - 10a is a diagram illustrating the Hall resistance of a graphene Hall sensor according to an embodiment of the invention
• - 10b is a graph showing the full-scale graphene linearity error for the graphene Hall sensor of 10a shows;
• - 11 is a diagram showing a comparison of the Hall voltage of the graphene Hall sensor of 10a with a Hall sensor showing non-graphene at a temperature of 4 K;
• - 12 is a chart comparing the full-scale linearity errors of the Hall sensors in 11 shows; and
• - 13 shows a diagram of the Hall voltage for the graphene Hall sensor from 10a under a magnetic field of 1.5 K.

DETAILED DESCRIPTION

According to an embodiment of the present invention, a Hall sensor 10 is provided. 1 shows a schematic representation (top view) of a graphene Hall sensor 10 according to an embodiment of the invention. The graphene Hall effect sensor 10 includes a graphene film, a first pair of electrical contacts 14, 15, a second pair of electrical contacts 16, 17 and a substrate 18.

In the embodiment of 1 The graphene sheet (not shown) is formed on the substrate 18 beneath an identically shaped/structured aluminum oxide (Al ₂ O ₃ ) layer 12. That is, the graphene sheet has the same shape (top view) as the aluminum oxide layer. The aluminum oxide layer 12 may have a thickness (in a plane perpendicular to the surface of the substrate) of approximately 10 nm. In the embodiment of 2 the graphene film and the aluminum oxide layer 12 are formed in a cross shape. Of course, in other embodiments, it is to be understood that other shapes for the graphene sheet and aluminum oxide layer 12 may be provided.

The ends of each of the four "arms" of the cruciform layer structure (i.e., the distal portions) of the graphene film and the patterned alumina 12 are in direct contact with a respective one of the first pair of electrical contacts 14, 15 and the second pair of electrical contacts 16, 17 .

The graphene film is provided on the substrate 18. The substrate 18 may include any suitable substrate on which the graphene sheet can be provided. For example, the substrate 18 may comprise a multilayer substrate, with one layer of the substrate providing the major surface on which the substrate is formed. For example, the substrate 18 may include a silicon wafer with a layer of Al ₂ O ₃ formed on a surface of the silicon wafer, with the exposed surface of the Al ₂ O ₃ layer providing the major surface on which the graphene sheet is provided. Alternatively, the substrate 18 may comprise a sapphire substrate or a silicon substrate.

In the embodiment of 1 the graphene film is formed on a main surface of the substrate 18. Graphene film is a film made from graphene material. The graphene film is therefore a substantially continuous layer of graphene. The graphene sheet can be formed on the substrate according to the process described at least in WO-A-2017/029470 is described. In the embodiment of 1 The graphene foil is formed on the entire major surface of the substrate 18, followed by the formation of the aluminum oxide layer 12 in the desired structure for the graphene foil and the aluminum oxide layer 12. The graphene not covered by the aluminum oxide layer 12 is then removed by plasma etching. A suitable plasma etching process may include etching for 30 s with an O ₂ flow rate of 6 sccm at 40% power on a 100 W plasma etching device.

The aluminum oxide layer 12 can be formed by thermal evaporation. Thermal evaporation can be provided using a ceramic boat to heat the material to be evaporated or by e-beam evaporation. In some embodiments, the aluminum oxide layer 12 formed has a thickness of at least 10 nm. By providing a thickness of at least 10 nm, the aluminum oxide layer can form a conformal coating that protects the underlying graphene foil from the plasma etching process.

In some embodiments, the substrate density of the graphene sheet may be tuned to provide improved sensitivity for a desired magnetic field operating range. In some embodiments, the layer support density can be selected by appropriate doping of the graphene film. For example, the graphene can be grown directly on the substrate 18 by a CVD process, for example as in WO-A-2017/029470 disclosed (and preferably monolayer graphene). After such a CVD process, the graphene may be a doped graphene monolayer grown by CVD from a precursor comprising a dopant element. Further variations in substrate density can also be achieved by optimizing reaction temperatures, reaction pressure, precursor choice, and precursor flow rate.

Depending on the maximum magnetic field to be measured by the graphene Hall sensor, the sheet support density (and hence sensitivity) can be selected in relation to a saturation limit of the device due to the quantum Hall effect.

The magnetic field at which the graphene Hall sensor saturates (a saturation limit) is inversely proportional to the sensitivity of the device. That is, a device with a lower sensitivity will saturate at a higher magnetic field than a device with a higher sensitivity. To reduce sensitivity, the layer support density can be increased. Of course, reducing the sensitivity reduces the resolution of the graphene Hall sensor.

The graphene film is formed with a sheet support density of 2 × 10 ¹¹ cm ^-2 . Thus, the graphene Hall sensor can be configured to perform magnetic field measurements within a range of at least -1 T to +1 T.

In some embodiments, the graphene sheet is formed with a substrate density of no more than 1 × 10 ¹³ cm ^-2 . By providing the graphene Hall sensor with a substrate density of no more than this size, the graphene Hall sensor can measure magnetic fields with a sensitivity of approximately 60 V/AT, which is comparable to the sensitivity of commercially available silicon-based Hall effect sensors is. However, the graphene Hall effect sensors can achieve this sensitivity at cryogenic temperatures that are well below the operating temperatures at which such silicon Hall effect sensors can operate.

In some embodiments, the graphene sheet may be formed with a substrate density of at least 1.25 x 10 ¹² cm ^-2 . Accordingly, the graphene Hall sensor can measure magnetic fields in the range of -7 T to +7 T at cryogenic temperatures. In some embodiments, the graphene sheet is formed with a sheet support density of no more than 3 × 10 ¹² cm ^-2 . Accordingly, the graphene Hall sensor can measure magnetic fields over a wide range of magnetic field strengths. For example, a graphene Hall sensor with such a carrier density is suitable for measuring magnetic fields in the range of -22 T to +22 T at cryogenic temperatures without being affected by quantum Hall effects.

In the embodiment of 1 For example, the first pair of electrical contacts 14, 15 and the second pair of electrical contacts 16, 17 may be formed in direct electrical contact with a distal end of a respective arm of the graphene sheet to make electrical contact with the graphene sheet. As in 1 shown, the electrical contacts 14, 15, 16, 17 are each rod-shaped. The electrical contacts 14, 15, 16, 17 are positioned with respect to each of the arms of the cross shape so that they contact the edge of the graphene at the ends of the cross arms. The rod-shaped electrodes extend away from the ends of the graphene film so that further electrical connections can be made to the graphene Hall effect sensor.

The first pair of electrical contacts 14, 15 are spaced along a first direction (x-direction) of the graphene sheet so that a known length of graphene is provided between the first pair of electrical contacts 14, 15. In the embodiment of 1 the first pair of electrical contacts 14, 15 are spaced apart from one another by a distance of at least 2 mm.

In some embodiments, the first pair of electrical contacts may be spaced apart by a distance of at least: 3 mm, 4 mm, 5 mm, or 10 mm. In some embodiments, the first pair of electrical contacts 14, 15 may be spaced no greater than 100 mm be spaced apart. In some embodiments, the first pair of electrical contacts may be spaced apart by a distance no greater than: 80 mm, 50 mm, 30 mm, or 20 mm.

The first pair of electrical contacts 14, 15 may comprise any suitable material for making ohmic contact with graphene. For example, the first pair of electrical contacts 14, 15 may include Ti or Au. In some embodiments, each of the first pair of electrical contacts 14, 15 may be formed from a single element, while in other embodiments, the first pair of electrical contacts 14, 15 may be formed from an alloy or a multilayer stack of materials, such as a layer of Ti can be formed by a layer of Au. In the embodiment of 1 A 10 nm thick layer (in a direction perpendicular to the substrate surface) of Ti, followed by a 120 nm thick layer of Au, is provided to form each of the electrical contacts.

The second pair of electrical contacts 16, 17 are also provided in direct electrical contact with the graphene film 12. In the embodiment of 1 the second pair of electrical contacts 16, 17 are provided on the graphene film 12 and spaced along a second direction (y-direction). As in 1 shown, the second direction is perpendicular to the first direction. The second pair of electrical contacts 16, 17 are arranged on the graphene sheet such that a path along the first direction between the first pair of electrical contacts 14, 15 crosses a path along the second direction between the second pair of electrical contacts 16, 17. That is, the path between the first pair of electrical contacts 14, 15 overlaps with the path between the second pair of electrical contacts 16, 17 to form a cross shape.

In the embodiment of 1 For example, the first pair of electrical contacts 14, 15 and the second pair of electrical contacts may be formed by thermally evaporating the one or more contact materials. The shape of the contacts can be defined by performing the thermal evaporation process through a suitable shadow mask or alternatively using a lithographic process.

As in 1 As shown, the graphene Hall effect sensor 10 may also include an encapsulation layer 20 (an air-resistant coating). The encapsulation layer 20 may be formed on the graphene foil, the aluminum oxide layer 12 and the first and second pairs of electrical contacts 14, 15, 16, 17. The encapsulation layer 20 may be provided as a substantially continuous layer. In the embodiment of 1 The encapsulation layer can be provided as a continuous air-resistant aluminum oxide coating. As in 1 shown, the encapsulation layer 20 is provided over the graphene foil and the aluminum oxide layer 12 and a portion of each of the electrical contacts 14, 15, 16, 17 in a manner sufficient to encapsulate the edges of the underlying graphene layer and a portion of each of the to leave electrical contacts 14, 15, 16, 17 exposed. The encapsulation layer 20 can be provided by electron beam evaporation.

In 1 1, the encapsulation layer 20 is illustrated as semi-transparent to illustrate the presence of the underlying patterned aluminum oxide 12. It is understood that the graphene foil has the same shape as the aluminum oxide layer 12.

Thus, according to a first embodiment of the invention, a graphene Hall sensor 10 is provided.

It is understood that in some embodiments, the method for forming the graphene Hall sensor 10 described above may be used to form an array of graphene Hall sensors 10 on a substrate 18. As such, rather than patterning a single Hall sensor using the dielectric layer (aluminum oxide layer 12), the dielectric layer may be patterned to define a plurality of discontinuous portions of the graphene foil, with each discontinuous portion of the graphene foil being used to define one Hall sensor to form. As such, an array structure similar to that of 9 be provided, with a plurality of Hall sensors being formed on a substrate 18. Such an array structure allows multiple Hall sensors to be formed on a single substrate. Such formation methods allow multiple graphene Hall sensors to be formed from the same graphene layer and dielectric layer. Accordingly, the resulting multiple graphene Hall sensors can have improved uniformity and can be formed in an economical manufacturing process.

According to a second embodiment of the invention, a magnetic field measuring system is provided. The system includes a graphene Hall sensor according to the first embodiment and a Hall measurement controller (not shown). The Hall measurement controller is connected to the first and second pairs of electrical contacts. The Hall measurement controller is configured to provide a Hall effect measurement solution using the graphene Hall sensor.

The Hall measurement controller may be connected to the first pair of electrical contacts and the second pair of electrical contacts via the respective portion of each contact not covered by the encapsulation layer 20 to control the graphene Hall effect sensor 10 . The Hall measurement controller may be any suitable controller such as a computer processor.

The Hall measurement controller is configured to bias the graphene Hall effect sensor 10 between the first pair of electrical contacts 14, 15. The Hall measurement controller can bias the graphene Hall sensor 10 by applying a constant current or a constant voltage. The bias voltage (constant current or constant voltage) can be controlled by the controller using a suitable power supply or can be formed as part of the Hall measurement controller.

The Hall measurement controller is also configured to measure an output voltage between the second pair of electrical contacts 16, 17. Of course, in other embodiments, it will be understood that the Hall measurement controller may apply the bias voltage between the second pair of electrical contacts 16, 17 and measure a voltage across the first pair of contacts 14, 15.

The Hall measurement controller and the graphene Hall sensor 10 can be used to make measurements of magnetic fields at a temperature range. In particular, the graphene Hall sensor 10 can be used to measure a magnetic field at a cryogenic temperature (i.e. at a temperature not greater than 120 K).

2 and 3 are graphs comparing the performance of two graphene Hall sensors. The first graphene Hall sensor (a) has a layer carrier density of 3.1 x 10 ¹² cm ^-2 and a sensitivity of 189 V/AT. The second graphene Hall sensor (b) has a layer carrier density of 4.6 × 10 ¹¹ cm ^-2 and a sensitivity of 1281 V/AT.

2 and 3 show graphs of the performance of the first (a) and second (b) graphene Hall sensors in response to an applied magnetic field at a temperature of 3.3 K and a constant current bias of 100 µA.

2 is a diagram showing the Hall voltage generated by the first (a) and second (b) graphene Hall sensors under different applied magnetic fields. 3 shows a graph of the full-scale Hall voltage linearity errors for each of the in 2 shown first and second graphene Hall sensors for magnetic fields that are between -7 T and +7 T. In the 3 Full-scale linearity errors shown are the difference between the data points of 2 and a linear pass line expressed as a percentage of the maximum Hall voltage (i.e. the Hall voltage at 7T for each graphene Hall sensor).

As in 3 As shown, the second (b) graphene Hall sensor has a full-scale linearity error of 22.3% at -7 T to +7 T (i.e. the maximum value of the full-scale linearity error in 3 should be between -7 T and +7 T). If the full scale linearity error is between -1T and +1T (i.e. based on a linear fit between -1T and +1T, not in 3 shown), the first (a) graphene Hall sensor has a full-scale linearity error of 3.17%.

The first (a) graphene Hall sensor has a full-scale linearity error of 0.98% between -1T and +1T. As in 3 shown, the first (a) graphene Hall sensor has a full scale linearity error of 1.3% between -7 T and +7 T.

Thus, it will be understood that by reducing the sensitivity of the device (within the specified limits), the graphene Hall sensor can be configured to provide a linear response over a desired magnetic field range.

Thus, according to embodiments of this invention, a graphene Hall sensor is provided. The graphene Hall sensor is particularly suitable for carrying out magnetic field measurements at cryogenic temperatures. In particular, the layer carrier density of the graphene film of the graphene Hall sensor is selected such that magnetic fields can be measured at cryogenic temperatures without undesirable saturation of the device, and also such that measurements of the magnetic field can be carried out with sufficient resolution.

10a shows a diagram of the Hall resistance of a graphene Hall sensor according to a further embodiment of the invention under an applied magnetic field. The applied magnetic field ranges from 0 T to +30 T. The Hall resistance measurements were carried out at a temperature of 4.2K. The Hall resistance measurements of 10a were obtained using a constant bias current of 1 µA.

The graphene Hall sensor shown in the diagram of 10a is used has a layer support density of 3.0 × 10 ¹² cm ^-2 . Similar to the second graphene Hall sensor (b) in 2 It is understood that the graphene Hall sensor from 3 has a generally linear response for magnetic fields ranging from 0T to +30T. As such, graphene Hall sensors according to embodiments of the invention can be used to perform magnetic field measurements at cryogenic temperatures and magnetic fields with relatively high magnetic field strength while still providing a linear response. For example, the graphene Hall sensor from 2 can be used to carry out magnetic field measurements at cryogenic temperatures, with the magnetic field strength having a magnitude of approximately 30 T, 35 T, 40 T or 45 T.

10b shows a plot of the full-scale linearity error for the graphene Hall sensor in 10a . As in 10b is the full scale linearity error (linear fit) is not greater than 8% over the magnetic field range of 0T to 30T.

11 shows a comparison of the graphene Hall sensor from 10 a with a known nonlinear Hall sensor when measuring a magnetic field at cryogenic temperatures. The non-graphene Hall sensor is based on the Group III-V semiconductor material such as GaAs, InSb or InAs.

As in 11 shown, the non-graphene Hall sensor has a Hall voltage response that increases with increasing magnetic field strength for magnetic fields in the range of approximately 0 T to 15 T. At higher magnetic fields, the Hall voltage decreases again. Therefore, the non-graphene Hall sensor is not suitable for carrying out magnetic field measurements over large magnetic field ranges (e.g. magnetic fields with a size of at least: 16 T, 19 T, 22 T, 25 T, 30 T, 35 T, 40 T etc.).

It is also understood that the non-graphene Hall sensor has a lower sensitivity response compared to the graphene Hall sensor. A lower sensitivity response may be undesirable because the signal-to-noise ratio may be lower. Relatively low sensitivity responses indicate non-graphene Hall sensors cannot operate effectively at cryogenic temperatures.

Thus, it will be seen from the above examples that the graphene Hall sensor according to embodiments of this invention provides a user with the ability to perform particularly accurate magnetic field measurements at cryogenic temperature and also over a relatively large range of magnetic fields.

12 shows a graphical representation of the full-scale linearity error for each of the Hall sensors of 11 over the magnetic field range 0 T to 30 T. For the graphene Hall sensor 10a the maximum linearity error is -8%. In contrast, the maximum linearity errors for the first and second non-graphene Hall sensors are -100% and +100%, respectively. Therefore, it is understood that the graphene Hall sensor of this disclosure provides a significant improvement in response linearity when operated at cryogenic temperatures compared to other non-graphene Hall sensors.

13 shows a diagram of the Hall voltage for the graphene Hall sensor from 10a under a magnetic field of 1.5K. Out of 13 It can be seen that the Hall response at 1.5 K follows the same curve shape as the response at 4 K (also in 13 shown for comparison). As such, the linear response properties of the graphene Hall are maintained even when the measurement temperature is reduced from 4 K to 1.5 K.

4 is a flowchart illustrating the method of the present invention 100. The method 100 includes a number of essential steps (105, 110, 115 and 120) and may further include one of three optional steps (125a, 125b and 125c), which represent three alternatively preferred specific embodiments of the method 100.

The method 100 is used to form an electronic device precursor suitable for a Hall sensor and includes a first step 105 of providing a plasma-etchable layer structure on a plasma-resistant substrate. In the exemplary method 100, the plasma-etchable layer structure consists of a graphene layer provided directly on a sapphire substrate by MOCVD.

Next, another step 110 involves patterning cruciform regions of aluminum oxide by jet evaporation on the exposed top surface of the graphene monolayer to form an array of intermediates. The process is further described with reference to an intermediate, although it is recommended that all intermediates of the array be treated simultaneously. Step 115 involves subjecting the intermediate to an oxygen plasma etch, thereby etching the exposed graphene monolayer and forming an array of cruciform regions of graphene coated with aluminum oxide are covered, with the alumina-coated graphene having a continuous exposed edge surface.

Method 100 further includes a step 120 of forming an ohmic metal contact in direct contact with a portion of the exposed edge surface of the etched graphene layer. Specifically, four metal contacts are formed at the end of each of the “arms” of the cross-sectional shape.

In a first specific embodiment of the method 100, the method 100 further includes a step 125a, performed after step 120, namely forming a coating of alumina by ALD over the sapphire substrate, thereby comprising the alumina-coated graphene, the ohmic contacts and the exposed substrate be provided with a continuous air-resistant coating.

In a second specific embodiment, the method 100 further includes a step 125b, performed after step 120, which includes patterning an alumina coating layer onto the substrate by e-beam evaporation, thereby providing the alumina-coated graphene with a continuous air-resistant coating. The aluminum oxide coating provided by step 125b therefore coats and protects the exposed edge(s) not in contact with the ohmic contact, and the pattern of the coating is the same geometric cross-sectional shape but geometrically larger. For example, the maximum width and/or the maximum height of the mold may be 10% larger or even 20% larger than that of the patterned alumina 110. The patterning step also leaves a portion of each metal contact exposed for connection to an electronic circuit.

In a third specific embodiment, the method 100 further includes a step 125c of forming a coating prior to step 120. Step 125c includes forming a coating to provide the alumina-coated graphene monolayer with a continuous air-stable coating of alumina (i.e., such that that the exposed edge surface is coated). In this embodiment, step 120 further includes a step of selectively laser etching four portions of the coating at the end of each of the "arms" of the underlying cross-sectional shape to expose the corresponding portions of the edge surface of the graphene. As required by method 100, step 120 then includes forming the ohmic metal contacts in direct contact with the exposed edge surface in each of the selectively etched portions.

5 is a cross-sectional view of an electronic device precursor 200. The precursor 200 is obtainable by the method described herein, which includes forming a coating by ALD after forming the ohmic contacts.

The electronic device precursor 200 is formed from a sapphire substrate 205 on which there is a plasma-etchable 2D material layer 210 comprising a graphene layer structure. The 2D material layer 210 has a shape defined by the aluminum oxide layer 215 formed thereon. Accordingly, the 2D material layer and the aluminum oxide share a continuous edge surface, with the graphene layer structure extending to this edge.

The precursor 200 further includes two ohmic contacts 220a and 220b, each of which is in direct contact with the edge of the 2D material layer 210 and therefore also the graphene layer structure. No contact material is on the surface of the 2D material layer 210 because the aluminum oxide and 2D material share a continuous edge surface and are of the same shape. Advantageously, the contact does not result in significant doping of the 2D material, as can be observed when contacts are provided on the flat surface of a 2D material. Further, the edge contact provides improved charge injection relative to surface charge injection, improving overall efficiency (for example, by reducing any electrical losses as heat).

A continuous air-resistant coating of silicon dioxide is formed on the aluminum oxide coating 215, the contacts 220a and 220b, and the substrate 205. The coating 225 provides excellent protection against atmospheric contamination by preventing the penetration of, for example, oxygen gas and water vapor. The precursor 200 further includes wires 230a and 230b connected to the ohmic contacts 220a and 220b. Wires 230a and 230b provide a means of electrical connectivity to the ohmic contacts and therefore protrude from the coating.

The inventors have found that the electronic device precursor 200 provides an electronic device with excellent stability. In particular, the inventors have found that a device 200 formed from the precursor has a degradation rate of less than 0.01%/day (measured in relation to the initial carrier concentration and therefore the sensitivity, the device and the place of manufacture).

For comparison, it was found that in a device formed from a precursor, the coating (e.g., coating 215) is not provided and instead a ceramic lid is used to "seal" the components (as is known in the art and which can also be used in combination with the present invention), the sensitivity of such a device deteriorates at a rate of 0.5%/day. The inventors also found that the lack of a coating or a ceramic lid was significantly greater.

As a further comparison, the inventors have found that for devices formed using an organic PMMA coating that provide greater protection against deterioration over known ceramic lids, such devices have a deterioration rate of between 0.03%/day and 0. Show 1%/day.

The inventors have also found that when metal contacts are deposited on graphene before patterning a dielectric layer, the metal results in heavy doping of the graphene greater than 10 ¹² cm ^-2 and even greater than 10 ¹³ cm ^-2 , thereby causing the Sensitivity is significantly reduced.

6 is a cross-sectional view of an electronic device precursor 300. The precursor 300 is obtainable by the method described herein, which includes forming a coating prior to the step of forming the ohmic contacts.

The electronic device precursor 300 includes a sapphire substrate 305 on which a plasma-etchable 2D material layer 310 is present. In this embodiment, the 2D material layer consists of a bi-layer graphene (ie, a graphene monolayer, with 2 graphene layers). A structured layer of silicon dioxide 315 is formed thereon, which shares a continuous edge surface with the bi-layer graphene 310. Deposited on the surface of the patterned silicon dioxide layer 315 is a continuous air-resistant coating 325. The coating 325 is also deposited on an adjacent portion of the surface of the substrate 305. 6 is a cross-sectional view of the precursor 300, the cross-section of two ohmic contacts 320 halved and deposited on the substrate 305. It is understood that in alternative cross sections the coating 325 is continuous.

The contacts 320 are in direct contact with an edge surface of the bilayer graphene and the silicon dioxide and aluminum oxide coatings thereon. Precursor 300 may be obtained by the method described herein, which includes selectively etching a coating formed prior to forming the ohmic contacts. Accordingly, the contacts extend from the surface of the substrate 305, which are exposed to the surface of the coating 325 during the etching process. In this embodiment, solder balls (or solder balls) 330 are provided on the exposed portion of the ohmic contact such that the precursor 300 can be described as a “flip chip.”

7 is a top view of a precursor of the electronic device 400. Precursor 400 is suitable for a Hall sensor and is formed from a 2D material layer beneath an identically shaped/patterned aluminum oxide layer 415, particularly a cruciform shape, all formed on a silicon substrate 405. The ends of each of the four “arms” of the cruciform layered structure (i.e., the distal portion) of the 2D material and patterned alumina 415405 are in direct contact with each of the four titanium contacts (420a, 420b, 420c, and 420d). A continuous air-resistant aluminum oxide coating 425 is provided over the layered structure and a portion of each of the contacts in a manner to encapsulate the edges of the underlying 2D material layer and leave a portion of each of the titanium contacts exposed. The coating 425 can be provided by electron beam evaporation. In 7 1, the coating 425 is illustrated as semi-transparent to illustrate the presence of the underlying structured aluminum oxide 415. It is understood that the 2D material layer has the same shape as the aluminum oxide layer 415. Precursor 400 is a single component obtainable by dividing a substrate formed from an array of equivalent precursors that share the common substrate. Precursor 400 is advantageous in that cutting does not involve cutting through the coating 425 since the coating does not extend into the so-called "roads" or sections of the substrate between the array of components.

The present inventors have used Raman spectra obtained at various positions of the device precursor to confirm the presence (and quality) or absence of graphene. In particular The method of the present invention facilitates the clean etching of graphene to the edge of the patterned alumina, so that ohmic contacts can then be provided without having to remove the protective alumina layer. Furthermore, the Raman spectra of the graphene show that the quality of the graphene proximal to the edge can be comparable to the quality of the rest of the underlying and protected graphene sections (as at label point 415 for the graphene stack and the structured alumina in 7 ). Additionally, the inventors of the present invention have used Raman spectroscopy to demonstrate the absence of graphene outside the patterned dielectric between the coating and the substrate (as at the point of coating marker 425 in 7 ).

8th is a top view of a precursor of the electronic device 500. Precursor 500 is suitable for a Hall sensor and is formed from a 2D material layer beneath an identically shaped/patterned aluminum oxide layer 515, particularly a cruciform shape, all formed on a silicon substrate. Separate gold contacts 520 are in direct contact with corresponding edge portions of the underlying 2D material layer at four portions of the cross, particularly four distal portions that form the ends of each arm of the cross shape. A continuous airborne coating 525 is formed by silicon dioxide formed by ALD over the entire substrate and layer structure of the 2D material and aluminum oxide 515 (and therefore all edges are not in direct contact with the contacts 520), along with all Contacts 520 itself. In 7 1, the coating 525 is illustrated as semi-transparent to illustrate the presence of the underlying structured aluminum oxide 515.

9 is a perspective view of an electronic device precursor array 600. Array 600 is formed from four electronic device precursors that can be separated by dividing the substrate along streets 635. Each precursor comprises a portion of the substrate (605a, 605b, 605c and 605d) and is formed on each portion of the coating (625a, 625b, 625c and 625d) that encapsulates the layered structures of 2D materials and patterned dielectric layers.

Furthermore, each precursor includes two ohmic contacts (620a and 620a'), portions of which are not encapsulated by the coating (625a).

Examples

1. 1. Graphen wurde nach dem Prozess in WO2017/ 029470 auf einem Saphirsubstrat gezüchtet.
2. 2. Al₂O₃ wurde durch thermisches Verdampfen durch eine Schattenmaske mit Öffnungen in Form eines Kreuzes auf das Graphen eingedampft. Die Dicke des verdampften Al₂O₃ betrug 10 nm.
3. 3. Das Graphen wurde in Bereichen, in denen es freiliegt, als die oberste Schicht durch Plasmaätzen entfernt. Die dafür verwendeten Einstellungen waren 40 % (auf einer 100-W-Vorrichtung) mit einer Sauerstoffdurchflussrate von 6 sccm für 30 Sekunden.
4. 4. Unter Verwendung einer anderen Schattenmaske wurden Ti/Au-stabförmige Kontakte auf die Enden der Arme des Kreuzes eingedampft. Diese wurden durch Verdampfen von 10 nm Ti und dann 120 nm Au hergestellt. Sie wurden in Bezug auf die Kreuzarme so positioniert, dass sie an den Enden der Kreuzarme am Rand des Graphens anliegen und seitlich weg von den Kreuzarmen verlaufen.
5. 5. Eine zweite Schicht von verdampftem AI₂O₃ wurde über die erste Schicht in einer Kreuzform abgeschieden, die größer als die erste ist, sodass sie den ersten Kreuz- und linken Teil jedes Stabkontakts freilegt.
6. 6. Dies ergab Vorrichtungen auf Waferbasis, die dann über Standard-BEOL-Verarbeitung verarbeitet wurden.

According to a first example:

1. 1. Graphene was grown on a sapphire substrate according to the process in WO2017/029470.
2. 2. Al ₂ O ₃ was evaporated onto the graphene by thermal evaporation through a shadow mask with openings in the shape of a cross. The thickness of the evaporated Al ₂ O ₃ was 10 nm.
3. 3. The graphene was removed as the top layer by plasma etching in areas where it was exposed. The settings used for this were 40% (on a 100 W device) with an oxygen flow rate of 6 sccm for 30 seconds.
4. 4. Using another shadow mask, Ti/Au rod-shaped contacts were evaporated onto the ends of the arms of the cross. These were prepared by evaporating 10 nm Ti and then 120 nm Au. They were positioned in relation to the cross arms so that they rest at the ends of the cross arms on the edge of the graph and extend laterally away from the cross arms.
5. 5. A second layer of vaporized Al ₂ O ₃ was deposited over the first layer in a cross shape larger than the first, exposing the first cross and left part of each rod contact.
6. 6. This resulted in wafer-based devices which were then processed via standard BEOL processing.

1. 1. Graphen wurde nach dem Prozess in WO2017/ 029470 auf einem Saphirsubstrat gezüchtet.
2. 2. AI₂O₃ wurde durch thermisches Verdampfen durch eine Schattenmaske mit Öffnungen in Form eines Kreuzes auf das Graphen eingedampft. Die Dicke des verdampften AI₂O₃ betrug 10 nm.
3. 3. Das Graphen wurde in Bereichen, in denen es freiliegt, als die oberste Schicht durch Plasmaätzen entfernt. Die dafür verwendeten Einstellungen waren 40 % (auf einer 100-W-Vorrichtung) mit einer Sauerstoffdurchflussrate von 6 sccm für 30 Sekunden.
4. 4. Unter Verwendung einer anderen Schattenmaske wurden Ti/Au-stabförmige Kontakte auf die Enden der Arme des Kreuzes eingedampft. Diese wurden durch Verdampfen von 10 nm Ti und dann 120 nm Au hergestellt. Sie wurden in Bezug auf die Kreuzarme so positioniert, dass sie an den Enden der Kreuzarme am Rand des Graphens anliegen und seitlich weg von den Kreuzarmen verlaufen.
5. 5. Eine zweite Schicht aus AI₂O₃ wurde über den gesamten Wafer unter Verwendung von ALD abgeschieden. Diese Schicht war 65 nm dick.
6. 6. Dies ergab Vorrichtungen auf Waferbasis, die dann über Standard-BEOL-Verarbeitung verarbeitet wurden.

According to a second example:

1. 1. Graphene was grown on a sapphire substrate according to the process in WO2017/029470.
2. 2. AI ₂ O ₃ was evaporated onto the graphene by thermal evaporation through a shadow mask with openings in the shape of a cross. The thickness of the evaporated Al ₂ O ₃ was 10 nm.
3. 3. The graphene was removed as the top layer by plasma etching in areas where it was exposed. The settings used for this were 40% (on a 100 W device) with an oxygen flow rate of 6 sccm for 30 seconds.
4. 4. Using another shadow mask, Ti/Au rod-shaped contacts were evaporated onto the ends of the arms of the cross. These were prepared by evaporating 10 nm Ti and then 120 nm Au. They were in Reference to the cross arms positioned so that they rest at the ends of the cross arms on the edge of the graph and extend laterally away from the cross arms.
5. 5. A second layer of Al ₂ O ₃ was deposited over the entire wafer using ALD. This layer was 65 nm thick.
6. 6. This resulted in wafer-based devices which were then processed via standard BEOL processing.

As used herein, the singular form of "a", "an" and "the", "the", "the" includes references to the plural unless the context clearly requires otherwise. The use of the term “comprehensive” should be construed to include such features but not to exclude other features, and should also include the option that the features are necessarily limited to those described. In other words, the term also excludes the restrictions “substantially consisting of” (meaning that certain additional components may be present provided they do not significantly impair the essential property of the feature described) and “consisting of” (meaning that none further feature may be included so that if the components were expressed as percentages of their proportions, they would add up to 100%, taking into account unavoidable impurities), unless the context clearly dictates otherwise.

It is to be understood that the terms "first", "second", etc. may be used throughout this document to describe various elements, layers and/or portions, which elements, layers and /or shares should not be restricted by these terms. These terms are used only to distinguish one element, layer or portion from another or a further element, layer or portion. It is understood that the term "on" is intended to mean "directly on" such that there are no intervening layers between a material that can be described as being "on" another material. Spatially relative terms such as "below", "below", "lower", "above", "above" and the like can be used here for easier description of the relationship of one element or feature to (an) other element (s) or (an) other feature(s). It is understood that the spatial terms are intended to include various orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the building element in the figures is flipped over, elements described as being “below” or “below” other elements or features would be oriented “above” the other elements or features. Thus, the exemplary term “bottom” can include both an orientation from above and from below. The component can be oriented differently and the spatially relative descriptors used here can be interpreted accordingly.

The foregoing detailed description is for purposes of explanation and illustration and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art and remain within the scope of the appended claims and their equivalents.

1. 1. Verfahren zum Herstellen eines elektronischen Vorrichtungsvorläufers, das Verfahren umfassend:
   1. (i) Bereitstellen einer plasmaätzbaren Schichtstruktur auf einem plasmabeständigen Substrat, wobei die Schichtstruktur eine freiliegende obere Oberfläche aufweist;
   2. (ii) Strukturieren eines plasmabeständigen Dielektrikums auf der freiliegenden oberen Oberfläche, um ein Zwischenprodukt mit mindestens einem bedeckten Bereich und mindestens einem unbedeckten Bereich der Schichtstruktur zu bilden,
   3. (iii) Unterziehen des Zwischenprodukts einer Plasmaätzung, wobei der mindestens eine unbedeckte Bereich der Schichtstruktur weggeätzt wird, um mindestens einen bedeckten Bereich der Schichtstruktur mit einer freiliegenden Randoberfläche zu bilden;
   4. (iv) Bilden eines ohmschen Kontakts in direktem Kontakt mit einem Abschnitt der freiliegenden Randoberfläche;
   wobei die plasmaätzbare Schichtstruktur eine oder mehrere Graphenschichten umfasst, die sich über die bedeckten Regionen der Schichtstruktur zu der freiliegenden Randoberfläche erstrecken
2. 2. Verfahren nach Klausel 1, wobei das plasmabeständige Substrat Saphir, Silizium, Siliziumdioxid, Siliziumnitrid, Siliciumcarbid, Germanium oder ein 111-V-Halbleiter ist.
3. 3. Verfahren nach Klausel 1 oder Klausel 2, wobei das plasmabeständige Dielektrikum ein anorganisches Oxid, Nitrid, Carbid, Fluorid oder Sulfid, vorzugsweise Aluminiumoxid oder Siliziumdioxid, ist.
4. 4. Verfahren nach einer der vorstehenden Klauseln, wobei das Plasmaätzen ein Sauerstoff-Plasmaätzen umfasst.
5. 5. Verfahren nach einer der vorstehenden Klauseln, wobei die plasmaätzbare Schichtstruktur aus einer oder mehreren 2D-Materialschichten besteht.
6. 6. Verfahren nach Klausel 5, wobei die plasmaätzbare Schichtstruktur aus einer oder mehreren Graphenschichten und optional einer oder mehreren Schichten aus Silicen, Germanen, h-BN, Borophen und/oder einem TMDC besteht.
7. 7. Verfahren nach einer der vorstehenden Klauseln, wobei der ohmsche Kontakt ein Metallkontakt, vorzugsweise ein Goldkontakt, ist.
8. 8. Verfahren nach einer der vorstehenden Klauseln, wobei Schritt (ii) das Bilden umfasst von:
   1. (i) einer oder mehreren rechteckigen Regionen des plasmabeständigen Dielektrikums, und wobei der Vorläufer der elektronischen Vorrichtung zum Bilden eines Transistors dient; oder
   2. (ii) einer oder mehreren kreuzförmigen Regionen des plasmabeständigen Dielektrikums, und wobei der Vorläufer der elektronischen Vorrichtung zum Bilden eines Hall-Sensors dient.
9. 9. Verfahren nach einer der vorstehenden Klauseln, wobei Schritt (ii) das Strukturieren eines plasmabeständigen Dielektrikums durch e-Strahlverdampfung, vorzugsweise unter Verwendung einer Maske, umfasst.
10. 10. Verfahren nach einer der vorstehenden Klauseln, wobei das Verfahren das Bilden eines Arrays von bedeckten Regionen umfasst, die jeweils einem Vorläufer einer elektronischen Vorrichtung entsprechen.
11. 11. Verfahren nach Klausel 9, wobei das Verfahren ferner das (vi) Zerteilen des Substrats umfasst, um elektronische Vorrichtungsvorläufer des Arrays zu trennen.
12. 12. Verfahren nach einer der vorstehenden Klauseln, wobei das Verfahren entweder vor oder nach Schritt (iv) ferner (v) das Bilden einer Beschichtung umfasst, um den bedeckten Bereich der Schichtstruktur mit einer kontinuierlichen luftbeständigen Beschichtung bereitzustellen.
13. 13. Verfahren nach Klausel 12, wobei die Beschichtung ein anorganisches Oxid, Nitrid, Carbid, Fluorid oder Sulfid, vorzugsweise Aluminiumoxid oder Siliziumdioxid, ist.
14. 14. Verfahren nach Klausel 12 oder Klausel 13, wobei:
    • Schritt (v) nach Schritt (iv) durchgeführt wird und der ohmsche Kontakt auf dem plasmabeständigen Substrat gebildet wird; und
    • wobei die Beschichtung durch ALD über dem plasmabeständigen Substrat gebildet wird, um den mindestens einen bedeckten Bereich der Schichtstruktur, den ohmschen Kontakt und die verbleibende freiliegende Randoberfläche mit einer durchgehenden luftbeständigen Beschichtung bereitzustellen.
15. 15. Verfahren nach Klausel 14, wobei das Verfahren ferner das Drahtbonden des ohmschen Kontakts des Vorrichtungsvorläufers durch die Beschichtung umfasst.
16. 16. Verfahren nach Klausel 12 oder Klausel 13, wobei:
    • Schritt (v) nach Schritt (iv) durchgeführt wird und der ohmsche Kontakt auf dem plasmabeständigen Substrat gebildet wird; und
    • wobei die Beschichtung durch Strukturieren einer Beschichtung auf dem plasmabeständigen Substrat gebildet wird, um den mindestens einen bedeckten Bereich der Schichtstruktur und die verbleibende freiliegende Randoberfläche mit einer durchgehenden luftbeständigen Beschichtung bereitzustellen.
17. 17. Verfahren nach Klausel 16, wobei die Beschichtung durch e-Strahlverdampfung gebildet wird.
18. 18. Verfahren nach Klausel 12 oder Klausel 13, wobei:
    • Schritt (v) vor Schritt (iv) durchgeführt wird und das selektive Ätzen eines oder mehrerer Abschnitte der Beschichtung, um entsprechende Abschnitte der Randoberfläche freizulegen, umfasst, und Schritt (iv) das Bilden eines ohmschen Kontakts in direktem Kontakt mit jedem freiliegenden Abschnitt der Randoberfläche umfasst.
19. 19. Verfahren nach Klausel 18, wobei das selektive Ätzen durch Laserätzen oder reaktives Ionenätzen durchgeführt wird.
20. 20. Verfahren nach einer der Klauseln 16 bis 19, wobei das Verfahren ferner das Abscheiden einer Lötkugel auf dem ohmschen Kontakt oder dem Drahtbonden des ohmschen Kontakts umfasst.
21. 21. Elektronischer Vorrichtungsvorläufer, umfassend:
    • ein Substrat mit einer Schichtstruktur darauf, wobei die Schichtstruktur umfasst:
      • eine untere Schicht auf einer ersten Region des Substrats, wobei die untere Schicht eine oder mehrere Graphenschichten umfasst, die sich über die untere Schicht erstrecken, und
      • eine obere Schicht auf der unteren Schicht, die aus einem dielektrischen Material gebildet ist,
      • wobei die untere und obere Schicht gemeinsam eine durchgehende Außenrandoberfläche nutzen,
    • einen ohmschen Kontakt, der auf einer weiteren Region des Substrats bereitgestellt ist und in direktem Kontakt mit der einen oder den mehreren Graphenschichten über die durchgehende Außenrandoberfläche steht, und
    • eine durchgehende luftbeständige Beschichtung auf dem Substrat, die Schichtstruktur und mindestens einen ohmschen Kontakt.
22. 22. Elektronischer Vorrichtungsvorläufer, umfassend:
    • ein Substrat mit einer Schichtstruktur darauf, wobei die Schichtstruktur umfasst:
      • eine untere Schicht auf einer ersten Region des Substrats, wobei die untere Schicht eine oder mehrere Graphenschichten umfasst, die sich über die untere Schicht erstrecken, und
      • eine obere Schicht auf der unteren Schicht, die aus einem dielektrischen Material gebildet ist,
      • wobei die untere und obere Schicht eine gemeinsam eine durchgehende Außenrandoberfläche nutzen,
    • einen ohmschen Kontakt, der auf einer weiteren Region des Substrats bereitgestellt ist und in direktem Kontakt mit der einen oder den mehreren Graphenschichten über die durchgehende Außenrandoberfläche steht, und
    • eine durchgehende luftbeständige Beschichtung, die die Schichtstruktur umschließt.
23. 23. Elektronischer Vorrichtungsvorläufer, umfassend:
    • ein Substrat mit einer Schichtstruktur darauf, wobei die Schichtstruktur umfasst:
      • eine untere Schicht auf einer ersten Region des Substrats, wobei die untere Schicht eine oder mehrere Graphenschichten umfasst, die sich über die untere Schicht erstrecken, und
      • eine obere Schicht auf der unteren Schicht, die aus einem dielektrischen Material gebildet ist,
      • wobei die untere und obere Schicht gemeinsam eine durchgehende
      • Außenrandoberfläche nutzen,
    • einen ohmschen Kontakt, der in direktem Kontakt mit der einen oder den mehreren Graphenschichten über die durchgehende Außenrandoberfläche steht, und
    • eine durchgehende luftbeständige Beschichtung, die die Schichtstruktur umschließt.
24. 24. Vorläufer der elektronischen Vorrichtung gemäß Klausel 21, erhältlich nach dem Verfahren zur Klausel 14 oder nach Klausel 22, erhältlich nach dem Verfahren zur Klausel 16, oder nach Klausel 23, erhältlich nach dem Verfahren zur Klausel 16 oder Klausel 18.

The present invention can also be extended to the following numbered clauses:

1. 1. A method for producing an electronic device precursor, the method comprising:
   1. (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed top surface;
   2. (ii) patterning a plasma-resistant dielectric on the exposed top surface to form an intermediate product having at least one covered area and at least one uncovered area of the layered structure,
   3. (iii) subjecting the intermediate product to a plasma etch, wherein the at least one uncovered region of the layered structure is etched away to form at least a covered region of the layered structure with an exposed edge surface;
   4. (iv) forming an ohmic contact in direct contact with a portion of the exposed edge surface;
   wherein the plasma-etchable layered structure comprises one or more graphene layers extending beyond the covered regions of the layered structure to the exposed edge surface
2. 2. The method according to clause 1, wherein the plasma-resistant substrate is sapphire, silicon, silicon dioxide, silicon nitride, silicon carbide, germanium or a 111 V semiconductor.
3. 3. Method according to clause 1 or clause 2, wherein the plasma-resistant dielectric is a inorganic oxide, nitride, carbide, fluoride or sulfide, preferably aluminum oxide or silicon dioxide.
4. 4. A method according to any of the preceding clauses, wherein the plasma etching comprises oxygen plasma etching.
5. 5. Method according to one of the above clauses, wherein the plasma-etchable layer structure consists of one or more 2D material layers.
6. 6. Method according to clause 5, wherein the plasma-etchable layer structure consists of one or more graphene layers and optionally one or more layers of silicene, germanene, h-BN, borophene and / or a TMDC.
7. 7. Method according to one of the above clauses, wherein the ohmic contact is a metal contact, preferably a gold contact.
8. 8. A method according to any of the preceding clauses, wherein step (ii) comprises forming:
   1. (i) one or more rectangular regions of the plasma resistant dielectric, and wherein the precursor of the electronic device serves to form a transistor; or
   2. (ii) one or more cross-shaped regions of the plasma-resistant dielectric, and wherein the precursor of the electronic device serves to form a Hall sensor.
9. 9. Method according to one of the preceding clauses, wherein step (ii) comprises structuring a plasma-resistant dielectric by e-beam evaporation, preferably using a mask.
10. 10. A method according to any of the preceding clauses, wherein the method comprises forming an array of covered regions, each corresponding to a precursor of an electronic device.
11. 11. The method of clause 9, the method further comprising (vi) dividing the substrate to separate electronic device precursors of the array.
12. 12. A method according to any of the preceding clauses, wherein either before or after step (iv), the method further comprises (v) forming a coating to provide the covered area of the layered structure with a continuous air-resistant coating.
13. 13. A method according to clause 12, wherein the coating is an inorganic oxide, nitride, carbide, fluoride or sulfide, preferably aluminum oxide or silicon dioxide.
14. 14. Procedure under clause 12 or clause 13, where:
    • step (v) is carried out after step (iv) and the ohmic contact is formed on the plasma-resistant substrate; and
    • wherein the coating is formed by ALD over the plasma resistant substrate to provide the at least one covered area of the layered structure, the ohmic contact and the remaining exposed edge surface with a continuous air resistant coating.
15. 15. The method of clause 14, the method further comprising wire bonding the ohmic contact of the device precursor through the coating.
16. 16. Procedure under clause 12 or clause 13, where:
    • step (v) is carried out after step (iv) and the ohmic contact is formed on the plasma-resistant substrate; and
    • wherein the coating is formed by patterning a coating on the plasma resistant substrate to provide the at least one covered region of the layered structure and the remaining exposed edge surface with a continuous air resistant coating.
17. 17. Process according to clause 16, wherein the coating is formed by e-beam evaporation.
18. 18. Procedure under clause 12 or clause 13, where:
    • Step (v) is performed before step (iv) and includes selectively etching one or more portions of the coating to expose corresponding portions of the edge surface, and step (iv) forming an ohmic contact in direct contact with each exposed portion of the edge surface includes.
19. 19. The method referred to in clause 18, wherein the selective etching is carried out by laser etching or reactive ion etching.
20. 20. The method of any of clauses 16 to 19, wherein the method further comprises depositing a solder ball on the ohmic contact or wire bonding the ohmic contact.
21. 21. Electronic device precursor comprising:
    • a substrate having a layer structure thereon, the layer structure comprising:
      • a bottom layer on a first region of the substrate, the bottom layer comprising one or more graphene layers extending over the bottom layer, and
      • an upper layer on the lower layer formed from a dielectric material,
      • whereby the lower and upper layers share a continuous outer edge surface,
    • an ohmic contact provided on another region of the substrate and in direct contact with the one or more graphene layers via the continuous outer edge surface, and
    • a continuous air-resistant coating on the substrate, the layer structure and at least one ohmic contact.
22. 22. Electronic device precursor comprising:
    • a substrate having a layer structure thereon, the layer structure comprising:
      • a bottom layer on a first region of the substrate, the bottom layer comprising one or more graphene layers extending over the bottom layer, and
      • an upper layer on the lower layer formed from a dielectric material,
      • wherein the lower and upper layers share a continuous outer edge surface,
    • an ohmic contact provided on another region of the substrate and in direct contact with the one or more graphene layers via the continuous outer edge surface, and
    • a continuous air-resistant coating that encloses the layered structure.
23. 23. Electronic device precursor comprising:
    • a substrate having a layer structure thereon, the layer structure comprising:
      • a bottom layer on a first region of the substrate, the bottom layer comprising one or more graphene layers extending over the bottom layer, and
      • an upper layer on the lower layer formed from a dielectric material,
      • whereby the lower and upper layers together form a continuous layer
      • Use outer edge surface,
    • an ohmic contact in direct contact with the one or more graphene layers via the continuous outer edge surface, and
    • a continuous air-resistant coating that encloses the layered structure.
24. 24. Precursor to the electronic device referred to in clause 21, obtainable under the procedure under clause 14, or under clause 22, obtainable under the procedure under clause 16, or under clause 23, obtainable under the procedure under clause 16 or clause 18.

QUOTES INCLUDED IN THE DESCRIPTION

This list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• GB 2585842 A [0005]
• GB 2570124 A [0011]
• WO 2017/029470 [0056, 0057]
• WO 2017/029470 A [0119, 0121]

Claims (20)

A graphene Hall sensor for operation at cryogenic temperatures, comprising: a substrate; a graphene sheet provided on the substrate; a dielectric layer provided on the graphene sheet, the graphene sheet and the dielectric layer sharing a continuous outer edge surface; a first pair of electrical contacts in electrical contact with the graphene sheet and spaced apart along a first direction; and a second pair of electrical contacts in electrical contact with the graphene sheet and spaced apart along a second direction, the first direction being perpendicular to the second direction, a path along the first direction between the first pair of electrical contacts, a path along the second direction between the second pair of electrical contacts, and the graphene film has a layer carrier density in the range of 2 × 10 ¹¹ cm ^-2 to 1 × 10 ¹³ cm ^-2 . Graphene Hall sensor Claim 1 , wherein the first pair of electrical contacts is provided on the substrate adjacent the graphene sheet such that the first pair of electrical contacts are in direct contact with the graphene sheet via the continuous outer edge surface; and the second pair of electrical contacts is provided on the substrate adjacent the graphene sheet, such that the second pair of electrical contacts are in direct contact with the graphene sheet via the continuous outer edge surface. Graphene Hall sensor Claim 1 or 2 , further comprising: a continuous air-resistant coating covering the substrate, the dielectric layer and the graphene film, and the first and second pairs of electrical contacts. Graphene Hall sensor Claim 3 , wherein the continuous air-resistant coating is an inorganic oxide, nitride, carbide, fluoride or sulfide, preferably aluminum oxide or silicon dioxide. Graphene Hall sensor according to one of the preceding claims, wherein the substrate comprises sapphire, silicon, silicon dioxide, silicon nitride, silicon carbide, germanium, or a Group III-V semiconductor. Graphene Hall sensor according to one of the preceding claims, wherein the dielectric layer comprises an inorganic oxide, nitride, carbide, fluoride or sulfide, preferably aluminum oxide or silicon dioxide. Graphene Hall sensor according to one of the preceding claims, wherein the graphene film has a substrate density of at least 1.25 × 10 ¹² cm ^-2 . Graphene Hall sensor according to one of the preceding claims, wherein the graphene film has a substrate density of at least 3 × 10 ¹² cm ^-2 . Graphene Hall sensor according to one of the preceding claims, wherein the dielectric layer has a thickness in a direction perpendicular to the graphene sheet of 10 nm. A graphene Hall sensor array for operation at cryogenic temperatures, comprising: a substrate; a graphene sheet provided on the substrate, and the graphene sheet having a plurality of discontinuous graphene sections, each discontinuous graphene section defining a graphene Hall sensor of the graphene Hall sensor array; a dielectric layer provided on the graphene sheet, the dielectric layer having a plurality of discontinuous dielectric sections provided on the discontinuous graphene sections, each discontinuous graphene section of the graphene film and a corresponding discontinuous dielectric section sharing a continuous outer edge; each graphene Hall sensor of the graphene Hall sensor array further comprises: a first pair of electrical contacts in electrical contact with the discontinuous graphene portion and spaced along a first direction; and a second pair of electrical contacts in electrical contact with the discontinuous graphene portion and spaced apart along a second direction, the first direction being perpendicular to the second direction, a path along the first direction between the first pair of electrical contacts and a path along the second direction between crosses the second pair of electrical contacts, and the graphene film has a layer carrier density in the range of 2 x 10 ¹¹ cm ^-2 to 1 x 10 ¹³ cm ^-2 . Magnetic field measurement system, comprising: a graphene Hall sensor according to one of Claims 1 until 9 ; and a Hall measurement controller connected to the first and the second pair of electrical contacts, wherein the Hall measurement controller is configured to perform a Hall effect measurement using the graphene Hall sensor. A method for determining a magnetic field at cryogenic temperatures, comprising: exposing a graphene Hall sensor according to one of the Claims 1 until 9 with a cryogenic environment with a temperature not exceeding about 120 K; and performing a Hall effect measurement using the graphene Hall sensor. A method of manufacturing a graphene Hall sensor, comprising: forming a graphene layer on a substrate; patterning a plasma-resistant dielectric layer on a portion of the graphene sheet to form an intermediate product having at least a covered area and at least an uncovered area of the graphene sheet; subjecting the intermediate product to a plasma etch, thereby etching away the at least one uncovered region of the graphene sheet to form an etched layer structure having one or more exposed edge surfaces; forming a first pair of electrical contacts in electrical contact with the graphene sheet and spaced apart along a first direction; and forming a second pair of electrical contacts in electrical contact with the graphene sheet and spaced apart along a second direction, the first direction being perpendicular to the second direction and a path along the first direction between the first pair of electrical contacts a path along the second direction between crosses the second pair of electrical contacts, and the graphene film has a sheet support density in the range of 2 × 10 ¹¹ cm ^-2 to 1 × 10 ¹³ cm ^-2 . Procedure according to Claim 13 , wherein the first pair of electrical contacts are formed on the substrate adjacent the graphene sheet such that the first pair of electrical contacts are in direct contact with the graphene sheet via one or more of the exposed edge surfaces; and the second pair of electrical contacts is provided on the substrate adjacent the graphene sheet such that the second pair of electrical contacts are in direct contact with the graphene sheet via one or more of the outer edge surfaces. Procedure according to Claim 13 or 14 , the method further comprising: forming a continuous air-resistant coating over the etched layer structure and the first and second pairs of electrical contacts. Procedure according to one of the Claims 13 until 15 , wherein a plasma-resistant dielectric layer comprises patterning a plasma-resistant dielectric by thermal evaporation, preferably using a mask. Procedure according to Claim 16 , wherein the plasma-resistant dielectric layer is patterned using e-beam evaporation. Using a graphene Hall sensor according to one of the Claims 1 until 9 , to measure a magnetic field with a magnitude of at least 1 T at a temperature not exceeding 120 K. Using a graphene Hall sensor according to one of the Claims 1 until 9 , to measure a magnetic field with a magnitude of at least: 3T, 5T, 7T, 9T, 11T, 13T, 16T, 19T or 22T at a temperature not exceeding 120K. Using a graphene Hall sensor according to one of the Claims 1 until 9 , to measure a magnetic field with a magnitude of at least 30 T or at least 40 T at a temperature not exceeding 120 K.

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