DE112016003849T5 - Distributed modulation system and method for power electronic applications - Google Patents

Abstract

End-point (30) for a distributed modulation system for power electronic applications, comprising: at least one transceiver for receiving control data from a control master (10) via at least one communication channel (201) embedding a reference clock signal (RefCLK) and having at least one set of modulation parameters, at least one clock recovery module arranged to recover a recovered clock signal (rCLK) from the data transmission channel, a modulator (302) arranged to generate modulation signals (401) based on the set of modulation parameters and on at least one periodic carrier using the recovered one Clock signal (rCLK) is generated, a monitoring module, which is configured for mastering and adjusting an initial phase difference between the / n periodic carrier (s) and an interrupt signal based on the reference clock signal. The present invention also relates to distributed modulation system for power electronic applications, comprising this end node and a relative method.

Description

Field of the invention

The present invention relates to an end node for a distributed modulation system for power electronic applications, such a system and a method for such a system.

Description of the Prior Art

Power converters or power conversion systems are often used to convert AC or DC signals into AC or DC signals of, for example, different amplitude or frequency.

Modern power converters comprise two parts. On the one hand, a power stage acts as a controllable valve (s) to shape the power signal (s) and to regulate the corresponding power flow (s). The power stage typically includes power semiconductor switches such as Insulated Gate Bipolar Transistor (IGBT), Insulated Gate Commutated Thyristor (IGCT), GTO (Gate Turn-Off Thyristor), thyristors, etc. On the other hand, a control stage generates control signals for these switches to provide the output signal (s). e) to shape as desired.

Modern converters generally use modulation techniques, such as pulse width modulation (PWM), to combine good harmonic performance and good conversion efficiency.

The modulation is achieved by means of a modulator. In the context of the present invention, a modulator is a functional block that generates one or more modulation signals based on one or more carriers and a set of modulation parameters. In general, the modulation signal is a digital signal and the carrier is a periodic analog signal which is approximated by the value of a digital counter based on a clock signal. Hereinafter, the term "carrier (or signal) generated based on a clock signal" indicates that the carrier (or signal) is generated using a digital counter based on this clock signal.

A modulator may perform various modulations, such as pulse width modulation, pulse frequency modulation, space vector modulation, or perhaps use optimized pulse patterns to convert its inputs to its outputs.

In the case of a pulse width modulator, the carrier is a periodic waveform, e.g. a sawtooth or triangular waveform generated based on a clock signal, and the main modulation parameter is a threshold. If the value of the carrier is higher than the threshold, the modulation signal is in a high state, otherwise it is in a low state.

The modulation signals are generally used to control one or more power semiconductor switches of the power stage, e.g. for determining the switching times of these switches.

Modular power conversion systems that include a multiple power electronic device (PEBB) circuit are well known. For example, systems comprising between 1 and 2,000 blocks or more are known. The use of a modular design makes it easy to scale the ratings and performance of power converters by connecting or stacking different PEBBs in parallel. In addition, modular inverters are simpler and less expensive to design and maintain, and are also more reliable due to possible redundancies.

Examples of modular power converters are in US 5642275A . DE10103031A1 or US20100156188A1 specified.

For a non-modular energy conversion system, the entire system can be assimilated to a unique PEBB.

A known disadvantage of modular power conversion systems is the difficult operation and coordination of the multiple PEBBs where the modulation signals must be synchronized by appropriate techniques. This is especially challenging if the modulators are inside the PEBBs and if they are physically separated or geographically distributed, as in large plants.

• - erste Problemart: Synchronisieren des Betriebs der Modulatoren; dies impliziert, dass es möglich sein muss, die relativen Phasen und Frequenzen der entsprechenden Modulationssignale einzustellen und zu mastern/beherrschen;
• - zweite Problemart: Bewahrung der zeitlichen Integrität der Modulationssignale zwischen dem(n) Modulator(en) und den Leistungsschaltern.

In practice, the synchronization of a plurality of modulation signals generated by a plurality of modulators located in different PEBBs involves two types of problems:

• first problem type: synchronizing the operation of the modulators; this implies that it must be possible to set and master the relative phases and frequencies of the corresponding modulation signals;
• second type of problem: preserving the temporal integrity of the modulation signals between the modulator (s) and the circuit breakers.

WO14207436A1 and WO13102779 Examples of post-modulation synchronization systems related to the second type of questions mentioned above.

The present invention is concerned with the first type of problem.

Several concerns relate to the synchronization of the modulation signals that meet different timing accuracy requirements. In the context of the present invention, the term "temporal accuracy" indicates the accuracy with which the phase difference between two signals can be controlled, e.g. mastered / mastered and adapted. This "temporal accuracy" can also be referred to as "temporal jitter" or simply "jitter".

• - Typ A: Wenn PEBBs oder Gruppen von PEBBs als getrennte Wandler mit niedrigen Pulszahlen betrieben werden, beispielsweise als parallel geschaltete Sechs- oder Zwölfpulswandler, steht die notwendige Genauigkeit der Synchronisation im Zusammenhang mit einem kleinen Bruchteil des AC-Leistungssignals. Beispielsweise, unter Annahme eines 50 Hz AC-Signals (Wechselsignals), führt dies typischerweise zu Anforderungen in der Grössenordnung von 10µs bis 1ms.
• - Typ B: Wenn PEBBs oder Gruppen von PEBBS einen Wandler mit höheren Pulszahlen bilden, wie beispielsweise PWM-betriebene Wandler, bezieht sich die notwendige Genauigkeit der Synchronisation zwischen den Wandlern auf einen kleinen Bruchteil der Schaltfrequenz. Beispielsweise, unter Annahme einer scheinbaren Schaltfrequenz von 2 kHz ergeben sich typischerweise Anforderungen in der Grössenordnung von 500ns bis 10µs. Diese Bedenken ergeben sich ebenfalls zwischen den Schaltzellen, welche die Multilevel-Wandler bilden.
• - Typ C: Wenn Leistungshalbleiterschalter direkt in Reihe oder parallel betrieben werden müssen, bezieht sich die erforderliche Genauigkeit der Synchronisation auf einen kleinen Bruchteil der Schaltübergangszeit (vom AUS- in den EIN-Zustand oder umgekehrt). Zum Beispiel ist eine Genauigkeit von 50ns oder mehr notwendig, um parallel oder in Reihe geschaltete Schalter ohne viele zusätzliche Massnahmen zu betreiben.

In particular, in a distributed modulation system, three different types of timing accuracy requirements can be distinguished:

• Type A: When PEBBs or groups of PEBBs are operated as separate transducers with low pulse counts, for example as six- or twelve-pulse converters connected in parallel, the necessary accuracy of the synchronization is associated with a small fraction of the AC power signal. For example, assuming a 50 Hz AC (alternating) signal, this typically results in requirements of the order of 10μs to 1ms.
• Type B: When PEBBs or groups of PEBBS form a higher pulse rate converter, such as PWM-powered converters, the necessary accuracy of synchronization between the converters refers to a small fraction of the switching frequency. For example, assuming an apparent switching frequency of 2 kHz, typically on the order of 500ns to 10μs will result. These concerns also arise between the switch cells that make up the multilevel converters.
• - Type C: When power semiconductor switches need to be operated directly in series or in parallel, the required accuracy of synchronization refers to a small fraction of the switching transition time (from OFF to ON or vice versa). For example, an accuracy of 50ns or more is necessary to operate parallel or series connected switches without many additional measures.

The "timing accuracy" required in a distributed power application modulation system must therefore be better than 1 ms and often on the order of tens to hundreds of nanoseconds.

The most obvious approach for synchronizing the operation of multiple modulators is to distribute to each of them a common clock signal using a dedicated electrical or optical line. In any case, this signal corresponds to an additional line which must be added to the existing communication channel between the modulators.

This approach is used for example in DE102013106006 used where the frequency of the distributed clock signal is similar to that of the AC signal, whereby a synchronization of the type A described above is achieved.

Alternatively, a clock signal having a frequency similar to that of the switching frequency may be passed to the PEBB controllers. A synchronization of the above type B can thus be achieved.

The number of signals that must be generated by the control stage increases with the number of PEBBs. Therefore, if additional synchronization signals must be present in large systems, this requires a prohibitive number of lines to the PEBBs.

Instead of distributing a common clock signal, the synchronization can be achieved by means of a communication channel in conjunction with a suitable synchronization protocol. PTP over Ethernet is an example of such a synchronization protocol or communication channel.

In large systems with a high number of PEBBs, the synchronization protocol requires a significant amount of data to be transmitted continuously, reducing the available bandwidth for more useful information exchange (payload).

Alternatively, more specialized techniques can be set up. For example, describes EP2800262 a control stage for directing N power converters. However, the invention is limited to a synchronization of the above type B and the generation of phase shifted carriers shifted by 360 / N degrees.

Thus, in all the above cases, the slave circuits (ie, the PEBBs and their modulators) have their own individual timing resources (oscillators, crystals, etc.) and are therefore clocked on separate time bases. That's why they belong inherent to separate clock domains and form a set of plesiochronous systems.

In the context of the present invention, the phrase "the circuits belong to separate clock domains" indicates that these circuits have no common time base. As a consequence, their clocks diverge because their frequencies are not exactly the same. For two clocks to belong to the same clock domain, they must either be generated from the same source or the clocks must have a constant phase relationship and a low relative jitter.

Since clock drift between systems belonging to separate clock domains is unavoidable, periodic or constant resynchronization between modulators belonging to separate clock domains is obligatory.

The more accurate the desired synchronization in plesiochronous systems, the more often the synchronization protocol must be performed or the less the different clock domains may differ. This implies either very accurate and expensive timing resources or intensive resynchronization efforts.

Therefore, none of these prior art solutions are suitable for modern modular power conversion systems having a large number of power electronic devices and high timing accuracy requirements for synchronization.

Moreover, none of these prior art solutions guarantees a timing accuracy of 50ns or better, which is necessary to operate parallel or series connected switches without many additional measures.

EP2408110 describes an energy conversion device and in particular inverters and their controls. The energy is transferred from an AC power source to a motor via a plurality of parallel single drives, each drive having an inverter. Optical fibers or conductors connect a control circuit to the inverters. A periodic synchronization pulse is transmitted to the supply layer circuit of each of the parallel inverters to synchronize the operation and the data transfer for each of the parallel inverters. The document recognizes that drifts or differences in pulse frequencies of local oscillators in the supply layer circuit processing circuit over a period of time may cause a synchronization loss between synchronization pulses and then errors. Therefore, the data for synchronization is embedded in the data provided along the optical fibers or conductors connecting the control circuit to the drives. This data enables clock data recovery on the supply layer within the inverters. Based on the clock data recovery on the supply layer, the supply layer circuit of each inverter periodically corrects the deviations of its local oscillator by adding or subtracting one clock cycle.

Brief summary of the invention

It is therefore an object of the present invention to propose a distributed modulation system and method in which the modulated signals can be controlled with a high temporal accuracy, for example an accuracy of 50ns or better.

Another object is to propose a distributed modulation system and method which does not require an extra line carrying a synchronization signal.

Another object is to propose a distributed modulation system and method in which the synchronization consumes less data communication bandwidth than the known solutions.

Another object is to propose a distributed modulation system and method that offers complete flexibility in the configuration of carrier frequencies and relative phases between the distributed modulators.

• - mindestens einen Transceiver, der zum Empfangen von Steuerdaten von einem Steuermaster über mindestens einen Datenübertragungskanal konfiguriert ist, der ein vom Steuermaster erzeugtes Referenztaktsignal einbettet, wobei die Steuerdaten mindestens einen Satz von Modulationsparametern umfassen, wobei der Steuermaster zum Erzeugen eines auf dem Referenztaktsignal basierenden Unterbrechungssignals konfiguriert ist,
• - ein Taktwiederherstellungsmodul, das zum Wiederherstellen eines wiederhergestellten Taktsignals vom Datenübertragungskanal konfiguriert ist,
• - einen Modulator, der konfiguriert ist zum Erzeugen mindestens eines periodischen Trägers basierend auf dem besagten wiederhergestellten Taktsignal, und zum Erzeugen von Modulationssignalen basierend auf dem Satz von Modulationsparametern und auf dem besagten mindestens einen periodischen Träger,
• - ein Überwachungsmodul, das zum Mastern und Einstellen einer anfänglichen Phasendifferenz zwischen dem besagten mindestens einem periodischen Träger und dem besagten Unterbrechungssignal konfiguriert ist.

These objects are achieved according to the invention by an end node for a distributed modulation system for power electronic applications, comprising:

• at least one transceiver configured to receive control data from a control master via at least one communication channel that embeds a reference clock signal generated by the control master, the control data comprising at least one set of modulation parameters, the control master configured to generate an interrupt signal based on the reference clock signal is
• a clock recovery module configured to recover a recovered clock signal from the communication channel,
• a modulator configured to generate at least one periodic carrier based on said recovered clock signal, and to generate modulation signals based on the set of Modulation parameters and on said at least one periodic carrier,
• a monitoring module configured to master and adjust an initial phase difference between said at least one periodic carrier and said interrupt signal.

In the context of the present invention, the term "end node" refers to a circuit associated with the control stage of a power converter and configured to communicate with the power stage of such a converter, e.g. with a PEBB. In a preferred embodiment, the end node is physically separate from a PEBB. In another embodiment, an end node and a PEBB may be integrated in the same circuit or assembly.

The modulation signals from the end node are configured to determine the temporal moments of some operations: in a preferred embodiment, they are used to determine the switching timings of circuit breakers of a PEBB connected to the end node.

However, in other embodiments wherein the end node is not connected to a PEBB, the modulation signals may be used to determine temporal moments of some measurements, e.g. the sampling times of analog-to-digital converters in the control infrastructure thus constructed.

Since the generation of the carrier is based directly on the recovered clock signal, this has the modulator driving clock signal synton with the reference clock signal of the main controller. Therefore, if at least two end nodes according to the invention are present in the distributed modulation system, each clock signal driving its modulators is synchronized with the reference clock signal of the control master, so that the clock signals which drive the modulators are also identical to each other.

For two clocks to be syntonic (i.e., to have exactly the same frequency), they must belong to the same clock domain.

In a preferred embodiment, according to the invention, the end node comprises an electrical path which connects the clock recovery module directly to the modulator so that the modulator directly uses the recovered clock signal to generate the carriers.

In one embodiment, the clock recovery module is part of a PHY circuit. In the context of the present invention, the term "PHY circuit" refers to a circuit that implements physical layer functions (Layer 1) according to the OSI model.

In one embodiment, the terminal node according to the invention further comprises a clock cleaning circuit. This clock cleaning circuit may be integrated with the clock recovery module or may be a discrete device.

In one embodiment, the PHY circuit is associated with a MAC circuit configured to receive the control data including a set of modulation parameters from the PHY circuit, as will be described.

In one embodiment, mastering and adjusting the initial phase difference between the at least one periodic carrier and the interrupt signal is based on the precision time protocol as defined by the IEEE1588 standard.

The monitoring circuit is arranged to control these phase differences with a timing accuracy of 50ns or better.

• - ihre Modulatoren werden durch Takte angesteuert, die untereinander synton und auch synton mit dem Referenztaktsignal des Steuermasters sind;
• - sie besitzen eine Phasendifferenz zwischen den Trägern ihrer Modulatoren, die gemastered und eingestellt werden können.

For two or more end nodes according to the invention, therefore:

• - Their modulators are controlled by clocks that are synton synonymous and synton with the reference clock signal of the control master;
• they have a phase difference between the carriers of their modulators, which can be mastered and adjusted.

In the context of the present invention, two periodic signals derived from synton clocks having an adjustable and controlled phase difference are referred to as being "completely synchronous".

Therefore, in the case of an end node according to the invention, the carriers of the modulators and the interrupt signal of the control master are "completely synchronous".

If there is more than one end node according to the invention, the carriers of the modulators of the end nodes are "completely in sync" since each carrier and the interrupt signal of the control master are "completely synchronous".

In one embodiment, the modulator of the end node according to the invention further comprises a prescale module for reducing the frequency of the recovered clock signal by adjusting the frequency of the recovered signal Clock signal is divided by an integer, eg from 1 to 10. In other words, each carrier signal can be generated by a counter based on an integer part of the recovered clock.

The use of a clock recovery module in each end node allows the use of a clock recovered from the communications network, thereby circumventing the effects of timing skew between the end nodes and between the end nodes and the control master, thus allowing the distributed modulators to be part of the same clock domain and actually use a common time base defined by the reference clock generated by the control master.

As a consequence, the distributed modulators can only be synchronized once, typically during system boot, by mastering and adjusting the initial phase difference between the carriers and the interrupt signal, i. H. the phase difference between the carriers and the interrupt signal during system startup. Therefore, virtually no data bandwidth is consumed by the synchronization mechanisms during runtime.

Thus, the accuracy of the synchronization obtained may be equal to or better than 50ns, and enables synchronizations of the type C described above.

Consequently, because the clock signal is embedded in the communications network, synchronization does not require dedicated lines. Therefore, the number of required lines is reduced.

In the context of the application, the term "embedding" means integrating as an inherent part. Therefore, a clock signal that can be recovered from the transitions in a communication channel is considered embedded in that communication channel. The same applies to a set of data transmission channels, i. H. a data transmission network.

According to an independent aspect of the invention, at least one signal transmitted by the transceiver of the end node according to the invention to the control master via the data transmission network may be clocked with a clock signal different from the recovered clock signal.

At least one special network switch may be located in the communication network formed by one or more communication channels between at least one control master and at least one end node. The modulation parameters as well as other data can be routed through this special network switch. This facilitates the connection of the various end nodes in the system.

If there is a special network switch in the communication network, that particular switch must transmit the embedded reference clock signal obtained from the control master, at least for the data coming from the control master to the end nodes. In addition, some processing of the data packets, such as special aggregation and disaggregation, may be necessary to reduce their size and thus the minimum data transfer delays in the network.

In a preferred embodiment, the number of PHY circuits in each end node depends on the number of control buttons to which the end node must be connected. In such a case, the end node may include a multiplexer configured to multiplex the signals from the PHY circuits.

In one embodiment of the invention, at least two control masters can be used, whereby at least two different reference clock signals are distributed in at least two different data transmission networks. In this case, the monitoring module is also configured to select only one recovered clock signal, the selection being made according to some fallback or fault tolerance criteria with respect to a redundant mode of operation.

In this case, each end node must have at least two clock recovery circuits to extract the at least two clocks and select one of them to drive the modulator. This allows the use of a multiplexer to switch from one control master to another for redundancy purposes. If at least two control masters, and hence reference clocks, are used, all end nodes must use the same reference clock that is recovered from the same network. Otherwise, perfect synchronization of the carriers can not be achieved.

In one embodiment, the end node according to the invention further comprises a MAC circuit configured to receive the modulation parameters and other control data from the PHY circuit. In the context of the present invention, a "MAC circuit" is one Circuit implementing the media access control of the OSI model.

Therefore, in one embodiment, the end node monitoring circuit is also configured to observe the recovered clock signals and data outputs of the MAC circuits to detect defects in the primary network and to switch through the multiplexer to a secondary network. This multiplexer may also operate at another point in the data path, such as between the PHY and MAC circuits.

In one embodiment, the end node according to the invention further comprises a DMA circuit configured to receive the modulation parameters and other control data from the MAC circuit. In the context of the present invention, a "DMA circuit" is a circuit which implements layers 3 through 7 of the OSI model.

• - mindestens einen Steuermaster, umfassend
• - ein Zeitbasisgenerator, der zum Erzeugen eines Referenztaktsignals konfiguriert ist,
• - mindestens eine überwachende Steuerung, die zum Erzeugen mindestens eines Satzes von Modulationsparametern konfiguriert ist,
• - mindestens einen Endknoten gemäss der Erfindung,
• - mindestens einen Datenübertragungskanal, der den mindestens einen Endknoten mit mindestens einem Steuermaster verbindet.

The present invention also relates to a distributed modulation system for power electronic applications, comprising:

• - At least one control master, comprising
• a timebase generator configured to generate a reference clock signal,
• at least one supervisory controller configured to generate at least one set of modulation parameters,
• at least one end node according to the invention,
• - At least one data transmission channel that connects the at least one end node with at least one control master.

Advantageously, the clock signal driving the modulator, i. the clock, which serves as a time base for the modulator, the reconstructed reference clock signal of the control master.

In a preferred embodiment, the system includes at least two end nodes, wherein the clock signal for generating the carriers in each end node is the recovered clock signal syntonized with the reference clock signal.

In a preferred embodiment, the system comprises at least one power electronic device connected to at least one end node, wherein the modulation signal (s) is / are configured to determine the switching timings of power switches of a PEBB connected to that end node.

In a preferred embodiment, at least one PEBB forms or is part of a multilevel converter.

In a preferred embodiment, the data transmission channels are based on fiber links capable of a raw data bandwidth greater than one gigabit per second.

In a preferred embodiment, the data transmission channels are Ethernet type channels.

In a preferred embodiment, the system comprises two or more control masters, each control master generating a reference clock signal (RefCLK_A, RefCLK_B).

• - Erzeugen eines Referenztaktsignals unter Verwendung eines Zeitbasisgenerators von mindestens einem Steuermaster, wobei jeder Steuermaster so konfiguriert ist, dass er ein Referenztaktsignal erzeugt;
• - Erzeugen eines Unterbrechungssignals basierend auf dem Bezugstaktsignal;
• - Erzeugen mindestens eines Satzes von Modulationsparametern unter Verwendung von mindestens einer Überwachungssteuerung des Steuermasters;
• - Übertragen dieses Satzes von Modulationsparametern durch mindestens einen Datenübertragungskanal, der das Referenztaktsignal einbettet, an einen Endknoten, der ein Taktwiederherstellungsmodul und einen Modulator umfasst;
• - Wiederherstellen des Referenztaktsignals vom Datenübertragungskanal unter Verwendung des Taktwiederherstellungsmoduls;
• - Empfangen des mindestens einen Satzes von Modulationsparametern vom Steuerungsmastersignal;
• - Erzeugen mindestens eines periodischen Trägers basierend auf dem wiederhergestellten Taktsignal;
• - Mastering und Anpassen einer anfänglichen Phasendifferenz zwischen dem mindestens einen periodischen Träger und dem Unterbrechungssignal durch ein Überwachungsmodul;
• - Erzeugen von Modulationssignalen basierend auf den periodischen Trägern und dem Satz von Modulationsparametern; wobei die Modulationssignale konfiguriert sind zur Bestimmung der zeitlichen Momente einiger Operationen, z.B. zur Bestimmung der Schaltzeitpunkte von Leistungsschaltern eines mit dem Endknoten verbundenen PEBBs.

The present invention also relates to a method for a distributed modulation system for power electronic applications, comprising the following steps:

• Generating a reference clock signal using a time base generator from at least one control master, each control master configured to generate a reference clock signal;
• Generating an interrupt signal based on the reference clock signal;
• Generating at least one set of modulation parameters using at least one monitoring controller of the control master;
• - transmitting said set of modulation parameters to at least one data transmission channel which embeds said reference clock signal to an end node comprising a clock recovery module and a modulator;
• - restoring the reference clock signal from the communication channel using the clock recovery module;
• Receiving the at least one set of modulation parameters from the control master signal;
• - generating at least one periodic carrier based on the recovered clock signal;
• - Mastering and adjusting an initial phase difference between the at least one periodic carrier and the interrupt signal by a monitoring module;
• Generating modulation signals based on the periodic carriers and the set of modulation parameters; wherein the modulation signals are configured to determine the temporal moments of some operations, eg for determining the switching times of circuit breakers of a PEBB connected to the terminal node.

In one embodiment, the initial synchronization of the carriers is achieved by an algorithm based on the Precision Time Protocol (PTP) as defined by the IEEE1588 standard.

list of figures

• 1 zeigt schematisch ein verteiltes Modulationssystem.
• 2 veranschaulicht schematisch einen Endknoten.

The invention will be better understood from the description of an embodiment given by way of example and illustrated by the figures.

• 1 schematically shows a distributed modulation system.
• 2 schematically illustrates an end node.

Detailed description of possible embodiments of the invention

1 schematically shows an example of a modular power converter 2 using a distributed modulation system. This example includes two control masters 10 , several data transmission channels 201 , some special network switches 20 and a plurality of end nodes 30 some of which use power electronic components 40 (PEBBs) are connected. The purpose of this system is to convert one or more power signals into one or more power signals of different frequency, phase or amplitude. The number of end nodes and PEBBs in the system can range from 1 to 200 or more.

For example, the power conversion system could provide one or more DC to AC, DC to DC, AC to DC, or AC to AC converters, or any combination thereof.

Some of the components of the power conversion system may be implemented as modular units mounted, for example, in one or more racks and cabinets. Different components can be mounted in different rooms or at different locations.

The various end nodes may be independent units and may be located in remote locations, such as throughout large wind or solar farms.

The control master 10 include one or more monitoring controls 100 , The monitoring control 100 generates commands for the end nodes 30 including at least one set of modulation parameters for the distributed modulators. The supervisory controller also generates other parameters, commands, control data, and signals to control and configure the end nodes 30 , The supervisory controller also receives data from the end nodes 30 , such as measurement and feedback data, and adjusts the controller in response to this feedback.

The steering master 10 further comprises a timebase generator 101 for generating a reference clock signal RefCLK. The timebase generator may be a stand-alone circuit or embedded as part of one of the supervisory controllers.

The steering master 10 also includes an interrupt generator 102 for generating an interrupt signal which is sent to the supervisory controllers 100 is transmitted. This signal is used to determine at what times some processing and control routines must be executed. It is generated based on the reference clock signal RefCLK.

The control master 10 For example, they may be based on suitably programmed and customized BoomBox units as provided by the Applicant. Optionally, multiple "BoomBox" units can be stacked, thus providing the multiple supervisory controls 100 a given control master 10 form.

At least two networks A, B can be controlled by at least two control masters 10 be built around to provide redundancy. In fact, the secondary network B thus constructed is used as a fallback system in case of a faulty operation of the primary network A. Accordingly, at least two networks are thus implemented which propagate two different reference clocks RefCLK_A and RefCLK_B.

The monitoring control 100 includes a network interface, such as a Gigabit Ethernet interface, and transmits at least one set of modulation parameters and control data other than packets over the communication channels 201 , Its network interfaces are responsive to the reference clock signal RefCLK and therefore send data packets clocked directly with this reference clock signal. The clock signal RefCLK is thus in the data transmission channels 201 embedded.

A plurality of monitoring controls 100 can in a given control master 10 to add redundancy to increase the bandwidth and the number of instructions that can be generated during a given unit of time, or to increase the number of data transfer channels handled.

The special network switches 20 are responsible for controlling data between the supervisory controls 100 and the end node 30 and vice versa. To do this while at the same time guaranteeing low transmission delays, the special network switches 20 Aggregate and disaggregate data packets to overcome some limitations, such as the minimum packet length.

In addition, the special network switches ensure 20 the dissemination of the reference clock RefCLK across the entire network. To do this, they must repeat the embedded clock from the control master 10 at the end nodes 30 connected ports is received. On the other hand, they do not have a clock from the end nodes 30 comes, restore or reuse it to transfer data back to the control master.

The end nodes 30 will be more detailed in terms of 2 described. The purpose of these circuits 30 This is the modulation parameters and other control data from the monitoring controllers 100 to receive the modulation, for example, to the corresponding circuit breaker 40 to control and some other control data to their monitoring control 100 to transfer back.

In some cases, the end nodes can 30 also be responsible for taking over some of the control tasks that would otherwise be handled by the supervisory controls 100, thereby relieving the latter of some of their responsibilities.

The modulation parameters that are received may be typical parameters for a pulse width modulation strategy, such as frequency, duty cycle, phase shift, blanking time, etc., or any other type of modulation parameter. For example, you can refer to optimized pulse patterns that are stored locally in lookup tables.

The power electronics modules 40 receive the modulation signals on the modulation channels 401 and other input / output signals on the I / O channels 402 received from the end nodes 30 and are responsible for actually converting and outputting the power signals (not shown). Every PEBB 40 includes at least one power semiconductor switch in this example. In a preferred embodiment, each PEBB comprises 40 a variety of power semiconductor switches.

In general, it is an end node 30 physically to a power electronic module 40 connected. However, other configurations are possible, such as the use of some end nodes 30 that may not work with a PEBB 40 However, they only use their distributed modulators as clock and synchronization resources, for example to ensure the synchronism of some measurements with the operation of the power switches.

In some cases, the end node can 30 and the PEBB 40 be physically removed.

Every PEBB 40 includes one or more power semiconductor switches such as, without limitation, IGBTs, IGCTs, GTOs, thyristors, etc. The shape of the output power signal is determined by the switching timings of those components determined by the modulation signals coming from the distributed modulators through the modulation channels 401 be sent.

Depending on the organization of the system and the modulation parameters sent by the monitoring controllers, the system can realize a variety of functions, including, for example, a pulse width modulated multilevel energy conversion system.

2 schematically illustrates an example of an end node 30 , The illustrated circuit contains the connection to two data transmission channels 201 , each one PHY circuit 300 and a MAC circuit 301 use. It also includes a modulator 302 , a DMA circuit 303 as well as other peripherals 306 , There is also a monitoring module 304 and a multiplexer 305 available to select which recovered clock and data channel should be used. In the illustrated embodiment, all circuits are integrated into a single chip, such as an ASIC or FPGA. Other combinations are possible.

The PHY circuits 300 form an interface between the medium-dependent analog domain of the data transmission channels 201 and the digital domain of link-layer packet signaling. They encode and decode the transmitted and received data and implement the hardware transmit and receive function of data packets.

In one embodiment, the physical medium is 201 a Gigabit Ethernet (GbE) fiber optic cable. In this case, the end node can 30 a transceiver, such as an SFP transceiver, to convert the serial electrical signals into serial optical signals, and vice versa.

The PHY circuit 300 includes a clock recovery module (not shown) for recovering the reference clock from the data running on the communication channel and delivering it to an rCLK output. In an embodiment, the clock recovery module may include a clock cleaning circuit including, for example, a PLL.

The PHY circuit 300 may be integrated as a single PHY chip with clock recovery functionalities or as a combination of a PHY chip and a separate clock recovery module.

The PHY circuit 300 may provide other signals, including Precision Time Protocol (PTP) functionalities as defined by the IEEE1588 standard.

The MAC circuit 301 receives data from the PHY circuit 300 detects packet boundaries, assembles bits into packets, validates them, and performs some processing.

The modulator 302 receives the recovered clock signal rCLK from the PHY circuit and data from the MAC circuit 301 , Data received from the MAC circuit includes the modulation parameters and other configuration data.

The modulation parameters can be used to determine the switching times of the power switches and thus determine the shape of the output signals of the power converter. For example, the modulation parameters determine the pulse widths in a pulse width modulation scheme.

In a preferred embodiment, the modulation parameters are frequently updated, such as at a refresh rate of 0.05 kHz to 100 kHz, to produce useful modulation signals.

In one embodiment, a DMA circuit is implemented 303 used to process the control data provided by the MAC circuit 301 be received and sent to this. It typically implements the control layers 3 through 7 according to the OSI model. This circuit may also be responsible for determining the temporal integrity of the data, for example, for evaluating the timestamps of each data packet against a given time validity.

The monitoring module 304 is responsible for the initial synchronization of the modulator 302 existing carrier with the through the interruption generator 102 generated interrupt signal. For this purpose, it observes the value (s) of counters based on the recovered clock signal (the recovered clock signals) and generates a synchronization stroboscope (SYNC on the 2 ) for the modulator 302 and other peripherals 306 , These counters can either be from the PHY 300 or the MAC circuit 301 to be provided.

This initial synchronization always occurs during the initialization procedure of the end node 30 reached. It can also be reached periodically if necessary.

In one embodiment, the monitoring module is watching 304 when redundant networks are used, also the recovered clock signals as well as the data signals to evaluate the integrity of a given network. If necessary, the monitoring module triggers 304 the multiplexer 305 to switch from one network to another.

If present, the other peripherals are included 306 the necessary circuits to the rest of the input / output connectivity of the end node 30 and its other processing tasks. This block refers to additional I / O signals and can also be used with the monitoring controllers 100 in the same way as for the modulators 302 communicate.

LIST OF REFERENCE NUMBERS

1

control level

2

final stage

10

Master control

20

Special network switch

30

end nodes

40

PEBB

100

supervisory control

101

Time base generator

102

interrupt generator

201

Data transmission channel

300

PHY circuit

301

MAC circuit

302

modulator

303

DMA circuit

304

monitoring module

305

multiplexer

306

Other peripherals

401

modulation channels

402

Additional I / O channels

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 5642275A [0010]
• DE 10103031 A1 [0010]
• US 20100156188 A1 [0010]
• WO 14207436 A1 [0014]
• WO 13102779 [0014]
• DE 102013106006 [0020]
• EP 2800262 [0025]
• EP 2408110 [0032]

Claims (18)

End node (30) for a distributed modulation system for power electronic applications, comprising: at least one transceiver for receiving control data from a control master (10) via at least one data transmission channel (201) embedding a reference clock signal (RefCLK) generated by said control master (10), said control data comprising at least one set of modulation parameters Control master (10) is designed to generate an interrupt signal based on said reference clock signal (RefCLK), at least one clock recovery module adapted to recover a recovered clock signal (rCLK) from said data transfer channel, a modulator (302) adapted to generate at least one periodic carrier using said recovered clock signal (rCLK) and to generate modulation signals (401) based on said set of modulation parameters and on said at least one periodic carrier, a monitoring module configured to master and set an initial phase difference between the at least one periodic carrier and said interruption signal, said modulation signals being configured to determine temporal moments of some operations, for example to determine the switching timings of at least one power switch of a PEBB ( 40) connected to said end node. End node according to Claim 1 an electrical path that connects the clock recovery module directly to said modulator (302) so that said modulator (302) uses said recovered clock signal (rCLK) directly to generate said periodic carriers. End node according to one of Claims 1 or 2 wherein said recovered clock signal (rCLK) is syntonic with said reference clock signal (RefCLK). End node according to one of the preceding claims, wherein said monitoring module is arranged to control said phase difference with an accuracy of 50ns or better. End node according to one of the preceding claims, comprising at least one PHY circuit (300) comprising said at least one clock recovery module. End node according to the preceding claim, wherein the number of said PHY circuits (300) depends on the number of control masters (10) to which said end node (30) is to be connected. End node according to one of Claims 5 to 6 further comprising at least one MAC circuit (301) configured to receive the control data including a set of modulation parameters from the PHY circuit (s) (300). End node according to the preceding claim, comprising at least two PHY circuits (300) and / or at least two MAC circuits (301) and a multiplexer (305) for multiplexing signals from said PHY circuits (300) and / or is configured by said MAC circuits, wherein the monitoring module (304) is configured to select the PHY and / or MAC circuits used. End node according to one of Claims 7 to 8th a DMA circuit (303) configured to receive the modulation parameters and other control data from the MAC circuit. A distributed modulation system for power electronic applications, comprising: - at least one control master (10) having - a time base generator (101) configured to generate a reference clock signal (RefCLK), - at least one supervisory controller (100) generating at least one set of modulation parameters is configured, - at least one interrupt generator (102) for generating an interrupt signal, - at least one end node (30) according to one of Claims 1 to 9 , - at least one data transmission channel (201), which connects the at least one end node (30) with the at least one control master (10). A system according to the preceding claim, further comprising at least one power electronic device (40) connected to at least one end node (30), said power electronic device (40) comprising at least one power switch, said modulation signals (401) for determining the Switching times of the at least one circuit breaker are configured. A system according to the preceding claim, wherein at least one PEBB (40) forms or is part of a multilevel converter. System according to one of Claims 10 to 12 wherein the communication channel (201) is based on fiber links. A system according to the preceding claim, wherein the data transmission channel (201) is an Ethernet type channel. System according to one of Claims 10 to 14 wherein at least one transceiver of at least one end node (30) is configured to use a clock different from said recovered clock signal (rCLK) to transmit data back to the control master (10). System according to one of Claims 10 to 15 , with two or more control buttons (10), each control master (10) generating a reference clock signal (RefCLK_A, RefCLK_B), the monitoring module (304) of said end node (30) being further configured to select only a recovered clock signal (rCLK), the selection being made according to fault tolerance criteria. System according to one of Claims 10 to 16 , at least one network switch (20) configured to communicate control data between the monitoring controller (s) (100) and the end node (s) 30. Method for a distributed modulation system for power electronic applications, comprising the following steps: - generating a reference clock signal (RefCLK) using a time base generator (101) of a control master (10); Generating an interrupt signal based on the reference clock signal using an interrupt generator (102) of said control master; - generating at least one set of modulation parameters using at least one monitoring controller (100) of the control master; - transmitting said set of modulation parameters to at least one communication channel (201) embedding said reference clock signal (RefCLK) to an end node (30) comprising a clock recovery module and a modulator (302); - restoring the reference clock signal from the communication channel using the clock recovery module; Receiving the at least one set of modulation parameters from the control master signal; Generating at least one periodic carrier based on the recovered clock signal; - Mastering and setting an initial phase difference between the at least one periodic carrier and the interrupt signal by a monitoring module (304); Generating modulation signals based on the periodic carriers and the set of modulation parameters, wherein the modulation signals are configured to determine the temporal moments of some operations, for example to determine the switching timings of at least one power switch of a PEBB connected to the end node.

Images