CH713045B1 - Device, distributed modulation system and method for power electronic applications. - Google Patents

Abstract

The invention relates to a device (10, 20, 30) for a distributed modulation system for power electronic applications, having: at least one transceiver for receiving control data from a control master (10) via at least one data transmission channel (201), which embeds a reference clock signal (RefCLK). and having at least one set of modulation parameters, at least one clock recovery module arranged to recover a recovered clock signal from the data transmission channel (201), a modulator arranged to generate modulation signals based on the set of modulation parameters and on at least one periodic carrier using of the recovered clock signal, a monitoring module configured to master and adjust an initial phase difference between the periodic carrier(s) and an interrupt signal based on the reference clock signal. The present invention also relates to a distributed modulation system for power electronic applications, comprising this end node and a relative method. Furthermore, the invention relates to a method for a distributed modulation system.

Description

field of invention

The present invention relates to a device for a distributed modulation system for power electronic applications, such a system and a method for such a system.

Description of the prior art

[0002] Power converters or power conversion systems are often used to convert AC or DC signals into AC or DC signals of, for example, different amplitude or frequency.

[0003] Modern power converters comprise two parts. On the one hand, a power stage acts as a controllable valve(s) to shape the power signal(s) and regulate the corresponding power flow(s). The power stage usually includes current semiconductor switches such as IGBTs (Insulated Gate Bipolar Transistor), IGCTs (Insulated Gate Commutated Thyristor), GTOs (Gate Turn-Off Thyristor), thyristors, etc. On the other hand, a control stage generates control signals for these switches to convert the output power signal ( e) shape as desired.

[0004] Modern power converters generally use modulation techniques such as pulse width modulation (PWM) to combine good harmonic performance and good conversion efficiency.

The modulation is achieved by means of a modulator. In the context of the present invention, a modulator is a functional block that generates one or more modulation signals based on one or more carriers and a set of modulation parameters. In general, the modulation signal is a digital signal and the carrier is a periodic analog signal approximated by the value of a digital counter based on a clock signal. In the following, the expression “carrier (or signal) generated based on a clock signal” indicates that the carrier (or signal) is generated using a digital counter based on this clock signal.

A modulator can perform various modulations, for example pulse width modulation, pulse frequency modulation, space vector modulation, or perhaps use optimized pulse patterns to convert its inputs to its outputs.

In the case of a pulse width modulator, the carrier is a periodic waveform, such as a sawtooth or triangle waveform, generated based on a clock signal, and the main modulation parameter is a threshold. If the value of the carrier is higher than the threshold, the modulation signal is in a high state, otherwise it is in a low state.

The modulation signals are generally used to control one or more power semiconductor switches of the power stage, e.g., to determine the switching instants of these switches.

[0009] Modular power conversion systems that include a circuit with multiple power electronic packages (PEBBs) are well known. For example, systems are known which comprise between 1 and 2,000 blocks or more. The use of a modular design allows the ratings and performance of power converters to be easily scaled by paralleling or stacking different PEBBs. In addition, modular converters are easier and less expensive to develop and maintain, and are also more reliable due to possible redundancies.

Examples of modular power converters are given in US 5642275A, DE10103031A1 or US20100156188A1.

For a non-modular power conversion system, the overall system can be assimilated to a unique PEBB.

A known disadvantage of modular power conversion systems is the difficult operation and coordination of the multiple PEBBs, which require the modulation signals to be synchronized by appropriate techniques. This is particularly challenging when the modulators are within the PEBBs and when these are physically separate or geographically distributed, as in large facilities.

In practice, the synchronization of a plurality of modulation signals generated by a plurality of modulators located in different PEBBs involves two types of problems: first type of problem: synchronizing the operation of the modulators; this implies that it must be possible to adjust and master the relative phases and frequencies of the corresponding modulation signals; second type of problem: preservation of the temporal integrity of the modulation signals between the modulator(s) and the power switches.

WO14207436A1 and WO13102779 are examples of post-modulation synchronization systems related to the second type of questions mentioned above.

The present invention addresses the first type of problem.

Various concerns relate to the synchronization of modulation signals that meet different requirements in terms of timing accuracy. In the context of the present invention, the term "temporal accuracy" indicates that accuracy with which the phase difference between two signals can be controlled, e.g., mastered and adjusted. This "time accuracy" can also be referred to as "time jitter" or simply "jitter".

In particular, in a distributed modulation system, three different types of requirements for time accuracies can be distinguished: Type A: When PEBBs or groups of PEBBs are operated as separate low pulse count converters, such as six or twelve pulse converters connected in parallel, the need for synchronization accuracy is related to a small fraction of the AC power signal. For example, assuming a 50 Hz AC signal (alternating signal), this typically results in requirements on the order of 10µs to 1ms. Type B: When PEBBs or groups of PEBBS form a converter with higher pulse counts, such as PWM-driven converters, the necessary accuracy of synchronization between the converters relates to a small fraction of the switching frequency. For example, assuming an apparent switching frequency of 2 kHz, the requirements are typically in the order of 500ns to 10µs. These concerns also arise between the switch cells that make up the multilevel converters. Type C: When power semiconductor switches must be operated directly in series or in parallel, the required accuracy of synchronization relates to a small fraction of the switching transition time (from OFF to ON state or vice versa). For example, an accuracy of 50ns or more is needed to operate switches connected in parallel or in series without many additional measures.

The "time accuracy" required in a distributed modulation system for power applications must therefore be better than 1 ms and often of the order of tens to hundreds of nanoseconds.

The most obvious approach to synchronizing the operation of multiple modulators is to distribute to each of them a common clock signal using a dedicated electrical or optical line. In any case, this signal corresponds to an additional line to be added to the communication channel already existing between the modulators.

This approach is used, for example, in DE102013106006, where the frequency of the distributed clock signal is similar to that of the AC signal, thereby achieving synchronization of type A described above.

Alternatively, a clock signal with a frequency similar to that of the switching frequency can be fed to the PEBB controllers. A synchronization of the above type B can thus be achieved.

The number of signals that must be generated by the control stage increases with the number of PEBBs. Therefore, if additional synchronization signals need to be present in large systems, this requires a prohibitive number of lines to the PEBBs.

Instead of distributing a common clock signal, the synchronization can be achieved by means of a communication channel in connection with a suitable synchronization protocol. PTP over Ethernet is an example of such a synchronization protocol or communication channel.

In large systems with a high number of PEBBs, the synchronization protocol requires a significant amount of data to be transmitted continuously, reducing the available bandwidth for more useful information exchange (payload).

Alternatively, more specialized techniques can be implemented. For example, EP2800262 describes a control stage for commanding N power converters. However, the invention is limited to synchronization of type B above and the generation of phase-shifted carriers that are shifted by 360/N degrees.

Consequently, in all of the above cases, the slave circuits (i.e. the PEBBs and their modulators) have their own individual clocking resources (oscillators, crystals, etc.) and are therefore clocked on separate time bases. Therefore, they inherently belong to separate clock domains and form a set of plesiochronous systems.

In the context of the present invention, the expression "the circuits belong to separate clock domains" indicates that these circuits do not have a common time base. As a consequence, their clocks differ from each other since their frequencies are not exactly the same. For two clocks to belong to the same clock domain, they must either be generated from the same source, or the clocks must have a constant phase relationship and low relative jitter.

Since clock drifts between systems belonging to separate clock domains are unavoidable, periodic or constant resynchronization between modulators belonging to separate clock domains is mandatory.

[0029] The more precise the desired synchronization is in plesiochronous systems, the more frequently the synchronization protocol must be carried out or the less the different clock domains may deviate from one another. This implies either very accurate and expensive clocking resources or intensive resynchronization efforts.

Therefore, none of these solutions according to the prior art is suitable for modern modular energy conversion systems that have a large number of power electronic components and high requirements with regard to the time accuracy of the synchronization.

In addition, none of these prior art solutions guarantees a timing accuracy of 50 ns or better, which is necessary to operate parallel or series switches without many additional measures.

EP2408110 describes an energy conversion device and in particular inverters and their controls. Power is transferred from an AC power source to a motor through a plurality of parallel individual drives, each drive having an inverter. Optical fibers or conductors connect a control circuit to the inverters. A periodic synchronization pulse is transmitted to the power layer circuit of each of the parallel inverters to synchronize operation and data transfer for each of the parallel inverters. The document recognizes that drifts or differences in pulse frequencies of local oscillators in the processing circuitry of the power layer circuit can cause a loss of synchronization between synchronization pulses and then errors over a period of time. Therefore, the data for the synchronization is embedded in the data provided along the optical fibers or conductors connecting the control circuitry to the drivers. This data enables clock data recovery at the power layer within the inverters. Based on the clock data recovery on the supply plane, each inverter's supply plane circuit periodically corrects the drifts of its local oscillator by adding or subtracting a clock cycle.

Brief Summary of the Invention

It is therefore an object of the present invention to propose an apparatus and a method for operating a distributed modulation system in which the modulated signals can be controlled with a high temporal accuracy, for example an accuracy of 50 ns or better.

A distributed modulation system and method is preferably proposed in which no extra line carrying a synchronization signal is required.

Preferably, a distributed modulation system and method is proposed in which synchronization consumes less data communication bandwidth than known solutions.

Preferably, a distributed modulation system and method is proposed that offers complete flexibility in configuring the carrier frequencies and relative phases between the distributed modulators.

According to the invention, these aims are achieved by a device according to claim 1 and by a modulation system according to claim 8.

In the context of the present invention, the term "end node" means circuitry associated with the control stage of a power converter and configured to communicate with the power stage of such a converter, e.g., a PEBB. In a preferred embodiment, the end node is physically separate from a PEBB. In another embodiment, an end node and a PEBB may be integrated in the same circuit or assembly.

The modulation signals from the end node are configured to determine the instants in time of some operations: in a preferred embodiment they are used to determine the switching instants of power switches of a PEBB connected to the end node.

However, in other embodiments, where the end node is not connected to a PEBB, the modulation signals can be used to determine instants in time of some measurements, for example the sampling instants of analog-to-digital converters in the control infrastructure so constructed.

Since the generation of the carrier is based directly on the recovered clock signal, the clock signal driving the modulator is in syntony with the master controller's reference clock signal. Therefore, when there are at least two end nodes in the distributed modulation system, each clock signal driving their modulators is syntonic with the reference clock signal of the controlling master, so that the clock signals driving the modulators are also mutually identical.

For two clocks to be syntonic (i.e. have exactly the same frequency), they must belong to the same clock domain.

In a preferred embodiment, the end node comprises an electrical path that connects the clock recovery module directly to the modulator so that the modulator uses the recovered clock signal directly to generate the carriers.

In one embodiment, the clock recovery module is associated with a PHY circuit. In the context of the present invention, the term "PHY circuit" denotes a circuit that implements physical layer functions (Layer 1) according to the OSI model.

In one embodiment, the end node also includes clock cleaning circuitry. This clock cleaning circuit can be integrated into the clock recovery module or can be a discrete device.

In one embodiment, the PHY circuit is associated with a MAC circuit that is configured to receive the control data including a set of modulation parameters from the PHY circuit, as will be explained.

In one embodiment, the mastering and setting of the initial phase difference between the at least one periodic carrier and the interrupt signal is based on the Precision Time Protocol as defined by the IEEE1588 standard.

The monitoring circuit is set up to control these phase differences with a temporal accuracy of 50 ns or better.

The following therefore applies to two or more end nodes: their modulators are driven by clocks which are syntonous to each other and also syntonous to the reference clock signal of the control master; they have a phase difference between the carriers of their modulators that can be mastered and adjusted.

In the context of the present invention, two periodic signals derived from synton clocks and having an adjustable and controlled phase difference are referred to as "perfectly synchronous".

Therefore, in the case of an end node, the carriers of the modulators and the interrupt signal of the control master are "perfectly synchronous".

When there is more than one end node, the carriers of the end nodes' modulators are "perfectly synchronous" since each carrier and the interrupt signal of the control master are "perfectly synchronous".

In one embodiment, the end node modulator further comprises a prescaling module to reduce the frequency of the recovered clock signal by dividing the frequency of the recovered clock signal by an integer, e.g., from 1 to 10 Counter can be generated based on an integer portion of the recovered clock.

The use of a clock recovery module in each end node allows the use of a clock recovered from the data transmission network, thereby bypassing the effects of clock skew between the end nodes and between the end nodes and the control master, and therefore allows the distributed modulators belonging to the same clock domain and actually using a common time base defined by the reference clock generated by the controlling master.

As a consequence, the distributed modulators can only be synchronized once, typically during system start-up, by mastering and adjusting the initial phase difference between the carriers and the interrupt signal, i. H. the phase difference between the carriers and the interrupt signal during system start-up. Therefore, practically no data bandwidth is consumed by the synchronization mechanisms during runtime.

Consequently, the accuracy of the synchronization obtained can be equal to or better than 50 ns and it allows synchronizations of the type C described above.

Consequently, because the clock signal is embedded in the data transmission network, synchronization does not require dedicated lines. Therefore, the number of lines required is reduced.

In the context of the application, the term "embedding" means integrating as an inherent part. Therefore, a clock signal that can be recovered from the transitions in a data pipe is said to be embedded in that data pipe. The same applies to a set of data transmission channels, i. H. a data transmission network.

According to one aspect of the invention, at least one signal sent from the transceiver of the end node to the controlling master via the data transmission network can be clocked with a clock signal that differs from the recovered clock signal.

At least one dedicated network switch can be arranged in the data transmission network formed by one or more data transmission channels between at least one control master and at least one end node. The modulation parameters as well as other data can be routed through this dedicated network switch. This facilitates the connection of the various end nodes in the system.

If there is a special network switch in the data transmission network, this special switch has to transmit the embedded reference clock signal obtained from the control master, at least for the data coming from the control master to the end nodes. In addition, some processing of the data packets, such as special aggregation and deaggregation, may be necessary to reduce their size and hence the minimum data transmission delays in the network.

In a preferred embodiment, the number of PHY circuits in each end node depends on the number of controlling masters to which the end node needs to be connected. In such a case, the end node may include a multiplexer configured to multiplex the signals from the PHY circuits.

In an embodiment of the invention, at least two control masters can be used, whereby at least two different reference clock signals are distributed in at least two different data transmission networks. In this case, the monitoring module is also configured to select only a clock signal to be recovered, the selection being made according to some fallback or fault tolerance criteria related to an operating mode in the redundant mode.

In this case, each end node must have at least two clock recovery circuits to extract the at least two clocks and select one of them to drive the modulator. This allows the use of a multiplexer to switch from one control master to another for redundancy purposes. If at least two control masters and thus reference clocks are used, all end nodes must use the same reference clock recovered from the same network. Otherwise, perfect synchronization of the carriers cannot be achieved.

In one embodiment, the end node further includes MAC circuitry configured to receive the modulation parameters and other control data from the PHY circuitry. In the context of the present invention, a "MAC circuit" is a circuit that implements the media access control of the OSI model.

Therefore, in one embodiment, the end node monitoring circuitry is also configured to monitor the recovered clock signals and data outputs of the MAC circuits to detect failures in the primary network and switch through the multiplexer to a secondary network. This multiplexer can also operate at another point in the data path, such as between the PHY and MAC circuits.

In one embodiment, the end node also includes a DMA circuit configured to receive the modulation parameters and other control data from the MAC circuit. In the context of the present invention, a "DMA circuit" is a circuit that implements layers 3 through 7 of the OSI model.

The present invention also relates to a distributed modulation system according to claim 8.

Advantageously, the clock signal that drives the modulator, i.e. the clock that serves as a time base for the modulator, is the recovered reference clock signal of the control master.

In a preferred embodiment, the system comprises at least two end-nodes, wherein the clock signal for generating the carriers in each end-node is the recovered clock signal syntonous with the reference clock signal.

In a preferred embodiment, the system comprises at least one electronic power module that is connected to at least one end node, the modulation signal(s) being/are configured to determine the switching times of power switches of a power switch connected to this end node.

In a preferred embodiment, at least one said power electronic component forms a multilevel converter or is part of one.

In a preferred embodiment, the data transmission channels are based on fiber optic links capable of raw data bandwidth in excess of one gigabit per second.

In a preferred embodiment, the communication channels are Ethernet-type channels.

In a preferred embodiment, the system comprises two or more control masters, each control master generating a reference clock signal (RefCLK_A, RefCLK_B).

The present invention also relates to a method for a distributed modulation system for power electronic applications according to claim 15.

In one embodiment, the initial synchronization of the carriers is achieved using an algorithm based on the Precision Time Protocol (PTP) as defined by the IEEE1588 standard.

Brief description of the drawings

The invention will be better understood from the description of an embodiment given by way of example and illustrated by the figures. 1 schematically shows a distributed modulation system. 2 schematically illustrates an end node.

Detailed description of possible embodiments of the invention

Figure 1 shows schematically an example of a modular power converter 2 using a distributed modulation system. This example comprises two control masters 10, several data transmission channels 201, some special network switches 20 and a multitude of end nodes 30, some of which are connected to power electronic components 40 (PEBBs). The purpose of this system is to convert one or more power signals into one or more power signals of different frequency, phase or amplitude. The number of end nodes and PEBBs in the system can range from 1 to 200 or more.

[0080] For example, the power conversion system could implement one or more DC-to-AC, DC-to-DC, AC-to-DC, or AC-to-AC converters, or any combination thereof.

[0081] Some of the components of the power conversion system may be implemented as modular building units, mounted in one or more racks and cabinets, for example. Different components can be assembled in different rooms or at different locations.

The various end nodes may be independent entities and may be located at remote locations, such as anywhere in large wind or solar farms.

The control masters 10 include one or more supervisory controllers 100. The supervisory controller 100 generates commands for the end nodes 30, including at least one set of modulation parameters for the distributed modulators. The supervisory controller also generates other parameters, commands, control data, and signals for controlling and configuring the end nodes 30. The supervisory controller also receives data from the end nodes 30, such as measurement and feedback data, and adjusts the controller in response to that feedback.

The control master 10 further comprises a time base generator 101 for generating a reference clock signal RefCLK. The time base generator can be a standalone circuit or embedded as part of one of the supervisory controllers.

The control master 10 also includes an interrupt generator 102 for generating an interrupt signal which is transmitted to the monitoring controllers 100. This signal is used to determine when some processing and control routines need to be performed. It is generated based on the reference clock signal RefCLK.

The control masters 10 can be based, for example, on suitably programmed and adapted "BoomBox" units, as provided by the applicant. If desired, multiple "BoomBox" units can also be stacked, thus forming the multiple supervisory controllers 100 of a given control master 10.

At least two networks A, B can be built around at least two control masters 10 to provide redundancy. In fact, the secondary network B thus constructed is used as a fallback system in case of faulty operation of the primary network A. Accordingly, at least two networks are implemented, which propagate two different reference clocks RefCLK_A and RefCLK_B.

The monitoring controller 100 includes a network interface, for example a gigabit Ethernet interface, and sends at least one set of modulation parameters and other control data as packets via the data transmission channels 201. Its network interfaces are syntonous to the reference clock signal RefCLK and therefore send data packets that directly are clocked with this reference clock signal. The clock signal RefCLK is thus embedded in the data transmission channels 201.

A plurality of supervisory controllers 100 can be used in a given control master 10 to add redundancy, to increase the bandwidth and the number of commands that can be generated during a given unit of time, or to increase the number of communication channels handled raise.

The dedicated network switches 20 are responsible for transferring control data between the supervisory controllers 100 and the end nodes 30 and vice versa. In order to do this while at the same time guaranteeing low transmission delays, the special network switches 20 can aggregate and de-aggregate data packets to circumvent some restrictions, such as those related to the minimum packet length.

[0091] In addition, the special network switches 20 ensure that the reference clock RefCLK is distributed over the entire network. To do this, they must repeat the embedded clock received from the control master 10 on the ports connected to the end nodes 30. On the other hand, they do not have to recover a clock originating from the end nodes 30, nor reuse it to transmit data back to the controlling master.

The end nodes 30 are described in more detail with reference to FIG. The purpose of these circuits 30 is to receive the modulation parameters and other control data from the supervisory controls 100 in order to perform the modulation, e.g.

In some cases, the end nodes 30 may also be responsible for taking over some of the control tasks otherwise handled by the supervisory controllers 100, thereby freeing the latter from some of their tasks.

The modulation parameters that are received can be typical parameters for a pulse width modulation strategy, such as frequency, duty cycle, phase shift, blanking time, etc., or any other type of modulation parameters. For example, you can also refer to optimized pulse patterns stored locally in lookup tables.

The power electronics components 40 receive the modulation signals on the modulation channels 401 as well as other input/output signals on the I/O channels 402 generated by the end nodes 30 and are responsible for actually converting the power signals (not shown) and to deliver. Each PEBB 40 includes at least one power semiconductor switch in this example. In a preferred embodiment, each PEBB 40 includes a plurality of power semiconductor switches.

In general, an end node 30 is physically connected to a power electronic device 40 . However, other configurations are possible, such as using some end nodes 30, which may not be connected to a PEBB 40, but which only use their distributed modulators as clock and synchronization resources, for example to ensure the synchronism of some measurements with the operation of the power switches to guarantee.

In some cases, the end node 30 and the PEBB 40 may be physically remote.

Each PEBB 40 includes one or more power semiconductor switches such as, without limitation, IGBTs, IGCTs, GTOs, thyristors, etc. The shape of the output power signal is determined by the switching instants of these components, which are determined by the modulation signals generated by the distributed modulators sent over the modulation channels 401.

Depending on the organization of the system and the modulation parameters sent by the supervisory controllers, the system can implement a variety of functions including, for example, a multilevel pulse width modulated energy conversion system.

Figure 2 schematically illustrates an example of an end node 30. The circuit shown includes the connection to two data transmission channels 201, each using a PHY circuit 300 and a MAC circuit 301. It also includes a modulator 302, a DMA circuit 303 and other peripherals 306. There is also a monitor module 304 and a multiplexer 305 to select which recovered clock and data link 201 should be used. In the illustrated embodiment, all circuitry is integrated into a single chip, such as an ASIC or FPGA. Other combinations are possible.

The PHY circuits 300 form an interface between the medium-dependent analog domain of the data transmission channels 201 and the digital domain of the link-layer packet signaling. They encode and decode the transmitted and received data and implement the hardware sending and receiving function of data packets.

In one embodiment, the physical medium 201 is a Gigabit Ethernet (GbE) fiber optic cable. In this case, the end node 30 may include a transceiver, such as an SFP transceiver, to convert the serial electrical signals into serial optical signals and vice versa.

The PHY circuit 300 includes a clock recovery module (not shown) to recover the reference clock from the data traveling on the data pipe 201 and provide it to an rCLK output. In one embodiment, the clock recovery module may include a clock cleaning circuit including, for example, a PLL.

[0104] The PHY circuit 300 may be integrated as a single PHY chip with clock recovery functionalities or as a combination of a PHY chip and a separate clock recovery module.

[0105] The PHY circuit 300 may provide other signals, including functionality related to the Precision Time Protocol (PTP) as defined by the IEEE1588 standard.

MAC circuitry 301 receives data from PHY circuitry 300, detects packet boundaries, assembles bits into packets, validates them, and performs some processing tasks.

The modulator 302 receives the recovered clock signal rCLK from the PHY circuit and data from the MAC circuit 301. Data received from the MAC circuit includes the modulation parameters and other configuration data.

The modulation parameters can be used to determine the switching times of the power switches and thus determine the shape of the output signals of the power converter. For example, the modulation parameters determine the pulse widths in a pulse width modulation scheme.

In a preferred embodiment, the modulation parameters are updated frequently, such as at a refresh rate of 0.05 kHz to 100 kHz, to produce useful modulation signals.

In one embodiment, a DMA circuit 303 is used to process the control data received from and sent to the MAC circuit 301 . It typically implements the control layers 3 to 7 according to the OSI model. This circuit can also be responsible for determining the chronological integrity of the data, for example for evaluating the time stamp of each data packet against a given chronological validity.

The monitoring module 304 is responsible for the initial synchronization of the carriers present in the modulator 302 with the interrupt signal generated by the interrupt generator 102. To do this, it observes the value(s) of counters based on the recovered clock signal(s) and generates a synchronization strobe (SYNC on Fig. 2) for the modulator 302 and other peripherals 306. These counters can be provided by either the PHY 300 or the MAC circuitry 301.

This initial synchronization is always achieved during the end node 30 initialization procedure. It can also be reached periodically if necessary.

In one embodiment, when redundant networks are used, the monitoring module 304 also monitors the recovered clock signals as well as the data signals to assess the integrity of a given network. If necessary, the monitoring module 304 triggers the multiplexer 305 to switch from one network to another.

If present, the other peripherals 306 contain the necessary circuitry to handle the rest of the end node's 30 input/output connectivity as well as its other processing tasks. This block relates to additional I/O signals and can also communicate with the supervisory controllers 100 in the same way as for the modulators 302.

Reference numbers used in the figures

1 control stage 2 output stage 10 control master 20 special network switch 30 end node 40 PEBB 100 supervisory controller 101 time base generator 102 interrupt generator 201 data transmission channel 300 PHY circuit 301 MAC circuit 302 modulator 303 DMA circuit 304 supervisory module 305 multiplexer 306 other peripheral devices 401 modulation channels 402 /O channels

Claims (15)

1. Device (10, 30, 40), having a control master (10), an end node (30) for a distributed modulation system for power electronic applications and at least one power electronic power electronic building block as a power electronic component (40) connected to the end node (30 ), where the end node (30) has: - at least one transceiver for receiving control data from the control master (10) via at least one data transmission channel (201), embedding a reference clock signal generated by said control master (10), said control data comprising at least one set of modulation parameters, - wherein said control master (10) is adapted to generate an interrupt signal based on said reference clock signal, - at least one clock recovery module suitable for producing a recovered clock signal from said data transmission channel (201), - a modulator (302) adapted to generate at least one periodic carrier using said recovered clock signal and to generate modulation signals based on said set of modulation parameters and on said at least one periodic carrier, - a monitoring module suitable for mastering and setting an initial phase difference between the at least one periodic carrier and said interrupt signal, wherein said modulation signals are suitable for determining the switching times of at least one power switch of the electronic power module (40). 2. Apparatus according to claim 1 including an electrical path connecting the clock recovery module directly to said modulator (302) so that said modulator (302) can use said recovered clock signal directly to generate said periodic carriers. 3. Device according to one of claims 1 or 2, arranged such that said recovered clock signal is syntonic with said reference clock signal. 4. Device according to one of the preceding claims, comprising at least one PHY circuit (300) comprising said at least one clock recovery module. The apparatus of claim 4, further comprising at least one MAC circuit (301) configured to receive the control data including a set of modulation parameters from the at least one PHY circuit (300). 6. Device according to the preceding claim, with at least two PHY circuits (300) and/or at least two MAC circuits (301) and a multiplexer (305) for multiplexing signals from said PHY circuits (300) and /or configured by said MAC circuitry, wherein the monitoring module (304) is configured to select the PHY and/or MAC circuitry used. 7. Apparatus according to any one of claims 5 to 6, including a DMA circuit (303) configured to receive the modulation parameters and other control data from the MAC circuit. 8. Distributed modulation system for power electronic applications, comprising: - at least one device (10, 30, 40) according to any one of claims 1 to 7, in which said control master (10) has the following characteristics: - a time base generator (101) configured to generate a reference clock signal, and - at least one supervisory controller (100) configured to generate at least one set of modulation parameters, and having - at least one interrupt generator (102) for generating an interrupt signal, wherein the at least one device (10, 30, 40) has at least one data transmission channel (201) which connects the end node (30) to the control master (10). 9. System according to claim 8, wherein at least one of said electronic power modules (40) forms a multilevel converter. 10. System according to any one of claims 8 to 9, wherein the data transmission channel (201) is based on fiber optic connections. The system according to claim 10, wherein the data transmission channel (201) is an Ethernet type channel. The system of any one of claims 8 to 11, wherein at least one transceiver of at least one end node (30) is configured to use a clock different from said recovered clock signal to transmit data back to the controlling master (10). The system of any of claims 8 to 12, comprising two or more of the control masters (10), each control master (10) being configured to generate a reference clock signal (A, B), the monitoring module (304) of said end node (30) further configured to select only one recovered clock signal, the selection being performed according to fault tolerance criteria. 14. System according to any one of claims 8 to 13, with at least one network switch (20) which is configured to transmit control data between the at least one supervisory controller (100) and the end node (30). 15. Method for operating a distributed modulation system for power electronic applications, with the following steps: - generating a reference clock signal using a time base generator (101) of a control master (10); - generating an interrupt signal based on the reference clock signal using an interrupt generator (102) of said control master (10); - generating at least one set of modulation parameters using at least one supervisory control (100) of the control master; - transmitting this set of modulation parameters through at least one data transmission channel (201) embedding the reference clock signal to an end node (30) comprising a clock recovery module and a modulator (302); - recovering the reference clock signal from the data transmission channel (201) using the clock recovery module; - receiving the at least one set of modulation parameters from a signal of the control master; - generating at least one periodic carrier based on the recovered clock signal; - mastering and adjusting an initial phase difference between the at least one periodic carrier and the interrupt signal by a monitoring module (304); - Generating modulation signals based on the periodic carriers and the set of modulation parameters, the modulation signals being designed to determine the switching times of at least one power switch of a power electronic component connected to the end node.