DE112011105725T5 - Output compensation circuit of LCD data driver IC, compensation method and liquid crystal panel - Google Patents

Abstract

The invention relates to an output compensation circuit of LCD data driver IC, a compensation method and a liquid crystal screen, the circuit having a data driver IC, a plurality of first switching units and delay control units, and wherein a plurality of output channels from the data driver IC each through data lines with the pixel electrode on the corresponding one Line are connected in the glass substrate and output the charging signal to charge the pixel electrode on the corresponding line; and a first switching unit being arranged on each output channel in order to control the output channel on which the first switching unit is located in accordance with the delay control signals generated by the delay control units, so that the charging signal is output in accordance with the predetermined delay; and wherein each delay control unit serves to generate a corresponding delay control signal according to the impedance value of the corresponding data lines and to control the start of the corresponding first switching unit after a predetermined delay, so that the charging time of each pixel electrode is identical. The present invention does not require winding and reduces the trace space of the glass substrate, which favors the design of the narrow frame of the liquid crystal display, and improves the problem with EMI that arises when all output channels are opened at the same time.

Description

Technical area

The present invention relates to the technical field of liquid crystal display, more particularly to an output compensation circuit of LCD data driver IC which is conducive to the design of the narrow frame of the liquid crystal panel, a compensation method and a liquid crystal panel.

State of the art

As in 1 shown when the data lines 2 in the liquid crystal panel from the driver IC (integrated circuit, integrated circuit) 3 are output, the impedance of each data line should be 2 be essentially identical to tracks, so that the signal of each data line 2 at the same time every pixel reaches every line.

In order for the impedance of each track to be substantially identical when each pixel is reached, a stretch of serpentine track is usually used in the prior art. The data lines 2 first go through a stretch of serpentine winding and then get to the pixel domain 1 connected, based on the material and the length of the data lines 2 is the impedance of each data line 2 essentially identical. Thus, when the scan lines open the pixel of a particular line, all the output channels enter from data driver IC 3 At the same time, at this time, the impedance of each row of data lines is identical so that the charging time of each pixel on the same row is identical, thus the screen has a good homogeneity. On the contrary, if the design of the impedance of the data lines is unidentical, the charging time of each pixel on the same line will be different, so that the screen display of the domain controlled by respective data lines may have a problem with inhomogeneity.

However, with the increase in the number of output channels of each data driver IC 3 For example, the required space for serpentine tracks may increase to meet the output compensation. But at present, the development of the frame tends to be in the direction of a frame, so that the space for winding will gradually decrease, therefore, the tracking method of the existing serpentine data lines does not meet the requirements of the narrow-frame liquid crystal panel, making the space of winding small and small the screen is homogeneous. Further, the output channels of data driver IC 3 essentially a simultaneous output, if all the output channels are opened simultaneously, a relatively large current must be provided to the glass substrate, thus creating the problem of EMI (Electro Magnetic Interference).

Content of the invention

The main object of the invention is to provide an output compensation circuit of LCD data driver IC, a compensation method, and a liquid crystal display panel to downsize the track space of the glass substrate and to favor the design of the narrow frame of the liquid crystal display panel.

In order to achieve the above object, the present invention discloses an output compensation circuit of LCD data driver IC, comprising a data driver IC, a plurality of first switching units, and delay control units, wherein:
the data driver IC has a plurality of output channels, and wherein the plurality of output channels are respectively connected through the data lines to the pixel electrode on the corresponding row in the glass substrate to output the charging signal so that the pixel electrode is charged on the corresponding row;
and wherein the first switching units are respectively arranged on each output channel and connected to the corresponding delay control units to control the output channel at which the first switching unit is located, in accordance with the delay control signals generated by the delay control units, so that the charging signal is output according to the predetermined delay ;
and wherein the delay control units serve to generate a corresponding delay control signal in accordance with the impedance value of the respective data lines and to control the start of the corresponding first switching unit after a predetermined delay, so that the charging time of each pixel electrode is identical.

Preferably, the delay control unit comprises shift actuators and second switching units, wherein the first and the second switching units are both MOS transistors, and wherein
the shift triggers of each delay control unit are cascade-connected to each other, and wherein each shift trigger has a first input port, a second input port and an output port, and only the first input port of the first-cascade shift trigger is connected to the external input port of the high / low-level trigger signal; to receive the high / low level trigger signal input from the outside, and the first input terminal of the shift trigger of other cascades are respectively connected to the output terminal the shift trigger of the first cascade is connected to the first input terminal of the shift trigger of the first cascade, respectively, and the second input terminal of each shift trigger is connected to a time controller, and the output terminal of each Shift trigger is respectively connected to the drain electrode of the corresponding second switching unit and the gate electrode of the corresponding first switching unit, and wherein the source electrode of the second switching unit is grounded; and wherein the drain of each first switching unit is connected to the corresponding output channel, and wherein the source of each first switching unit connects the corresponding pixel electrode;
when the first input terminal of the shift trigger from the first cascade receives the high level trigger signal, each shift trigger cascade-generates the delay-predetermined delay signal in accordance with the frequency of the timing signal generated by the timing controller and cascades the corresponding first switching unit; When the first input terminal of the shift trigger from the first cascade receives the low-level trigger signal, each shift trigger respectively controls and switches the second switch unit connected thereto, and the shift trigger controls the turn-off of the corresponding first switch unit.

Preferably, the impedance value of the data lines decreases symmetrically along the two ends of the data driver IC to the center in cascade.

Preferably, the data driver IC has n output channels, the number of the first switching unit corresponding to n; when the number of output channels is an even number, the number of the delay control unit is n / 2, with the cascaded interconnect triggers having n / 2 cascades, and the shift trigger of each cascade having a second switching unit connected thereto, and the output terminal of the tripping trigger each of the first cascade is connected to the gate electrode of the first and nth first switching units, and wherein the output terminal of the shift trigger of the second cascade is connected to the gate electrode of the second and (n-1) th first switching unit, respectively continuing analogously, and where n is a natural number;
or when the number of output channels is an odd number, the number of delay control units is (n + 1) / 2, with the cascaded interconnect solvers having (n + 1) / 2 cascades, and to the relocation trigger of each cascade being a second switching unit and the output terminal of the displacement trigger of the first cascade is connected to the gate electrodes of the first and fifth first switching units, respectively, and the output terminal of the displacement trigger of the second cascade is respectively connected to the gate electrode of the second and (n). 1) the first switching unit is connected, and it proceeds analogously thereto, and wherein the output terminal of the displacement trigger of the nth cascade is connected to the gate of the (n + 1) / 2nd first switching unit, and where n is a natural number is.

Preferably, the data driver IC has n output channels, wherein the number of the first switching unit is n, and wherein the number of the delay control unit is n, and wherein the cascaded interconnect triggers have n cascades, and a second switching unit is connected to the relocation trigger of each cascade and wherein the output terminal of the displacement trigger of the first cascade is connected to the gate of the first first switching unit, and wherein the output terminal of the displacement trigger of the second cascade is connected to the gate of the second first switching unit, and wherein continues analogously, and wherein the output terminal of the displacement trigger of the nth cascade is connected to the gate of the nth first switching unit.

Preferably, the high / low level trigger signal is a load signal output by the data driver IC.

Preferably, the cascaded shift trigger is the shift memory in the data driver IC.

The time controller is preferably embedded in the data driver IC.

Further, the present invention discloses a compensation method of the LCD data driver IC, comprising the following steps:
that the delay control units under control of the time controller according to the impedance value of respective data line between the data driver IC and the pixel electrode on the corresponding row in the glass substrate generate a corresponding delay control signal and send to the first switching unit on the output driver IC corresponding output channel;
the first switching unit controls the output channel corresponding to the data driver IC in accordance with the delay control signal, the output channel at which the first switching unit is located, so that it outputs the charge signal to the corresponding pixel electrode after the predetermined delay so that the pixel electrode on the corresponding row has the same charge time.

Preferably, the present method further comprises: when the delay controllers receive the high level trigger signal, each delay controller generates a corresponding delay control signal according to the frequency of the timing signal output by the timing controller and cascades the corresponding first switching unit such that the output channel at which the corresponding one of the output channels first switching unit is located, after the predetermined delay outputs the charging signal to the corresponding pixel electrode; When the delay control units receive the low-level trigger signal, each delay control unit controls the turn-off of the corresponding first switching unit.

Preferably, the impedance value of the data lines decreases symmetrically along the two ends of the data driver IC to the center in cascade.

The present invention further discloses a liquid crystal panel having an output compensation circuit of data driver IC, the output compensation circuit of data driver IC having a data driver IC, a plurality of first switching units and delay control units, and wherein:
the data driver IC has a plurality of output channels, and wherein the plurality of output channels are respectively connected through the data lines to the pixel electrode on the corresponding row in the glass substrate to output the charging signal so that the pixel electrode is charged on the corresponding row;
and wherein the first switching units are respectively arranged on each output channel and connected to the corresponding delay control units to control the output channel at which the first switching unit is located, in accordance with the delay control signals generated by the delay control units, so that the charging signal is output according to the predetermined delay ;
and wherein the delay control units serve to generate a corresponding delay control signal in accordance with the impedance value of the respective data lines and to control the start of the corresponding first switching unit after a predetermined delay, so that the charging time of each pixel electrode is identical.

Preferably, the delay control unit comprises shift actuators and second switching units, wherein the first and the second switching units are both MOS transistors,
and wherein the shift triggers of each delay control unit are cascade-connected with each other, and wherein each shift trigger has a first input port, a second input port, and an output port, and wherein only the first input port of the first-cascade shift trigger is connected to the external input port of the high / low-level trigger signal is to receive the high / low level trigger signal input from the outside, and wherein the first input terminal of the shift trigger of other cascades is connected to the output terminal of the shift trigger of the previous cascade respectively, and wherein the first input terminal of the shift trigger from the first cascade is connected to the gate electrode of each second switching unit, and wherein the second input terminal of each shift trigger is connected to a time controller, and wherein the output each shift trigger is respectively connected to the drain of the corresponding second switching unit and the gate of the corresponding first switching unit, and wherein the source of the second switching unit is grounded;
and wherein the drain of each first switching unit is connected to the corresponding output channel, and wherein the source of each first switching unit connects the corresponding pixel electrode;
when the first input terminal of the shift trigger from the first cascade receives the high level trigger signal, each shift trigger cascade-generates the delay-predetermined delay signal in accordance with the frequency of the timing signal generated by the timing controller and cascades the corresponding first switching unit; When the first input terminal of the shift trigger from the first cascade receives the low-level trigger signal, each shift trigger respectively controls and switches the second switch unit connected thereto, and the shift trigger controls the turn-off of the corresponding first switch unit.

Preferably, the impedance value of the data lines decreases symmetrically along the two ends of the data driver IC to the center in cascade.

Preferably, the data driver IC has n output channels, the number of the first switching unit corresponding to n; when the number of output channels is an even number, the number of the delay control unit is n / 2, which is cascaded with each other Shift trigger having n / 2 cascades, and wherein the shift trigger of each cascade, a second switching unit is connected, and wherein the output terminal of the shift trigger of the first cascade is respectively connected to the gate electrode of the first and nten first switching unit, and wherein the output terminal of Shift trigger of the second cascade is connected to the gate electrode of the second and (n-1) th first switching unit, respectively, and analogously thereto, and n is a natural number;
or when the number of output channels is an odd number, the number of delay control units is (n + 1) / 2, with the cascaded interconnect solvers having (n + 1) / 2 cascades, and to the relocation trigger of each cascade being a second switching unit and the output terminal of the displacement trigger of the first cascade is connected to the gate electrodes of the first and fifth first switching units, respectively, and the output terminal of the displacement trigger of the second cascade is respectively connected to the gate electrode of the second and (n). 1) the first switching unit is connected, and it proceeds analogously thereto, and wherein the output terminal of the displacement trigger of the (n + 1) / 2nd cascade is connected to the gate electrode of the (n + 1) / 2nd first switching unit, and where n is a natural number.

Preferably, the data driver IC has n output channels, wherein the number of the first switching unit is n, and wherein the number of the delay control unit is n, and wherein the cascaded interconnect triggers have n cascades, and a second switching unit is connected to the relocation trigger of each cascade and wherein the output terminal of the displacement trigger of the first cascade is connected to the gate of the first first switching unit, and wherein the output terminal of the displacement trigger of the second cascade is connected to the gate of the second first switching unit, and wherein continues analogously, and wherein the output terminal of the displacement trigger of the nth cascade is connected to the gate of the nth first switching unit.

Preferably, the high / low level trigger signal is a load signal output by the data driver IC.

Preferably, the cascaded shift trigger is the shift memory in the data driver IC.

The time controller is preferably embedded in the data driver IC.

The present invention discloses an output compensation circuit of LCD data driver IC, a compensation method, and a liquid crystal panel. With the delay control units, the load signal output from the data driver IC is successively delayed from both sides to the center, so that the problem that the impedances of the Data lines from the data driver IC to the pixel electrode on each line do not mate with each other so that each output channel on the pixel electrode on a particular row is substantially identical. Since the data lines do not need a winding process, the homogeneity of the display of the liquid crystal panel is ensured, while the glass substrate has a small trace space, which can better promote the design of the narrow frame of the liquid crystal panel. Furthermore, more output channels can be used for COF (Chip On Film) to reduce costs. It also improves the problem with EMI, which results from simultaneous opening of all output channels.

Short description of the drawing

In 1 FIG. 12 is a schematic structural view that the prior art data driver IC interconnects the pixel domains through the data lines; FIG.

In 2 Fig. 12 is a schematic structural view that, in an embodiment of the output compensation circuit of LCD data driver IC according to the present invention, the data driver IC connects the pixel domains through the data lines;

3 Fig. 10 is a schematic structural view of an embodiment of the output compensation circuit of LCD data driver IC according to the present invention;

4 Fig. 12 is a schematic representation of the timing of operation of each output channel in the embodiment of the output compensation circuit of LCD data driver IC according to the present invention; and

5 Fig. 10 is a schematic diagram of the procedure in the embodiment of the output compensation method of LCD data driver IC according to the present invention.

In order to make the technical programs of the present invention clearer and clearer, they are explained in the following with reference to figures.

Detailed embodiment

It should be understood that the detailed embodiments described herein are merely illustrative of the present invention rather than limitation of the present invention.

The main solution of the present invention is: control switches are arranged on the output channels of data driver IC, and by the delay control units according to the impedance value of each data line, the switches on each output channel are closed cascade, so that the respective pixel electrode on each row in the glass substrate is identical and Homogeneity of the display is ensured. For the data lines, it is unnecessary to use the serpentine tracks, so that the winding space is reduced, and this is conducive to the design of the narrow frame of the liquid crystal panel.

Please refer 2 and 3 in connection, 2 Fig. 12 is a schematic structural view showing that the data lines output by the data driver IC according to the present invention need no winding and charge the pixel electrode. 3 Fig. 12 is a schematic structural view of the output compensation circuit of data driver IC according to the present invention.

In 2 connects the data driver IC 30 through several data lines (denoted by N in Figure, n is a natural number) 20 the pixel domain 10 and loads the pixel electrode in the pixel domain 10 on.

When the data lines 20 from the data driver IC 30 the tracks are not serpentine tracks like in 1 but just traces, thereby the space wasted by winding is saved, so that the frame of the liquid crystal panel can be narrower. However, if used straight, each one has the data driver IC 30 output data line 20 different length and unidentical impedance value when all output channels from the data driver IC 30 output simultaneously loads the data signal through each data line 20 the corresponding pixel for different time, the data line 20 with high impedance value, it charges for a relatively short time, so that the display of the data driven by the data driver IC 30 controlled pixel domain 10 is inhomogeneous. Therefore, the output time of each output channel is changed by the delay control unit 50 controlled so that the output time of each output channel to the impedance value of the corresponding data line 20 matches to ensure that each output channel loads the pixel electrodes on a given row of the pixel domain 10 for an identical time, so that a homogeneous display is produced.

As in 3 in detail, the output compensation circuit of LCD data driver IC, a data driver IC 30 , several first switching units 40 and a plurality of delay controllers 50 on, where:
the data driver IC 30 has a plurality of output channels, and wherein the plurality of output channels respectively through the data lines 20 are connected to the pixel electrode on the corresponding row in the glass substrate to output the charging signal, so that the pixel electrode is charged on the corresponding row;
and wherein each switching unit 40 is arranged corresponding to each output channel and with the corresponding delay control unit 50 is connected in accordance with the by the delay control unit 50 generated delay control signals to control the output channel, where the first switching unit 40 is, so that the charging signal is output according to the predetermined delay;
and wherein each delay control unit 50 this is done according to the impedance value of the corresponding data lines 20 to generate a corresponding delay control signal and the start of the corresponding first switching unit 40 after a predetermined delay, so that the charging time of each pixel electrode is identical.

The delay control unit 50 has a move trigger 501 and a second switching unit 502 on, the first and second switching unit 40 . 502 Both are MOS transistors (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor), wherein the first switching unit 40 is an NMOS transistor, and wherein the second switching unit 502 a PMOS transistor is.

In the present embodiment, the shift initiators are 501 respective delay control units 50 connected in cascade with each shift trigger 501 a first input terminal, a second input terminal and an output terminal, and wherein only the first input terminal of the shift trigger 501 of the first cascade is connected to the external input terminal of the high / low level (out on) trigger signal to receive the high / low level trigger signal input from the outside, and the first input terminal of the shift trigger 501 from other cascades respectively to the output terminal of the shift trigger 501 from the previous cascade is connected.

To the second input terminal of each shift trigger 501 In each case a time controller is connected, wherein the output terminal of each shift trigger 501 Further, each with the drain electrode of the corresponding second switching unit 502 is connected and in each case with the gate electrode of the corresponding first switching unit 40 is connected, and wherein the source electrode of each second switching unit 502 is grounded.

Further, the first input terminal of the shift trigger 501 from the first cascade to the gate electrode of each second switching unit, respectively 502 connected.

The drain of each first switching unit 40 is connected to the corresponding output channel, wherein the source electrode of each first switching unit 40 the corresponding pixel electrode connects.

If the first input port of the shift trigger 501 each shift trigger will generate the high level trigger signal from the first cascade 501 in accordance with the frequency of the timing signal generated by the timing controller, the delay control signal defining the delay is cascaded and switches the corresponding first switching unit 40 in cascade; when the first input terminal of the shift trigger 501 from the first cascade receives the low level trigger signal, each shift trigger controls and switches 501 in each case the second switching unit 502 on, which is connected to it, and the shift trigger controls the elimination of the corresponding first switching unit 40 ,

The present invention explains it under the example that the impedance value of the data lines 20 symmetrical along the two ends of data driver IC 30 cascaded down to the middle, but the data line 20 with a smallest impedance is not necessarily located on the output channel in the middle of COF, from the middle channel to both ends is the increase of the impedance of the data line 20 not necessarily symmetrical. The delay should be adjusted according to the actual impedance distribution to achieve the best effect.

The data driver IC defined by the present embodiment 30 has the output channels of a number of the odd number, with the example it is explained, ie, the number n of the output channels from the data driver IC 30 defined as an odd number, n = 2k - 1, where k is a natural number, 2k - 1 output channels correspond to 2k - 1 data lines 20 , accordingly, the number of the first switching unit 40 2k - 1. At the same time the number of delay control unit 50 defined as k, the cascaded shift triggers 501 have k cascades, with the shift trigger 501 from each cascade a second switching unit 502 connected. The output terminal of the shift trigger 501 of the first cascade is respectively to the gate electrode of the 1st and (2k-1) th first switching unit 40 connected, the output terminal of the shift trigger 501 of the second cascade is respectively to the gate electrode of the 2nd and (2k - 2) th first switching unit 40 connected, and where it continues analogously, and wherein the output terminal of the shift trigger 501 from the kth cascade to the gate of the kth first switching unit 40 connected.

The track method of the data lines 20 as in 2 The size of their impedance decreases symmetrically from both ends to the middle in cascade.

The kte data line 20 returns from the kth channel from the data driver IC 30 This channel has a shortest path between the data driver IC 30 and the pixel domain 10 and a smallest impedance. The impedance of left and right channels has a symmetrical gradual increase. The impedance value of the first data line 20 reduces down to the kten data line 20 from the (k + 1) th data line 20 on, the impedance value increases in a line up to the (2k - 1) th data line 20 , wherein the first data line 20 and the (2k - 1) th data line 20 have an identical impedance value, and wherein the second data line 20 and the (2k - 2) th data line 20 have an identical impedance value and continue analogously, and where the (k-1) th data line 20 and the (k + 1) th data line 20 have an identical impedance value, and wherein the kte data line 20 has a smallest impedance value. Thus, if the delay controllers 50 for the pixel electrode on each line does not work and each output channel from the data driver IC 30 simultaneously outputting signals, the charging time from the kth output channel to both sides gradually decreases, so that the display color is different when an equal gray level is displayed in the middle.

By controlling the delay control units 50 becomes the output time of the load signal of each output channel from the data driver IC 30 set so that the pixel electrodes on each row in the pixel domain 10 have identical loading time, concrete principles as follows:
The (2k - 1) te switching unit 40 corresponds in each case to the switch which controls the output channel on which the (2k - 1) nth data line 20 located. The 1st first switching unit 40 is located at the first output channels from the data driver IC 30 to the circuit of the first data line 20 to control. The 2nd first switching unit 40 is located on the second output channel of the data driver IC 30 to the circuit of the second data line 20 to steer, it continues analogously to the kte first switching unit 40 is located on the kth output channel of the data driver IC 30 to the circuit of the kten data line 20 to control the (2k - 1) te first switching unit 40 is located on the (2k - 1) th output channel of the data driver IC 30 to the circuit of the (2k - 1) th data line 20 to control.

The move trigger 501 In the present embodiment, a D flip-flop may be rising edge.

The cascade-linked displacement trigger 501 is a k-stage series-connected D flip-flop rising edge 501 , the output terminal of the D flip-flop rising edge 501 Each stage connects the gate electrode of the corresponding first switching unit 40 to open and close the corresponding first switching unit 40 to control.

Concretely speaking, the output terminal of the D flip-flop connects rising edge 501 first stage, the gate electrode of the first switching unit 40 from the 1st and the (2k - 1) th data line 20 , the second-stage output terminal connects the gate of the first switching unit 40 from the 2nd and the (2k - 2) th data line 20 Similarly, the output terminal of the (k-1) th stage connects the gate electrode of the first switching unit 40 from the (k-1) th and the (k + 1) th data line 20 The output terminal of the kth stage connects the gate electrode of the first switching unit 40 from the kth data line 20 ,

The gate electrode of each second switching unit 502 connects the input terminal of the D flip-flop rising edge 502 the first stage and simultaneously receives the high / low trigger signal input from the outside.

The drain of each second switching unit 502 respectively correspondingly connects the gate electrode of the first switching unit 40 that is, the drain electrode of the 1st second switching unit 502 connects the gate electrode of the first first switching unit 40 , the drain electrode of the second second switching unit 502 connects the gate electrode of the second first switching unit 40 , Where it goes on analogously to continue, the drain of the kten second switching unit 502 connects the gate electrode of the kth first switching unit 40 , the drain electrode of the (2k-1) th second switching unit 502 connects the gate electrode of the (2k-1) th first switching unit 40 , the source electrode of all second switching unit 502 is grounded.

4 Figure 3 is a schematic representation of the timing of each output channel operating from the data driver IC 30 when the rising edge of the clock signal clk of the second input terminal, namely the timing signal input terminal of the cascade with each other connected D-flipflop rising edge 501 occurs, the D flip-flop rising edge 501 and its turning state is determined by the level of the level of the out on signal received by the second input terminal. Before the t1 time, the out on signal has a low level, the output terminal of each rising edge of the D flip flop 501 has low level, all first switching unit 40 are in the off state. At the time t1, the out-on signal jumps from the low level to the high level, at which time the rising edge of the clock signal of the second input terminal from the rising-edge D flip-flop occurs 501 the first stage, the D-flipflop rising edge 501 the first stage, the output terminal of the D flip-flop rising edge 501 the first stage 501 turns to the high level and becomes the second input terminal of the rising edge D flip-flop 501 provided at the second stage, at this time, the gate electrodes of the 1st receive the first switching unit 40 and the (2k - 1). first switching unit 40 and control the start of the first data line and the (2k-1) th data line to charge the corresponding pixel. At the t2 point in time, the second input terminal jumps from the D flip-flop rising edge 501 the second stage to the high level, before the next rising edge of the clock signal occurs, the output terminal of the D flip-flop uses rising edge 501 the second stage to the high level, at this time, the gate electrodes of the 2nd receive the first switching unit 40 and the (2k - 2). first switching unit 40 High level and control the start of the second data line and the (2k - 2) th data line to charge the corresponding pixel, it continues analogously. At tk time, the output terminal of the D flip-flop gives rising edge 501 kth high level, the gate of kten first switching unit 40 receives high level and controls the start of the kth data line, until now each delay controller controls 50 the output channels of each data line 20 so that they are turned on at a reasonable time, hence the data lines 20 are turned on from both ends to the center, the difference of the impedance value is compensated so that an identical charging time of each pixel electrode is ensured.

At the tm point in time, the second input terminal changes from the cascade-connected D flip-flop to the rising edge 501 from high level to low level. At this time, the output channels are from all data lines 20 under the down train of the second switching unit 502 closed fast as lightning.

In the present embodiment, the data driver IC 30 and the delay controllers 50 by the methods of COF or COG (chip on glass, encapsulation of the chip on the glass) are laminated on the glass substrate.

If the data driver IC 30 The output channels having an even number number, n = 2k (where k is a natural number), is the output compensation principle of the data driver IC 30 like the above embodiment, only the number of output channels is different. The impedance value of the data lines 20 are still decreasing evenly from both ends to the middle, under the control of time controls generating the delay controllers 50 according to the impedance value of the respective data line 20 a corresponding delay control signal, so that by the data driver IC 30 output charge signal is delayed from both sides to the center one after the other, so that the problem is compensated that the impedances of the data lines 20 from data driver IC 30 to the pixel electrode on each line do not mate with each other so that each output channel on the pixel electrode on a particular row is substantially identical. According to various designs for traces of the liquid crystal panel in other embodiments, the impedance value of the data lines decreases 20 not necessarily from both ends to the center regularly, the increase of the impedance from the middle to both ends is not necessarily symmetrical, the delay of the waveform will also be different. At this time, the delay of the output waveform must be set by the actual impedance distribution, e.g. For example, the D-flipflop may be rising edge 501 each stage one or more series-connected D flip-flops (s) rising edge 501 to obtain adequate compensation so that the charging time of each pixel electrode is identical.

In this case, the cascaded D flip-flop rising edge 501 also in the sliding memory in the data driver IC 30 can be shared, the time controller can also be in the data driver IC 30 embedded, furthermore, T-CON in the data driver IC 30 is used to connect the second input port of the shift controller or the receive port of the timing signal to the output port of T-CON (time-control controller), it is provided by T-CON. Since the clock signal has a relatively high frequency at this time, an appropriate Δt can be obtained by controlling the frequency of the clock signal clk of the cascade-connected D flip-flop of rising edge 501 are generated so that an identical charging time of each pixel electrode ensured and an optimal real display is realized. At the same time, the length of the delay of the output channel can be controlled by controlling the frequency of clk or by separating it through more D flip-flops.

Further, the edge rising through the first input terminal of the cascade-connected D-type flip-flop may be 501 Also, the high / low level trigger signal received will also be the load signal output by the data driver IC.

In the present embodiment, the output time of each output channel is adjusted so that the output time of each passage matches the impedance value of the corresponding data line to ensure that each passage charges the pixel electrodes on a particular row for an identical time, thus providing a homogeneous display becomes. As a result, no serpentine tracks are required for the output compensation, the utilization rate of the glass substrate is increased, the frame of the glass can be narrowed, the data driver IC 30 can use multiple output channels, reducing costs. The method further improves the problem with EMI caused by simultaneous opening of all channels.

According to the principle of the above preferred embodiments, based on the number of delay control units 50 and the output channels from the data driver IC 30 be defined accordingly, that is, when the data driver IC 30 n channels, the number of the delay control unit is 50 also n, the cascaded interconnected displacement trigger 501 have n cascades, the output terminal of the shift trigger 501 from the first cascade to the gate of the first first switching unit 40 is connected, and wherein the output terminal of the shift trigger 501 from the second cascade to the gate electrode of the second first switching unit 40 is connected, and it continues analogously, and wherein the output terminal of the shift trigger 501 from the nth cascade to the gate of the nth first switching unit 40 is connected, and the other operations and principles are the same as the above preferred embodiments.

As in 5 Further, the present invention further discloses an output compensation method of the LCD data driver IC, comprising:
Step S101, wherein the delay control units under control of the time controller according to the impedance value of respective data line between the data driver IC and the pixel electrode on the corresponding row in the glass substrate generate a corresponding delay control signal and send to the first switching unit on the output driver IC corresponding output channel;
Step S102, wherein the first switching unit controls the output channel corresponding to the data driver IC according to the delay control signal, the output channel on which the first switching unit is located so as to output the charging signal to the corresponding pixel electrode after the predetermined delay to cause the pixel electrode on the pixel electrode corresponding line has the same load time.

In the output compensation method of the LCD data driver IC according to the present invention, when the delay control units receive the high level trigger signal, each delay control unit generates a corresponding delay control signal according to the frequency of the timing signal outputted by the time controller and cascades the corresponding first switching unit so that the output channel, where the corresponding first switching unit is located, after the predetermined delay, outputs the charging signal to the corresponding pixel electrode; When the delay control units receive the low-level trigger signal, each delay control unit controls the turn-off of the corresponding first switching unit.

In the output compensation method of the LCD data driver IC according to the present invention, the impedance value of the data lines gradually decreases symmetrically from both ends to the center, but according to various designs of the tracks of the liquid crystal panel, the impedance value of the data lines does not necessarily decrease from both ends to the center regularly Increasing the impedance from the center to both ends is not necessarily symmetrical, the delay of the waveform will also be different. At this time, the delay of the output waveform must be adjusted by the actual impedance distribution to realize a best effect. For the basic principle of output compensation from the data driver IC, please refer to the detailed embodiment of the output compensation circuit, which will not be discussed further here.

Further, the present invention provides a liquid crystal panel, the liquid crystal panel has the output compensation circuit of the LCD data driver IC according to the present embodiment, and will not be described here.

The present invention discloses an output compensation circuit of LCD data driver IC, a compensation method, and a liquid crystal panel. With the delay control units, the load signal output from the data driver IC is successively delayed from both sides to the center, so that the problem that the impedances of the Data lines from the data driver IC to the pixel electrode on each line do not mate with each other so that each output channel on the pixel electrode on a particular row is substantially identical. Since the data lines do not need a winding process, the homogeneity of the display of the liquid crystal panel is ensured, while the glass substrate has a small trace space, which can better promote the design of the narrow frame of the liquid crystal panel. Furthermore, more output channels can be used for COF to reduce costs. It also improves the problem with EMI, which results from simultaneous opening of all output channels.

The foregoing is merely preferred embodiments of the present invention and therefore does not limit the scope of the present invention. Any equivalent structures or process modifications made using the description or figures of the present invention or directly or indirectly employed in other relevant technical fields are within the scope of the present invention.

Claims (19)

An output compensation circuit of LCD data driver IC, characterized by comprising: a data driver IC, a plurality of first switching units and delay control units, wherein the data driver IC has a plurality of output channels, and wherein the plurality of output channels are each through the data lines having the pixel electrode on the corresponding one of the output channels Line in the glass substrate are connected to output the charging signal, so that the pixel electrode is loaded on the corresponding line; and wherein the first switching units are respectively arranged on each output channel and connected to the corresponding delay control units to control the output channel at which the first switching unit is located, in accordance with the delay control signals generated by the delay control units, so that the charging signal is output according to the predetermined delay ; and wherein the delay control units serve to generate a corresponding delay control signal in accordance with the impedance value of the respective data lines and to start the start of the delay corresponding first switching unit to control after a predetermined delay, so that the charging time of each pixel electrode is identical. The output compensation circuit of LCD data driver IC according to claim 1, characterized in that the delay control unit comprises shift trigger and second switching units, wherein the first and second switching units are both MOS transistors, and wherein: the shift triggers of each delay control unit are connected to each other in a cascade, and wherein each shift trigger has a first input terminal, a second input terminal, and an output terminal, and wherein only the first input terminal of the first-cascade shift trigger is connected to the external input terminal of the high / low level trigger signal by the high / low level trigger signal input from the outside and wherein the first input port of the shift trigger of other cascades is respectively connected to the output port of the shift trigger from the previous cascade, and wherein the first input The output terminal of the shift trigger of the first cascade is connected to the gate of each second switching unit, and the second input terminal of each shift trigger is connected to a time controller, and the output terminal of each shift trigger is connected to the drain of the corresponding second switching unit Gate electrode of the corresponding first switching unit is connected, and wherein the source electrode of each second switching unit is grounded in each case; and wherein the drain of each first switching unit is connected to the corresponding output channel, and wherein the source of each first switching unit connects the corresponding pixel electrode; when the first input terminal of the shift trigger from the first cascade receives the high level trigger signal, each shift trigger cascade-generates the delay-predetermined delay signal in accordance with the frequency of the timing signal generated by the timing controller and cascades the corresponding first switching unit; When the first input terminal of the shift trigger from the first cascade receives the low-level trigger signal, each shift trigger respectively controls and switches the second switch unit connected thereto, and the shift trigger controls the turn-off of the corresponding first switch unit. An output compensation circuit of LCD data driver IC according to claim 2, characterized in that the impedance value of the data lines is reduced cascade-wise symmetrically along both ends of the data driver IC to the middle. An output compensation circuit of LCD data driver IC according to claim 3, characterized in that the data driver IC has n output channels, the number of the first switching unit being n corresponding to n; when the number of output channels is an even number, the number of the delay control unit is n / 2, with the cascaded interconnect triggers having n / 2 cascades, and the shift trigger of each cascade having a second switching unit connected thereto, and the output terminal of the tripping trigger each of the first cascade is connected to the gate electrode of the first and nth first switching units, and wherein the output terminal of the shift trigger of the second cascade is connected to the gate electrode of the second and (n-1) th first switching unit, respectively continuing analogously, and where n is a natural number; or when the number of output channels is an odd number, the number of delay control units is (n + 1) / 2, with the cascaded interconnect solvers having (n + 1) / 2 cascades, and to the relocation trigger of each cascade being a second switching unit and the output terminal of the displacement trigger of the first cascade is connected to the gate electrodes of the first and fifth first switching units, respectively, and the output terminal of the displacement trigger of the second cascade is respectively connected to the gate electrode of the second and (n). 1) the first switching unit is connected, and it proceeds analogously thereto, and wherein the output terminal of the displacement trigger of the (n + 1) / 2nd cascade is connected to the gate electrode of the (n + 1) / 2nd first switching unit, and where n is a natural number. The output compensation circuit of LCD data driver IC according to claim 3, characterized in that the data driver IC has n output channels, the number of the first switching unit is n, and wherein the number of the delay controller is n, and wherein the cascaded interconnect trigger n Cascades, and wherein a second switching unit is connected to the shift trigger of each cascade, and wherein the output terminal of the shift trigger from the first cascade is connected to the gate electrode of the first first switching unit, and wherein the output terminal of the shift trigger from the second cascade to the Gate electrode of the second first switching unit is connected, and it proceeds analogously thereto, and wherein the output terminal of the displacement trigger of the nth cascade is connected to the gate electrode of the nth first switching unit. An output compensation circuit of LCD data driver IC according to claim 2, characterized in that said high / low level trigger signal is the load signal output by said data driver IC. An output compensation circuit of LCD data driver IC according to claim 2, characterized in that the cascaded shift trigger is the shift memory in the data driver IC. An output compensation circuit of LCD data driver IC according to claim 6, characterized in that the time controller is embedded in the data driver IC. Output compensation process from the LCD data driver IC, characterized in that it comprises the following steps: that the delay control units generate, under the control of the timing controller in accordance with the impedance value of each data line between the data driver IC and the pixel electrode on the corresponding line in the glass substrate, a corresponding delay control signal and for send first switching unit on output channel corresponding to the data driver IC; that the first switching unit at the output channel corresponding to the data driver IC according to the delay control signal controls the output channel at which the first switching unit is located so that it outputs the charging signal to the corresponding pixel electrode after the predetermined delay, so that the pixel electrode on the corresponding line same Loading time has. The output compensation method of the LCD data driver IC according to claim 9, characterized by further comprising: when the delay control units receive the high level trigger signal, each delay control unit generates a corresponding delay control signal according to the frequency of the timing signal output by the time controller and cascades the corresponding first switching unit such that the output channel at which the corresponding first switching unit is located outputs, after the predetermined delay, the charging signal to the corresponding pixel electrode; When the delay control units receive the low-level trigger signal, each delay control unit controls the turn-off of the corresponding first switching unit. An output compensation method of the LCD data driver IC according to claim 9, characterized in that the impedance value of the data lines decreases cascade-wise symmetrically along both ends of the data driver IC to the middle. A liquid crystal panel comprising an output compensation circuit of data driver IC, characterized in that the output compensation circuit of data driver IC comprises a data driver IC, a plurality of first switching units and delay control units, and wherein: the data driver IC has a plurality of output channels, and wherein the plurality of output channels are respectively through the data lines are connected to the pixel electrode on the corresponding row in the glass substrate to output the charging signal, so that the pixel electrode is charged on the corresponding row; and wherein the first switching units are respectively arranged on each output channel and connected to the corresponding delay control units to control the output channel at which the first switching unit is located, in accordance with the delay control signals generated by the delay control units, so that the charging signal is output according to the predetermined delay ; and wherein the delay control units serve to generate a corresponding delay control signal in accordance with the impedance value of the respective data lines and to control the start of the corresponding first switching unit after a predetermined delay, so that the charging time of each pixel electrode is identical. A liquid crystal display panel as claimed in claim 12, characterized in that the delay control unit comprises displacement initiators and second switching units, wherein the first and second switching units are both MOS transistors, and wherein: the displacement triggers of each delay control unit are cascade-connected to each other, and wherein each displacement triggers a first input terminal, a first input terminal and an output terminal, and wherein only the first input terminal of the first trigger cascade is connected to the external input terminal of the high / low level trigger signal to receive the high / low level trigger signal input from the outside, and wherein the first input terminal of the shift trigger of other cascades is respectively connected to the output terminal of the shift trigger of the previous cascade, and wherein the first input terminal of the Verschi ebeauslösers of the first cascade each with the gate electrode each second switching unit is connected, and wherein the second input terminal of each shift trigger is connected to a time controller, and wherein the output terminal of each shift trigger is respectively connected to the drain of the corresponding second switching unit and the gate electrode of the corresponding first switching unit, and wherein the Source electrode of the second switching unit is grounded; and wherein the drain of each first switching unit is connected to the corresponding output channel, and wherein the source of each first switching unit connects the corresponding pixel electrode; when the first input terminal of the shift trigger from the first cascade receives the high level trigger signal, each shift trigger cascade-generates the delay-predetermined delay signal in accordance with the frequency of the timing signal generated by the timing controller and cascades the corresponding first switching unit; When the first input terminal of the shift trigger from the first cascade receives the low-level trigger signal, each shift trigger respectively controls and switches the second switch unit connected thereto, and the shift trigger controls the turn-off of the corresponding first switch unit. A liquid crystal panel according to claim 13, characterized in that the impedance value of the data lines is reduced cascade-wise symmetrically along the both ends of the data driver IC to the center. A liquid crystal panel according to claim 14, characterized in that the data driver IC has n output channels, the number of the first switching unit being n corresponding to n; when the number of output channels is an even number, the number of the delay control unit is n / 2, with the cascaded interconnect triggers having n / 2 cascades, and the shift trigger of each cascade having a second switching unit connected thereto, and the output terminal of the tripping trigger each of the first cascade is connected to the gate electrode of the first and nth first switching units, and wherein the output terminal of the shift trigger of the second cascade is connected to the gate electrode of the second and (n-1) th first switching unit, respectively continuing analogously, and where n is a natural number; or when the number of output channels is an odd number, the number of delay control units is (n + 1) / 2, with the cascaded interconnect solvers having (n + 1) / 2 cascades, and to the relocation trigger of each cascade being a second switching unit and the output terminal of the displacement trigger of the first cascade is connected to the gate electrodes of the first and fifth first switching units, respectively, and the output terminal of the displacement trigger of the second cascade is respectively connected to the gate electrode of the second and (n). 1) the first switching unit is connected, and it proceeds analogously thereto, and wherein the output terminal of the displacement trigger of the (n + 1) / 2nd cascade is connected to the gate electrode of the (n + 1) / 2nd first switching unit, and where n is a natural number. A liquid crystal panel according to claim 14, characterized in that the data driver IC has n output channels, the number of the first switching unit is n, and wherein the number of the delay control unit is n, and wherein the cascaded interconnect triggers have n cascades, and wherein the shift trigger of each cascade is connected to a second switching unit, and wherein the output terminal of the shift trigger from the first cascade is connected to the gate of the first first switching unit, and the output terminal of the shift trigger from the second cascade to the gate of the second first Switching unit is connected, and it proceeds analogously thereto, and wherein the output terminal of the displacement trigger of the nth cascade is connected to the gate of the nth first switching unit. A liquid crystal panel according to claim 13, characterized in that the high / low level trigger signal is the load signal output by the data driver IC. A liquid crystal panel according to claim 13, characterized in that the cascaded shift trigger is the shift memory in the data driver IC. Liquid crystal screen according to claim 18, characterized in that the time controller is embedded in the data driver IC.

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