CN107886921B - Source driver, method for realizing multi-gray-scale binding voltage combination thereof and driving circuit - Google Patents

Source driver, method for realizing multi-gray-scale binding voltage combination thereof and driving circuit Download PDF

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Publication number
CN107886921B
CN107886921B CN201711268733.3A CN201711268733A CN107886921B CN 107886921 B CN107886921 B CN 107886921B CN 201711268733 A CN201711268733 A CN 201711268733A CN 107886921 B CN107886921 B CN 107886921B
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pins
gray scale
pole
pairs
throw switch
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CN107886921A (en
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黎云涛
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TCL Huaxing Photoelectric Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3696Generation of voltages supplied to electrode drivers
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0271Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction

Abstract

The invention provides a source electrode driver, which comprises an integrated circuit and a switch combination with six-out-of-ten functions, wherein the integrated circuit comprises three pairs of pins for binding low gray-scale voltage, one pair of pins for binding high gray-scale voltage, five pairs of pins for binding medium gray-scale voltage and pins for receiving high and low level signals; the three pairs of pins with low gray scales and the one pair of pins with high gray scales are respectively directly connected with eight of the fourteen pins with P-Gamma; the switch combination is connected with five pairs of pins of the middle gray scale and the remaining six pins of the P-Gamma, and the switch combination performs ten-out-of-six output according to the level change condition of the pins receiving the high and low level signals, so that three pairs of the five pairs of pins of the middle gray scale are electrically connected with the remaining six pins of the P-Gamma. The invention can realize the flexible binding of a plurality of groups of gray scale voltages of the source driver on the fixed Gamma voltage quantity output by the existing P-Gamma integrated circuit, enhance the universality of the source driver and shorten the binding time.

Description

Source driver, method for realizing multi-gray-scale binding voltage combination thereof and driving circuit
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a source driver, a method for realizing multi-gray-scale binding voltage combination and a driving circuit thereof.
Background
On one hand, the electro-optic characteristics of red, green and blue of the liquid crystal display are different, so that the color difference of each gray scale is large, the color of each gray scale needs to be corrected, particularly, the gray scale error of a dark field is very obvious, and the color error of each gray scale cannot be eliminated through white balance adjustment, so that the color temperature can be adjusted to meet the preset requirement through white balance adjustment of a bright dark field only after the colors of each gray scale are consistent. On the other hand, the lighting value of the liquid crystal display is relatively high, and in order to increase the transmittance lighting value of the liquid crystal display and to better express colors, it is necessary to perform nonlinear correction on the lighting value of the liquid crystal display. Therefore, the gray scales of the dark field are obviously improved by performing gamma correction on the liquid crystal display, the color error of each gray scale is obviously reduced, the details of the color of the dark field are clear, the colors of the image lightening values are consistent, the transparent lightening values are good, and the contrast is obvious.
In the prior art, a P-Gamma integrated circuit is usually used to generate Gamma voltages, and the generated Gamma voltages are sent to a source driver to implement non-linear correction of each gray level color and its lighting value of the liquid crystal display. As shown in fig. 1, 14 sets of Gamma voltages generated by the P-Gamma integrated circuit currently can only be connected to 14 corresponding Gamma voltage pins in 18 gray level binding voltages on the source driver, and once the connection is selected, if the optical application to the liquid crystal display needs to be changed, the binding position of the pin corresponding to the Gamma voltage output by the P-Gamma integrated circuit on the source driver needs to be changed, and further the routing output mode of the PCB needs to be changed, which not only results in a long change period, but also results in poor versatility of the source driver.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a source driver, a method for implementing multi-gray-scale binding voltage combination thereof, and a driving circuit, which can implement flexible binding of multiple groups of gray-scale voltages of the source driver on the fixed Gamma voltage quantity output by the existing P-Gamma integrated circuit, thereby not only enhancing the versatility of the source driver, but also shortening the binding time.
In order to solve the above technical problem, an embodiment of the present invention provides a source driver, which is matched with a P-Gamma integrated circuit that outputs fourteen sets of Gamma voltages with fourteen pins, wherein the source driver includes an integrated circuit and a switch combination connected to the integrated circuit and having six-out-of-ten functions; wherein the content of the first and second substances,
the integrated circuit comprises three pairs of pins, a pair of pins, five pairs of pins and pins, wherein the three pairs of pins are used for binding that the gray scale value output by the low gray scale voltage is smaller than a first threshold value, the pair of pins are used for binding that the gray scale value output by the high gray scale voltage is larger than a second threshold value, the five pairs of pins are used for binding that the gray scale value output by the medium gray scale voltage is positioned between the first threshold value and the second threshold value, and the pins are used for receiving high and low level signals; the three pairs of pins for binding the low gray scale voltage and the pair of pins for binding the high gray scale voltage are respectively and correspondingly connected with eight pins of fourteen pins of the P-Gamma integrated circuit in a direct connection mode to realize electric connection;
the switch combination is provided with ten output ends which are correspondingly connected with the five pairs of pins for binding the middle gray-scale voltage respectively, and six input ends which are correspondingly connected with the remaining six pins of the fourteen pins of the P-Gamma integrated circuit respectively, and the switch combination can realize the automatic switching of six-out-of-ten output according to the level signals received by the pins for receiving the high and low level signals, so that the corresponding three pairs of the five pairs of pins for binding the middle gray-scale voltage are respectively and correspondingly electrically connected with the remaining six pins of the fourteen pins of the P-Gamma integrated circuit.
Wherein the switch combination comprises a first single-pole-three-throw switch, a second single-pole-three-throw switch, a third single-pole-three-throw switch, a fourth single-pole-three-throw switch, a fifth single-pole-three-throw switch, and a sixth single-pole-three-throw switch; wherein the content of the first and second substances,
the first single-pole three-throw switch, the second single-pole three-throw switch and the third single-pole three-throw switch are connected with three of the remaining six pins of the fourteen pins of the P-Gamma integrated circuit and correspondingly connected with three of the five pairs of pins for binding the middle-gray-scale voltage;
the fourth single-pole three-throw switch, the fifth single-pole three-throw switch and the sixth single-pole three-throw switch are connected with the other three pins of the rest six pins of the fourteen pins of the P-Gamma integrated circuit and correspondingly connected with the other three pins of the five pairs of pins for binding the middle gray level voltage;
the first single-pole-three-throw switch, the fourth single-pole-three-throw switch, the second single-pole-three-throw switch, the fifth single-pole-three-throw switch, the third single-pole-three-throw switch and the sixth single-pole-three-throw switch form pairwise matching combinations, the three pairs of matching combinations can carry out output switching according to the level change condition of signals received by the pair of pins for receiving external high and low level signals, and accordingly, the purpose that the corresponding three pairs of the five pairs of pins for binding the middle-gray-level voltage are electrically connected with the remaining six pins of the fourteen pins of the P-Gamma integrated circuit is achieved.
The pins for receiving the high and low level signals are a pair, and the received level signal combination comprises 00, 01, 10 and 11
When the level signals are combined to 00, the first single-pole three-throw switch and the fourth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the second pins after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in sequence from small to large, the second single-pole three-throw switch and the fifth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the fourth pins after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in sequence from small to large, and the third single-pole three-throw switch and the sixth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the maximum pins after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in sequence from small to large;
when the level signals are combined to 11, the first single-pole three-throw switch and the fourth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the smallest after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, the second single-pole three-throw switch and the fifth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the third after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, and the third single-pole three-throw switch and the sixth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the largest after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order;
when the level signals are combined to be 01, the first single-pole three-throw switch and the fourth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the smallest after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, the second single-pole three-throw switch and the fifth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the third after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, and the third single-pole three-throw switch and the sixth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the fourth after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order;
when the level signals are combined to 10, the first single-pole three-throw switch and the fourth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins, which are the second pins after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, the second single-pole three-throw switch and the fifth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins, which are the third pins after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, and the third single-pole three-throw switch and the sixth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins, which are the fourth pins after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order.
The invention also provides a method for realizing multi-gray-scale binding voltage combination by using the source driver, which is realized on the source driver, and the method comprises the following steps:
determining three low gray scale voltages output by three pairs of pins for binding the low gray scale voltages on the source driver and one high gray scale voltage output by one pair of pins for binding the high gray scale voltages;
according to the level signals received by pins used for receiving high and low level signals on the source driver, combining ten-out-of-six outputs of a switch on the source driver to determine three middle gray scale voltages of three selected pairs of outputs among five pairs of pins used for binding the middle gray scale voltages on the source driver;
and combining and outputting the determined three low gray scale voltages, three middle gray scale voltages and one high gray scale voltage.
The pins for receiving the high and low level signals are a pair, and the received level signal combination comprises 00, 01, 10 and 11.
Wherein, the step of determining three middle gray scale voltages of three selected pairs of outputs among five pairs of pins used for binding the middle gray scale voltages on the source driver by combining six-out-of-ten outputs of a switch on the source driver according to the level change condition of the signal received by the pin used for receiving the high and low level signals on the source driver specifically includes:
when the level signals are combined to 00, determining that the gray scale values of the five middle gray scale voltages output by the three pairs of selected middle gray scale voltages in the five pairs of pins used for binding the middle gray scale voltages on the source driver are three of the second, fourth and maximum gray scale values after being arranged from small to large;
when the combination of the level signals is 11, determining that three middle gray scale voltages output by three pairs selected from five pairs of pins used for binding the middle gray scale voltages on the source driver are three of the minimum, the third and the maximum after being arranged in sequence from small to large;
when the level signals are combined to be 01, determining that three middle gray scale voltages output by three pairs selected from five pairs of pins used for binding the middle gray scale voltages on the source driver are three of the five middle gray scale voltages output by the three pairs, namely the minimum, the third and the fourth gray scale values are arranged in the descending order;
and when the combination of the level signals is 10, determining that the gray scale values of the five middle gray scale voltages output by the three pairs of selected five pins used for binding the middle gray scale voltages on the source driver are three of the second middle gray scale voltage, the third middle gray scale voltage and the fourth middle gray scale voltage in the order from small to large.
The embodiment of the invention also provides a driving circuit which comprises the source driver.
The embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the source driver controls the switching state of the added six-out-of-ten switch combination by starting pins for receiving high and low level signals and receiving the level signals of the high and low level signal pins, so that three corresponding pairs of five pairs of pins for binding gray scale voltages in the source driver are flexibly connected with six pins of a P-Gamma integrated circuit to realize electric connection without changing the routing output mode of a PCB (printed circuit board), thereby realizing flexible binding of multiple groups of gray scale voltages of the source driver on the fixed Gamma voltage output by the existing P-Gamma integrated circuit, enhancing the universality of the source driver and simultaneously shortening the binding time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.
FIG. 1 is a schematic diagram of a source driver and a P-Gamma IC according to the prior art;
FIG. 2 is a schematic diagram of a source driver and a P-Gamma IC according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another connection between a source driver and a P-Gamma IC according to an embodiment of the invention;
FIG. 4 is a flowchart illustrating a method for implementing multi-gray-scale binding voltage combination by the source driver according to an embodiment of the invention;
in the figure, G1-G14 are fourteen pins of a P-Gamma integrated circuit respectively, J1-J18 are eighteen pins for binding gray scale voltages of a source driver, wherein J1 and J10, J2 and J11, J3 and J12 are three pairs of low gray scale voltage binding pins, J4 and J13, J5 and J14, J6 and J15, J7 and J16, J8 and J17 are five pairs of gray scale voltage binding pins, J9 and J18 are a pair of high gray scale voltage binding pins, K is a switch combination, and L1-L6 are first to sixth single-pole three-throw switches in the switch combination respectively.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 2 and 3, a source driver according to a first embodiment of the present invention is provided, which is coupled to a P-Gamma integrated circuit for outputting fourteen sets of Gamma voltages corresponding to fourteen pins (G1-G14), the source driver includes an integrated circuit L and a switch combination K connected to the integrated circuit and having six out of ten functions,
the integrated circuit comprises three pairs of pins (J and J ) for binding gray-scale values output by low gray-scale voltages and smaller than a first threshold, a pair of pins (J and J) for binding gray-scale values output by high gray-scale voltages and larger than a second threshold, five pairs of pins (J and J ) for binding gray-scale values output by middle gray-scale voltages and located between the first threshold and the second threshold, pins (J and/or J, even three or four) for receiving high and low level signals, and a switch combination K with six-out-of-ten functions, wherein the three pairs of pins (J and J ) for binding the low gray-scale voltages and the pair of pins (J and J) for binding the high gray-scale voltages are respectively and directly connected with eight pins (G, G-G, G) of the fourteen pins (G-G) of the P-Gamma integrated circuit;
the switch combination K has ten outputs respectively connected with five pairs of pins (J4 and J13, J5 and J14, J14 and J14) for binding intermediate gray scale voltage, and has six inputs respectively connected with the rest six pins (G14-G14) of fourteen pins (G14-G14) of the P-Gamma integrated circuit, and the switch combination K automatically switches the ten-selected six outputs according to the level signals received by the pins (J14 and/or J14, even three or four) for receiving high and low level signals, so that the five pairs of pins J14 and J14, J14 and J14 for centering gray scale voltage, three pairs of the corresponding pins (J14) of the P-Gamma integrated circuit are respectively connected with the rest six pins (G14-G14 and J14) of the P-Gamma integrated circuit, G11-G13) to make electrical connection.
It should be noted that the gray scale value outputted by each gray scale voltage of the source driver is the RGB pixel brightness for lighting the lcd panel, and can be divided into 0-255. The gray scale voltage having an output gray scale value smaller than the first threshold value (e.g., 50) is divided into a low gray scale voltage, i.e., a gray scale voltage having a gray scale value <50, the gray scale voltage having an output gray scale value larger than the second threshold value (e.g., 254) is divided into a high gray scale voltage, i.e., a gray scale voltage having a gray scale value of 255, and the gray scale voltage having an output gray scale value between the first threshold value (e.g., 50) and the second threshold value (e.g., 254) is divided into a medium gray scale voltage, i.e., a gray scale voltage having a gray scale value between [50, 254 ].
It should be noted that the source driver receives the Gamma voltages of the P-Gamma integrated circuit 14 group, and divides the pins connected with the Gamma voltages larger than 8v into positive pins, and divides the pins smaller than 8v into negative pins, and the binding output of the gray scale voltages is realized through the paired positive pins and negative pins.
It should be noted that the level signals for receiving the signals received by the high and low level signal pins are respectively derived from clock signals, and may also be obtained by performing signal shunt output by an internal control circuit; for example, there are a pair of pins J19 and J20 receiving signals whose level signals are derived from two external clock signals, respectively.
In the embodiment of the invention, the source driver receives the external high-low level signal pin by enabling the pin, and the switching state of the added six-out-of-ten switch combination K is controlled by the enabled level signal of the pin for receiving the high and low level signals, six pins (G2-G4, G11-G13) of three pairs of P-Gamma integrated circuits are selected from five pairs of pins (J4 and J13, J5 and J14, J6 and J15, J7 and J16, J8 and J17) used for binding gray scale voltages in the source driver to realize electric connection after flexible connection, the wiring output mode of a PCB circuit board does not need to be changed, therefore, the flexible binding of multiple groups of gray scale voltages of the source electrode driver is realized on the fixed Gamma voltage quantity output by the existing P-Gamma integrated circuit, the universality of the source electrode driver is enhanced, and the binding time can be shortened.
In the embodiment of the invention, the switch combination K has various structures.
As shown in fig. 2, the switch combination K may be a terminal block structure having six input terminals and ten output terminals, and the six input terminals are connected to the ten output terminals by controlling the electrical characteristics.
Of course, as shown in fig. 3, the switch combination K may also include a first single-pole-three-throw switch L1, a second single-pole-three-throw switch L2, a third single-pole-three-throw switch L3, a fourth single-pole-three-throw switch L4, a fifth single-pole-three-throw switch L5, and a sixth single-pole-three-throw switch L6, wherein,
the first single-pole-three-throw switch L1, the second single-pole-three-throw switch L2 and the third single-pole-three-throw switch L3 are connected with three (G2-G4) of the remaining six (G2-G4, G11-G13) pins of fourteen (G1-G14) pins of the P-Gamma integrated circuit and three (J4, J5, J6, J7 and J8) pins of five pairs of pins (J4, J13, J5, J14, J6, J15, J7, J16, J8 and J17) for binding middle-gray-level voltage are selected to be connected correspondingly;
the fourth single-pole-three-throw switch L4, the fifth single-pole-three-throw switch L5 and the sixth single-pole-three-throw switch L6 are connected with the other three (G11-G13) of the remaining six (G2-G4, G11-G13) pins of fourteen pins (G1-G14) of the P-Gamma integrated circuit and are connected with the other five pairs of pins (J4 and J13, J5 and J14, J6 and J15, J7 and J16, J8 and J17) for binding middle gray-scale voltage, and three pairs of pins (J13, J14, J15, J16 and J17) are selected to be connected correspondingly;
the first single-pole-three-throw switch L1 and the fourth single-pole-three-throw switch L4, the second single-pole-three-throw switch L2 and the fifth single-pole-three-throw switch L5, and the third single-pole-three-throw switch L3 and the sixth single-pole-three-throw switch L6 form pairwise pairing combination, and the three pairing combination can carry out output switching according to the level change of signals received by a pair of pins (J19 and J20) for receiving external high-low level signals, so that the remaining six pins (G2-G4, G11-G13) of the five pairs of pins (J4 and J13, J5 and J14, J6 and J15, J7 and J16, J8 and J17) for binding intermediate gray-level voltage and fourteen pins (G1-G14) of the P-Gamma integrated circuit are electrically connected.
In one embodiment, a first single-pole-three-throw switch L has an input connected to a pin (G2) of a P-Gamma integrated circuit, three outputs connected to three pins (J5 and J6) of a source driver, respectively, a second single-pole-three-throw switch L has an input connected to a pin (G3) of the P-Gamma integrated circuit, three outputs connected to three pins (J5, J6 and J7) of the source driver, respectively, a third single-pole-three-throw switch 7 has an input connected to a pin (G7) of the P-Gamma integrated circuit, three outputs connected to three pins (J7, J7 and J7) of the source driver, an input of a fourth single-pole-three-throw switch 7 is connected to a pin (G7) of the P-Gamma integrated circuit, three outputs connected to three pins (J7, J7 and J7) of the source driver, a fifth single-pole-three pins (J7, J7) of the P-Gamma integrated circuit, J7, J366, and a sixth input of the P-Gamma integrated circuit, 7, and three input of the P-Gamma integrated circuit 7, respectively.
In the embodiment of the present invention, there is a pair of pins (J19 and J20) for receiving high and low level signals, wherein J19 is the first signal receiving pin and J20 is the second signal receiving pin, and the received level signals are combined into four kinds, such as all low level signals, which are represented as 00; are both high, denoted 11; a high level and a low level, denoted as 01 or 10.
According to the four combination situations of the level signals, taking the switch combination K with six single-pole-three-throw switches as an example, the detailed description will be given of the case that the first single-pole-three-throw switch L1, the second single-pole-three-throw switch L2, the third single-pole-three-throw switch L3, the fourth single-pole-three-throw switch L4, the fifth single-pole-three-throw switch L5 and the sixth single-pole-three-throw switch L6 in the switch combination K are correspondingly switched to different pins of the source driver and output corresponding gray-scale values, for convenience of description, the gray-scale values output by the middle gray-scale voltage of the source driver are bound according to the corresponding pins after being sorted from small to large, and the specific description is as follows:
(1) the level signal combination is 00, that is, when the levels of the signals received by the first signal receiving pin J19 and the second signal receiving pin J20 for receiving the high and low level signals are both low level;
the gray level values output from the first single-pole-three-throw switch L1 and the fourth single-pole-three-throw switch L4 in the paired combination are simultaneously switched to the second two pins (J5 and J14) in the order from small to large among the five pairs of pins (J4 and J13, J5 and J14, J6 and J15, J7 and J16, J8 and J17) for binding gray level voltages, and the gray level values output from the second single-pole-three-throw switch L2 and the fifth single-pole-three-throw switch L5 in the paired combination are simultaneously switched to the fifth pair of pins (J L and J L ) for binding intermediate gray level voltages, and the gray level values output from small to large among the fourth two pins (J L and J72) in the paired combination, and the sixth pair of switches L and L are simultaneously switched to the maximum gray level values output from the third pair of pins (J L, J L and J L) in the order from small to large among the paired switches L, J L and the third single-pole-three-pole-three-throw switches L and the third switch L.
(2) The level signal combination is 11, that is, when the level of the signal received by the first signal receiving pin J19 and the second signal receiving pin J20 for receiving the high-low level signal is high level;
the first single-pole-three-throw switch L1 and the fourth single-pole-three-throw switch L4 in the paired combination are simultaneously switched to the two pins (J4 and J13) which are the smallest gray-scale values after being arranged from small to large in order among the five pairs of pins (J4 and J13, J5 and J14, J6 and J15, J7 and J16, J8 and J17) for binding gray-scale voltages, and the second single-pole-three-throw switch L2 and the fifth single-pole-three-throw switch L5 in the paired combination are simultaneously switched to the five pairs of pins (J L and J L ) which are the third gray-scale values after being arranged from small to large in order among the five pairs of pins (J L and J L) for binding the middle gray-scale voltages, and the gray-scale values after being arranged from small to large in order among the three pairs of pins (J L and J L ) and the third single-pole-three-pole-throw switches L and the maximum gray-pole-three-throw switches L and L in the paired combination (J L) for binding the three-pole-three switches L, J L and the maximum gray-pole-three-pole-three switches.
(3) The level signal combination is 01, that is, when the level of the signal received by the first signal receiving pin J19 for receiving the high-low level signal is low level and the level of the signal received by the second signal receiving pin J20 is low-high level;
the first single-pole-three-throw switch L1 and the fourth single-pole-three-throw switch L4 in the paired combination are simultaneously switched to the two pins (J4 and J13) which are the smallest gray-scale values after being arranged from small to large in order among the five pairs of pins (J4 and J13, J5 and J14, J6 and J15, J7 and J16, J8 and J17) for binding gray-scale voltages, and the second single-pole-three-throw switch L2 and the fifth single-pole-three-throw switch L5 in the paired combination are simultaneously switched to the five pairs of pins (J L and J L ) for binding intermediate gray-scale voltages, and the gray-scale values output from small to large in order among the five pairs of pins (J L and J L) for binding intermediate gray-scale voltages are simultaneously switched to the three pairs of pins (J L and J L ) for binding the third gray-pole-scale values after being arranged from small to the three pairs of switches L, J L and J L, and the fourth single-pole-three switches L are simultaneously switched to the fourth single-pole-three switches L and J L and L for binding gray-pole-three switches (J L) among the five pairs of the paired switches L, J L and the three pairs of the three switches L and the.
(4) The level signal combination is 10, that is, when the level of the signal received by the first signal receiving pin J19 for receiving the high and low level signals is high level and the level of the signal received by the second signal receiving pin J20 is low and high level;
the gray level values output from the first single-pole-three-throw switch L1 and the fourth single-pole-three-throw switch L4 in the paired combination are simultaneously switched to the second two pins (J5 and J14) in the order from small to large among the five pairs of pins (J4 and J13, J5 and J14, J6 and J15, J7 and J16, J8 and J17) for binding gray level voltages, and the gray level values output from the second single-pole-three-throw switch L2 and the fifth single-pole-three-throw switch L5 in the paired combination are simultaneously switched to the fifth pair of pins (J L and J L ) for binding intermediate gray level voltages, and the gray level values output from small to large among the third two pins (J L and J L) in the paired combination, and the sixth pair of switches L and L are simultaneously switched to the fourth single-pole-three-throw switch L and J L and the fourth single-pole-three-throw switch L and L are simultaneously switched to the third gray level voltages (J L, J L and the paired combination are simultaneously switched to the fourth single-pole-three-pole-switch L and the fourth single-switch L.
In one embodiment, the gray scale values output by the three pairs of pins (J1 and J10, J2 and J11, J3 and J12) for binding the low gray scale voltage are 0, 1 and 31 respectively; wherein, the gray scale value corresponding to the stitch (J1 and J10) is 0, the gray scale value corresponding to the stitch (J2 and J11) is 1, and the gray scale value corresponding to the stitch (J3 and J12) is 31;
the gray value output by a pair of pins (J9 and J18) for binding the high gray voltage is 255;
the gray level values output by five pairs of pins (J4 and J13, J5 and J14, J6 and J15, J7 and J16, J8 and J17) for binding the middle gray level voltage are respectively 63, 127, 191, 223 and 254 after being sorted from small to large; the gray scale value corresponding to the stitch (J4 and J13) is 63, the gray scale value corresponding to the stitch (J5 and J14) is 127, the gray scale value corresponding to the stitch (J6 and J15) is 191, the gray scale value corresponding to the stitch (J7 and J16) is 223, and the gray scale value corresponding to the stitch (J8 and J17) is 254.
When J19 and J20 are 00, the first single-pole three-throw switch L1 is switched to the pin of the source driver (J5) and the fourth single-pole three-throw switch L4 is switched to the pin of the source driver (J14) so that the gray-scale value is 127, the second single-pole three-throw switch L2 is switched to the pin of the source driver (J7) and the fifth single-pole three-throw switch L5 is switched to the pin of the source driver (J16) so that the gray-scale value is 223, the third single-pole three-throw switch L3 is switched to the pin of the source driver (J8) and the sixth single-pole three-throw switch L6 is switched to the pin of the source driver (J17) so that the gray-scale value is 254, when the tie point combination of the source driver is 0, 1, 31, 223, 254, 255;
when J19 and J20 are 11, the first single-pole-three-throw switch L1 is switched to the pin of the source driver (J4) and the fourth single-pole-three-throw switch L4 is switched to the pin of the source driver (J13) so that the gray-scale value is 63, the second single-pole-three-throw switch L2 is switched to the pin of the source driver (J6) and the fifth single-pole-three-throw switch L5 is switched to the pin of the source driver (J15) so that the gray-scale value is 191, the third single-pole-three-throw switch L3 is switched to the pin of the source driver (J8) and the sixth single-pole-three-throw switch L6 26 6 is switched to the pin of the source driver (J17) so that the gray-scale value is 254, when the tie point combination of the source driver is 0, 1, 31, 63, 191, 254, 255;
when J19 and J20 are 01, the first single-pole-three-throw switch L1 is switched to the pin of the source driver (J4) and the fourth single-pole-three-throw switch L4 is switched to the pin of the source driver (J13) so that the gray-scale value is 63, the second single-pole-three-throw switch L2 is switched to the pin of the source driver (J6) and the fifth single-pole-three-throw switch L5 is switched to the pin of the source driver (J15) so that the gray-scale value is 191, the third single-pole-three-throw switch L3 is switched to the pin of the source driver (J7) and the sixth single-pole-three-throw switch L6 is switched to the pin of the source driver (J16) so that the gray-scale value is 223, and the binding point combination of the source driver is 0, 1, 31, 63, 191, 223, 255;
when J19 and J20 are 10, the first single-pole-three-throw switch L1 is switched to the pin of the source driver (J5) and the fourth single-pole-three-throw switch L4 is switched to the pin of the source driver (J14) so that the gray-scale value is 127, the second single-pole-three-throw switch L2 is switched to the pin of the source driver (J6) and the fifth single-pole-three-throw switch L5 is switched to the pin of the source driver (J15) so that the gray-scale value is 191, the third single-pole-three-throw switch L3 is switched to the pin of the source driver (J7) and the sixth single-pole-three-throw switch L6 is switched to the pin of the source driver (J16) so that the gray-scale value is 223, and the binding point combination of the source driver is 0, 1, 31, 63, 191, 223, 255;
in summary, the binding combination relationship of the source driver can be illustrated by the following table 1:
TABLE 1
Corresponding to the source driver in the first embodiment of the present invention, a second embodiment of the present invention further provides a method for implementing a multi-gray-scale binding voltage combination by using the source driver, which is implemented on the source driver in the first embodiment of the present invention, and the method includes the following steps:
step S1, determining three low gray scale voltages output by three pairs of pins used for binding the low gray scale voltages on the source driver and one high gray scale voltage output by one pair of pins used for binding the high gray scale voltages;
specifically, three low grayscale voltages of 0, 1, 31 are output, and one high grayscale voltage of 255 is output.
Step S2, according to the level signal received by the pin on the source driver for receiving the high and low level signal, implementing six out of ten outputs of the switch combination on the source driver to determine three middle gray scale voltages of three selected outputs among five pairs of pins on the source driver for binding the middle gray scale voltages;
the specific process is that the combination is carried out according to the level signals received by the pins for receiving the high and low level signals, and three pairs of middle gray scale voltages are selected from five pairs of pins for binding the middle gray scale voltages to output three middle gray scale voltages.
The free combination of three middle gray scale voltages will be described in detail by taking the received level signal as an example when the pins for receiving the high and low level signals are a pair. Since the received level signal combination includes 00, 01, 10, and 11, the following specific analysis is performed:
(1) when the received level signals are combined to 00, namely when pins used for receiving high-low level signals on the source driver comprise a first signal receiving pin and a second signal receiving pin, wherein the received signal levels are low levels, three middle gray scale voltages which are determined to be output are three middle gray scale voltages which are the second, the fourth and the largest after being arranged in sequence from small to large; the output three middle gray scale voltages are 127, 223 and 254.
(2) When the received level signal combination is 11, namely when the pins for receiving the high and low level signals on the source driver comprise a first signal receiving pin and a second signal receiving pin, the received signal levels of which are high levels, three output middle gray scale voltages are determined as three minimum, third and maximum gray scale values of the five output middle gray scale voltages which are arranged from small to large; the output three middle gray scale voltages at this time are 63, 191 and 254.
(3) When the received level signals are combined to 01, that is: when the pins for receiving the high-level and low-level signals on the source driver comprise a first signal receiving pin with the low level of the received signal and a second signal receiving pin with the high level of the received signal, determining that three output middle gray scale voltages are three of the five output middle gray scale voltages which are the smallest, third and fourth gray scale values after being arranged from small to large; the three middle gray scale voltages are output at this time as 63, 191 and 223.
(4) When the received level signal combination is 10, namely when pins for receiving high and low level signals on the source driver comprise a first signal receiving pin with the received signal level being high level and a second signal receiving pin with the received signal level being low level, determining that three output middle gray scale voltages are three of a second middle gray scale voltage, a third middle gray scale voltage and a fourth middle gray scale voltage which are arranged in sequence from small to large; the output three middle gray scale voltages are 127, 191 and 223.
And step S3, combining and outputting the determined three low gray scale voltages, three middle gray scale voltages and one high gray scale voltage.
The specific process is to combine and output the three freely combined middle gray scale voltages, the three freely combined low gray scale voltages and the high gray scale voltage.
Corresponding to the source driver in the first embodiment of the present invention, a third embodiment of the present invention further provides a driving circuit, which includes the source driver in the first embodiment of the present invention, and has the same structure and connection relationship as the source driver in the first embodiment of the present invention, so please refer to the related contents in the first embodiment of the present invention specifically, and details are not repeated here.
The embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the source driver controls the switching state of the added six-out-of-ten switch combination by starting at least one pin for receiving high and low level signals and controlling the switching state of the added six-out-of-ten switch combination according to the level change condition of the started pin for receiving the high and low level signals, so that three corresponding pairs of five pairs of pins for binding gray scale voltages in the source driver are flexibly connected with six pins of a P-Gamma integrated circuit to realize electric connection without changing the routing output mode of a PCB (printed circuit board), thereby realizing flexible binding of multiple groups of gray scale voltages of the source driver on the fixed Gamma voltage quantity output by the existing P-Gamma integrated circuit, enhancing the universality of the source driver and simultaneously shortening the binding time.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (8)

1. A source driver, it cooperates with P-Gamma integrated circuit that outputs fourteen groups of Gamma voltages with fourteen pins, characterized by that, the said source driver includes the integrated circuit and switches combination with the said integrated circuit connection and with ten select six functions; wherein the content of the first and second substances,
the integrated circuit comprises three pairs of pins, a pair of pins, five pairs of pins and pins, wherein the three pairs of pins are used for binding that the gray scale value output by the low gray scale voltage is smaller than a first threshold value, the pair of pins are used for binding that the gray scale value output by the high gray scale voltage is larger than a second threshold value, the five pairs of pins are used for binding that the gray scale value output by the medium gray scale voltage is positioned between the first threshold value and the second threshold value, and the pins are used for receiving high and low level signals; the three pairs of pins for binding the low gray scale voltage and the pair of pins for binding the high gray scale voltage are respectively and correspondingly connected with eight pins of fourteen pins of the P-Gamma integrated circuit in a direct connection mode to realize electric connection;
the switch combination is provided with ten output ends which are correspondingly connected with the five pairs of pins for binding the middle gray-scale voltage respectively, and six input ends which are correspondingly connected with the remaining six pins of the fourteen pins of the P-Gamma integrated circuit respectively, and the switch combination can realize the automatic switching of six-out-of-ten output according to the level signals received by the pins for receiving the high and low level signals, so that the corresponding three pairs of the five pairs of pins for binding the middle gray-scale voltage are respectively and correspondingly electrically connected with the remaining six pins of the fourteen pins of the P-Gamma integrated circuit.
2. The source driver of claim 1, wherein the switch combination comprises a first single-pole-three-throw switch, a second single-pole-three-throw switch, a third single-pole-three-throw switch, a fourth single-pole-three-throw switch, a fifth single-pole-three-throw switch, and a sixth single-pole-three-throw switch; wherein the content of the first and second substances,
the first single-pole three-throw switch, the second single-pole three-throw switch and the third single-pole three-throw switch are connected with three of the remaining six pins of the fourteen pins of the P-Gamma integrated circuit and correspondingly connected with three of the five pairs of pins for binding the middle-gray-scale voltage;
the fourth single-pole three-throw switch, the fifth single-pole three-throw switch and the sixth single-pole three-throw switch are connected with the other three pins of the rest six pins of the fourteen pins of the P-Gamma integrated circuit and correspondingly connected with the other three pins of the five pairs of pins for binding the middle gray level voltage;
the first single-pole-three-throw switch, the fourth single-pole-three-throw switch, the second single-pole-three-throw switch, the fifth single-pole-three-throw switch, the third single-pole-three-throw switch and the sixth single-pole-three-throw switch form pairwise matching combinations, the three pairs of matching combinations can carry out output switching according to level signals received by pins for receiving high and low level signals, and accordingly, the electrical connection between three corresponding pairs of five pairs of pins for binding middle-level gray-scale voltage and the remaining six pins among fourteen pins of the P-Gamma integrated circuit is achieved.
3. The source driver as claimed in claim 1 or 2, wherein the pins for receiving high and low level signals are a pair, and the received level signal combination comprises 00, 01, 10, 11.
4. The source driver of claim 3, wherein when the combination of level signals is 00, the first single-pole three-throw switch and the fourth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are arranged from small to large and then are the second pins among the five pairs of pins for binding the middle gray scale voltage, the second single-pole three-throw switch and the fifth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are arranged from small to large and then are the fourth pins among the five pairs of pins for binding the middle gray scale voltage, the third single-pole three-throw switch and the sixth single-pole three-throw switch in the pairing combination are simultaneously switched to the two pins with the largest gray scale values output by the five pairs of pins for binding the middle gray scale voltage after being arranged in sequence from small to large; when the level signals are combined to 11, the first single-pole three-throw switch and the fourth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the smallest after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, the second single-pole three-throw switch and the fifth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the third after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, and the third single-pole three-throw switch and the sixth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the largest after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order;
when the level signals are combined to be 01, the first single-pole three-throw switch and the fourth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the smallest after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, the second single-pole three-throw switch and the fifth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the third after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, and the third single-pole three-throw switch and the sixth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins which are the fourth after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order; when the level signals are combined to 10, the first single-pole three-throw switch and the fourth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins, which are the second pins after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, the second single-pole three-throw switch and the fifth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins, which are the third pins after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order, and the third single-pole three-throw switch and the sixth single-pole three-throw switch in the pairing combination are simultaneously switched to two pins, which are the fourth pins after the gray scale values output by the five pairs of pins for binding the middle gray scale voltage are arranged in a descending order.
5. A method for a source driver to implement multi-gray level binding voltage combination, which is implemented on the source driver as claimed in any one of claims 1 to 4, the method comprising the steps of:
determining three low gray scale voltages output by three pairs of pins for binding the low gray scale voltages on the source driver and one high gray scale voltage output by one pair of pins for binding the high gray scale voltages;
according to the level signals received by pins used for receiving high and low level signals on the source driver, combining ten-out-of-six outputs of a switch on the source driver to determine three middle gray scale voltages of three selected pairs of outputs among five pairs of pins used for binding the middle gray scale voltages on the source driver;
and combining and outputting the determined three low gray scale voltages, three middle gray scale voltages and one high gray scale voltage.
6. The method of claim 5, wherein the pins for receiving the high and low level signals are a pair, and the combination of the received level signals comprises 00, 01, 10, 11.
7. The method for source driver implementation of multi-gray-scale binding voltage combination as claimed in claim 6, wherein said step of implementing six out of ten switch combinations on said source driver to determine three middle gray-scale voltages of selected three pairs of outputs among five pairs of pins on said source driver for binding middle gray-scale voltages according to the level signals received by the pins on said source driver for receiving high and low level signals specifically comprises:
when the level signals are combined to 00, determining that the gray scale values of the five middle gray scale voltages output by the three pairs of selected middle gray scale voltages in the five pairs of pins used for binding the middle gray scale voltages on the source driver are three of the second, fourth and maximum gray scale values after being arranged from small to large;
when the combination of the level signals is 11, determining that three middle gray scale voltages output by three pairs selected from five pairs of pins used for binding the middle gray scale voltages on the source driver are three of the minimum, the third and the maximum after being arranged in sequence from small to large;
when the level signals are combined to be 01, determining that three middle gray scale voltages output by three pairs selected from five pairs of pins used for binding the middle gray scale voltages on the source driver are three of the five middle gray scale voltages output by the three pairs, namely the minimum, the third and the fourth gray scale values are arranged in the descending order;
and when the combination of the level signals is 10, determining that the gray scale values of the five middle gray scale voltages output by the three pairs of selected five pins used for binding the middle gray scale voltages on the source driver are three of the second middle gray scale voltage, the third middle gray scale voltage and the fourth middle gray scale voltage in the order from small to large.
8. A driving circuit comprising the source driver according to any one of claims 1 to 4.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102081896A (en) * 2009-11-26 2011-06-01 奇景光电股份有限公司 Source electrode driver, display unit and method for driving display panel
CN104091575A (en) * 2014-06-26 2014-10-08 京东方科技集团股份有限公司 Gamma voltage generating circuit, generating method and data driver
US20150279301A1 (en) * 2014-03-27 2015-10-01 Boe Technology Group Co., Ltd. Device and method for adjusting gamma voltage
CN106023930A (en) * 2016-07-20 2016-10-12 武汉华星光电技术有限公司 Gamma voltage generating circuit and driving device
CN107274850A (en) * 2017-08-11 2017-10-20 京东方科技集团股份有限公司 A kind of display driver circuit and its driving method, display device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4798753B2 (en) * 2005-02-28 2011-10-19 ルネサスエレクトロニクス株式会社 Display control circuit and display control method
CN201726313U (en) * 2010-06-02 2011-01-26 青岛海信电器股份有限公司 Voltage-boosting circuit and liquid crystal driving circuit with the same
CN102402957B (en) * 2011-11-15 2014-01-22 深圳市华星光电技术有限公司 LCD (liquid crystal display) data driven IC (integrated circuit) output compensation circuit and compensation method
CN105513529A (en) * 2016-02-23 2016-04-20 深圳市华星光电技术有限公司 Display panel drive circuit and quality test method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102081896A (en) * 2009-11-26 2011-06-01 奇景光电股份有限公司 Source electrode driver, display unit and method for driving display panel
US20150279301A1 (en) * 2014-03-27 2015-10-01 Boe Technology Group Co., Ltd. Device and method for adjusting gamma voltage
CN104091575A (en) * 2014-06-26 2014-10-08 京东方科技集团股份有限公司 Gamma voltage generating circuit, generating method and data driver
CN106023930A (en) * 2016-07-20 2016-10-12 武汉华星光电技术有限公司 Gamma voltage generating circuit and driving device
CN107274850A (en) * 2017-08-11 2017-10-20 京东方科技集团股份有限公司 A kind of display driver circuit and its driving method, display device

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