DE112005002852B4 - Passivation structure with voltage equalization loops - Google Patents

Passivation structure with voltage equalization loops

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Publication number
DE112005002852B4
DE112005002852B4 DE112005002852.6T DE112005002852T DE112005002852B4 DE 112005002852 B4 DE112005002852 B4 DE 112005002852B4 DE 112005002852 T DE112005002852 T DE 112005002852T DE 112005002852 B4 DE112005002852 B4 DE 112005002852B4
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DE
Germany
Prior art keywords
closed loop
loop
semiconductor device
passivation structure
resistance material
Prior art date
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Active
Application number
DE112005002852.6T
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German (de)
Other versions
DE112005002852T5 (en
Inventor
Niraj Ranjan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
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Infineon Technologies North America Corp
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Publication date
Priority to US10/991,167 priority Critical patent/US7183626B2/en
Priority to US10/991,167 priority
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Priority to PCT/US2005/041734 priority patent/WO2006055738A2/en
Publication of DE112005002852T5 publication Critical patent/DE112005002852T5/en
Application granted granted Critical
Publication of DE112005002852B4 publication Critical patent/DE112005002852B4/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/965Shaped junction formation

Abstract

A semiconductor device comprising:
a semiconductor body of a first conductivity type,
an active region formed in the semiconductor body and containing a region of a second conductivity type which ends in the vicinity of the outer boundary of the active region, and
a passivation structure arranged around the active area and
a continuous band of resistance material with a substantially uniform width, the continuous band crossing itself after a circumnavigation of the active area and forming a first closed loop made of a resistance material, which serves as the inner boundary of the passivation structure, a loop-forming band made of the resistance material which surrounds the first closed loop to form loops without crossing, the continuous band crossing itself a second time and forming a second closed loop of the resistive material around the first closed loop, acting as the outer boundary serves the passivation structure,
wherein the loop-forming tape extends at one end from the outer edge of the first closed loop and ends at the other end at the inner edge of the second closed loop.

Description

  • The present invention relates to a semiconductor component and in particular to a semiconductor component which has an edge passivation structure.
  • A typical semiconductor component usually has an active region that ends at a pn junction.
  • The breakdown voltage of a pn junction formed in a substrate is generally lower than its theoretical limit, since certain locations on the pn junction tend to develop stronger electric fields. The pn junction at the end edge of the active area of a component is exposed to stronger electrical fields, for example, in particular at locations with a small radius of curvature.
  • In order to reduce the intensity of the electric fields in the vicinity of the pn junction at the termination edge of the active region, high-voltage semiconductor components can have an edge passivation structure. An edge passivation structure provides a transition zone in which the strong electric fields around the active area gradually transition to the lower potential at the edge of the device. A passivation structure reduces the field strength around the termination area of a pn junction by distributing the electrical field lines over the edge passivation area.
  • US 5,382,825 A explains various passivation structures and their respective disadvantages. In order to improve the passivation structures of the prior art explained there, disclosed US 5,382,825 A a passivation structure that includes a spiral band of resistive material that is disposed around the active area of a semiconductor device so that the electric fields near the termination area of a pn junction in a semiconductor device are gradually reduced.
  • US 5,382,825 A However, the spiral band disclosed does not cross. As a result, the position of the end of the spiral band closest to the active area determines the initial tension at which the voltage drop begins around the active area. However, this initial voltage may not be representative of the strength of the electric field around the active area.
  • To balance the tension strikes US 5,382,825 A forming a field plate around the active area. The proposed width for the field plate is three times the depth of the pn junction surrounding the active area. This width would take up a large area on the surface of the chip (die) and thereby enlarge it.
  • The spiral band also has a varying width so that the resistance of the band is balanced over its length. In practice, such a tape may be difficult to manufacture with precision. As a result, the resistance along the band can vary in an unpredictable manner, resulting in fluctuations in the voltage drop rather than a smooth, almost linear voltage drop.
  • An object of the present invention is to provide a passivation structure to reduce the electrical fields around the active area of a semiconductor chip.
  • According to the present invention, a passivation structure comprises a conductive band of resistive material that crosses once and forms a first closed loop and then ends by crossing a second time and forming a second closed loop.
  • According to the present invention, the first closed loop made of an electrically conductive resistance material is arranged around the active region of a semiconductor device and serves as an inner boundary of the passivation structure, the second closed loop made of the resistance material is arranged around the first closed loop and serves as outer boundary of the passivation structure, and a loop-forming tape made of the resistive material with the same width as the inner closed loop and the outer closed loop surrounds the first closed loop without forming a loop and ends at the second closed loop.
  • The inner closed loop and the outer closed loop provide a substantially uniform tension at the ends of the loop-forming band, and since the inner closed loop and the outer closed loop are approximately the same width as the continuous band, they take up much less space Claim as the field plates proposed in the prior art.
  • According to a further embodiment of the present invention, the continuous band is doped so that it has pn junctions which ensure gradual (instead of continuous) voltage drops along the continuous band.
  • According to yet another aspect of the present invention, a conductive metal layer is deposited at least over the pn junctions in the continuous band in order to improve (reduce) its time constant RC and to reduce the overall resistance.
  • Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
  • 1 shows a plan view of a passivation structure according to the prior art.
  • 2nd shows a top view of a passivation structure according to the first embodiment of the present invention.
  • 3rd shows a top view of a passivation structure according to the second embodiment of the present invention.
  • 4th shows a top view of a passivation structure according to the third embodiment of the present invention.
  • 5 shows a top view of a passivation structure according to the fourth embodiment of the present invention.
  • 6 shows a top view of a passivation structure according to the fifth embodiment of the present invention.
  • 7 shows a along line 7 - 7 in 4th Cross-sectional view of a passivation structure running in the direction of the arrows.
  • In the first embodiment of the present invention in 2nd it is a semiconductor device 10th which is an active area 12th has that on a main surface of a semiconductor chip 14 is trained. The active area 12th may include active elements that form a particular semiconductor device, such as a power MOSFET, a power IGBT, a bipolar power device, a power diode, etc. The device 10th contains those around the active area 12th passivation structure trained around 16 . The passivation structure 16 is formed from a continuous conductive band made of resistance material such as n-doped polysilicon and has an inner closed loop 18th on that right around the active area 12th is arranged around, as well as an outer closed loop 20th that around the inner closed loop 18th is formed around and as the outer boundary of the passivation structure 16 serves. The inner closed loop 18th has a rectangular shape with rounded corners and therefore contains two pairs of straight, parallel sides, which are connected by four arches. The outer closed loop 20th has essentially the same shape as the inner closed loop. Between the inner closed loop 18th and the outer closed loop 20th is a loop-forming tape 22 Made of resistance material that is attached to the inner closed loop 18th begins and surrounds it with the formation of loops without crossing and on the outer closed loop 20th ends.
  • Any number of loops can be used depending on the total resistance desired and the resistivity of each loop.
  • The inner closed loop 18th is formed by the resistance band crossing itself once before the multiple loops of the loop-forming band 22 begin, and the outer closed loop 20th is formed by the continuous band crossing itself a second time before it ends. The two closed loops are used to equalize tension at each end of the loop-forming belt 22 what about the active area 12th enables a more uniform voltage drop around.
  • In the first embodiment of the present invention, one end is a loop-forming tape 22 with a straight side 24th the inner closed loop 18th connected and initially runs at an angle to one straight side 24th and then for its first loop parallel to the outer boundary of the inner closed loop 18th . The loop-forming tape 22 then runs with its first loop parallel to the inner closed loop 18th and ends on a straight side 26 the outer closed loop 20th . It should be noted that the loop-forming tape 22 according to an aspect of the present invention on one side of the outer closed loop 20th ends that has the same positional relationship as the inner closed loop side 18th , of which the loop-forming band 22 going out. The loop-forming tape 22 starts especially on the right straight side, for example 24th the inner closed loop 18th and ends on the right straight side 26 . As a result, the loop-forming tape covered 22 on all sides of the inner closed loop 18th essentially the same area. Like for example in 2nd can be seen, the loop-forming tape winds 22 the inner closed loop forming a loop 18th nine times.
  • Each loop of the loop-forming tape 22 is preferably at the same distance an adjacent loop, and the loop-forming ribbon 22 has essentially the same width throughout.
  • Also have the inner closed loop 18th and the outer closed loop 20th preferably the same width as the loop-forming tape 22 .
  • The second embodiment of the present invention in 3rd contains all the features of the first embodiment, only here is the loop-forming tape 22 with a corner 28 the inner closed loop 18th connected and ends at a corner 30th the outer closed loop 20th . The loop-forming tape 22 ends at a corner 30th the outer closed loop 20th that has the same positional relationship as the corner 28 the inner closed loop 18th . The loop-forming tape 22 in particular begins, for example, at the top right corner of the inner closed loop 18th and ends at the top right corner of the outer closed loop 20th . Similar to the first embodiment, the loop-forming tape follows 22 in the second embodiment then the outer contour of the inner closed loop 18th without crossing until it is on the outer closed loop 20th ends.
  • An in 4th The device shown according to the third embodiment of the present invention contains all the elements of the first and second embodiments, only the loop-forming tape 22 here with one side 30th the inner closed loop 18th connected, passes into this and then follows the outer contour of the inner closed loop 18th , gradually increasing in distance from the outer boundary of the inner closed loop 18th runs. After its first loop, the loop-forming band follows 22 their contour and gradually goes into the outer closed loop 20th about. It should be noted that the loop-forming tape 22 at one point in the outer closed loop 20th that corresponds to its position on the inner closed loop at which it begins to separate from it. The loop-forming tape 22 especially begins, for example, on the left side of the inner closed loop 18th to separate from this, and then ends by putting it in the left side of the outer closed loop 20th transforms.
  • The passivation structure 16 In a typical device according to the present invention, by depositing and doping a polysilicon layer at a desired location on the chip 14 and subsequently applying the desired structure using a photolithography step. To achieve a desired voltage drop for a 600V device, the continuous band may have a resistivity of 100 megohms, be 1.0 µm wide, and form forty-six loops, with each loop approximately 0.5 µm apart from the adjacent loops owns.
  • The passivation structure according to the present invention can be doped with dopants with a conductivity, such as n-conductivity. Any number of loops and any corresponding specific resistance can be used to achieve the desired total resistance.
  • The passivation structure 16 can also be designed to contain areas of opposite conductivity, creating a structure that has pn junctions anywhere. A pn junction is used to gradually lower the voltage rather than linearly. Each pn junction would thus form a diode.
  • In order to achieve an adequate voltage drop, the passivation structure can be designed to contain twenty five loops, each of which has four diodes, each causing a voltage drop of six volts.
  • When pn junctions are formed in the loop-forming band 22 in 5 a mask can be used to counter-dope the desired portions of the loop-forming tape 22 to enable. 5 shows, for example, p-regions 34 which intersect the loop-forming n-band (N-type looping strip) 22 and in the continuous band 22 Form pn junctions.
  • However, it has been found that passivation structures containing diodes have a relatively high capacitance, which is undesirable especially under conditions of a high ratio dv / dt. In order to reduce the high capacitance, the polysilicon between the diodes can be short-circuited by a metal layer or silicide, for example at least on the curves in each loop (90 ° positions).
  • As in 6 For example, a layer of metal (represented by a darker layer) over the loop-forming tape 22 are formed which contains pn junctions. Through the metal layer over the loop-forming tape 22 there is a reduction in its resistance, which in turn reduces its time constant RC.
  • The passivation structure 16 in 7 is between the contact 36 of the active area 12th and the contact 38 switched to the HIGH side of the component. The passivation structure 16 is over the oxide layer 40 formed, which is arranged on the chip (die) 14. An area 42 with conductivity opposite to the chip's conductivity is under the thick oxide layer 40 educated. The area 42 preferably contains a RESURF concentration of dopants. In the preferred embodiment, the chip is 14 doped with n-dopants while the area 42 is doped with p-type dopants. It should be noted that the thickness of the oxide layer 40 instead of 1.0 μm, as was necessary in the case of components of the prior art, can be approximately 0.5 μm, since the voltage is graded very gradually.

Claims (9)

  1. A semiconductor device comprising: a semiconductor body of a first conductivity type, an active region formed in the semiconductor body and containing a region of a second conductivity type which ends in the vicinity of the outer boundary of the active region, and a passivation structure arranged around the active area and a continuous band of resistance material with a substantially uniform width, the continuous band crossing itself after a circumnavigation of the active area and forming a first closed loop made of a resistance material, which serves as the inner boundary of the passivation structure, a loop-forming band made of the resistance material that surrounds the first closed loop to form loops without crossing, the continuous band crossing itself a second time and forming a second closed loop of the resistive material around the first closed loop, acting as the outer boundary serves the passivation structure, wherein the loop-forming tape extends at one end from the outer edge of the first closed loop and ends at the other end at the inner edge of the second closed loop.
  2. Semiconductor device after Claim 1 , in which the resistance material consists of polysilicon.
  3. Semiconductor device after Claim 1 , in which the continuous band of resistance material contains areas of a first conductivity type, which are adjacent to areas of a second conductivity type.
  4. Semiconductor device after Claim 1 , in which the passivation structure is arranged over a thick insulating layer.
  5. Semiconductor device after Claim 1 , in which the passivation structure is arranged over an area of the second conductivity type in the semiconductor body which is doped with a RESURF concentration of dopants.
  6. Semiconductor device after Claim 1 , in which the first closed loop contains several curved sections which are connected to one another via straight sections and thus form a closed loop.
  7. Semiconductor device after Claim 1 which further comprises a metal layer formed on the continuous band of resistance material.
  8. Semiconductor device after Claim 1 , in which the continuous band of resistance material has pn junctions formed therein and wherein a metal layer is formed over at least one of the pn junctions.
  9. Semiconductor device after Claim 8 , in which the resistance material comprises polysilicon.
DE112005002852.6T 2004-11-17 2005-11-17 Passivation structure with voltage equalization loops Active DE112005002852B4 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/991,167 US7183626B2 (en) 2004-11-17 2004-11-17 Passivation structure with voltage equalizing loops
US10/991,167 2004-11-17
PCT/US2005/041734 WO2006055738A2 (en) 2004-11-17 2005-11-17 Passivation structure with voltage equalizing loops

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DE112005002852T5 DE112005002852T5 (en) 2007-10-11
DE112005002852B4 true DE112005002852B4 (en) 2020-03-12

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US (2) US7183626B2 (en)
JP (1) JP2008521256A (en)
KR (1) KR100903428B1 (en)
CN (1) CN101057337B (en)
DE (1) DE112005002852B4 (en)
WO (1) WO2006055738A2 (en)

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US7183626B2 (en) * 2004-11-17 2007-02-27 International Rectifier Corporation Passivation structure with voltage equalizing loops
CN101405871A (en) * 2004-11-24 2009-04-08 美高森美公司 Junction termination structures for wide-bandgap power devices
US8928065B2 (en) * 2010-03-16 2015-01-06 Vishay General Semiconductor Llc Trench DMOS device with improved termination structure for high voltage applications
US8853770B2 (en) * 2010-03-16 2014-10-07 Vishay General Semiconductor Llc Trench MOS device with improved termination structure for high voltage applications
JP2012221976A (en) * 2011-04-04 2012-11-12 Toyota Central R&D Labs Inc Semiconductor device
EP2779225B1 (en) 2011-11-11 2018-04-25 Fuji Electric Co., Ltd. Semiconductor device
JP6134219B2 (en) 2013-07-08 2017-05-24 ルネサスエレクトロニクス株式会社 Semiconductor device
JP6649102B2 (en) * 2016-02-05 2020-02-19 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2018101662A (en) * 2016-12-19 2018-06-28 パナソニックIpマネジメント株式会社 Semiconductor element
JP2019062031A (en) * 2017-09-25 2019-04-18 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of the same

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Publication number Publication date
KR20070084339A (en) 2007-08-24
CN101057337A (en) 2007-10-17
US20070120224A1 (en) 2007-05-31
DE112005002852T5 (en) 2007-10-11
KR100903428B1 (en) 2009-06-18
CN101057337B (en) 2011-01-05
WO2006055738A3 (en) 2006-11-02
JP2008521256A (en) 2008-06-19
US8076672B2 (en) 2011-12-13
US20060102984A1 (en) 2006-05-18
WO2006055738A2 (en) 2006-05-26
US7183626B2 (en) 2007-02-27

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