DE10354421A1 - Gate contact structure, produced by forming a trench in a substrate, precipitating a gate dielectric, precipitating a field oxide, and polyrecess etching - Google Patents

Abstract

A process for producing a gate contact structure during the production of a trench high power transistor, comprises preparing a semiconductor substrate, forming a trench in the substrate, precipitating a gate dielectric (1) onto the inner walls of the trench, and precipitating a field oxide. The gate oxide is precipitated followed by a gate material (3). The gate material is then polyrecess etched. The liner (4) is then precipitated, and the liner and the intermediate oxide (5) are selectively etched. The liner consists of silicon nitride or oxynitride.

Description

The The invention relates to high-power transistors, in particular high-power transistors with a new gate contact structure.

In the power electronics is for Transistors generally a reduction of their area-specific On resistance wanted. With a reduction of structure sizes and Increase the Cell density can be the goal of a smaller on-resistance over one Magnification of the area specific Channel width of a power transistor can be achieved. The more cells per unit area can be integrated the bigger the channel width and the smaller the on-resistance.

The Reduction of structure sizes achieved their limit at the minimum feature size, which is essentially through the accuracy of structuring by the photo technique set becomes. For modern power transistors and especially for low-voltage devices the lithographic requirements are already close to the requirements to modern DRAM technologies. Adjustment accuracy by 50nm and structure widths By 250nm, however, will be necessary to comply with the current process concepts Next-generation power transistors to develop.

The accuracy to be achieved in the structuring of individual semiconductor zones through mask steps is by the misalignment of the respective photo levels for forming these semiconductor zones relative to already formed in the semiconductor body Structures, paint properties of the used in the exposure Photoresist and aberrations limited. With the help of the latest Although exposure techniques can be accurate, with the smallest Structures relative to each other can be further improved. The effort for this but is extremely large and expensive.

at the manufacture of trench high-power transistors are with Help of a usual photoresist and etching technology and a hard mask of, for example, a silicon dioxide layer Trenches introduced. The width of a trench can be, for example ranging from 200 nm to several microns. She can, too smaller or possibly larger. The distance between the trenches is between 250 nm to several microns and can also be smaller. Instead of the silicon dioxide layer may also be a other suitable masking layer is used to form the trenches become.

To the removal of the silicon dioxide layer is by deposition the inner walls the trenches a gate dielectric for example, also deposited silicon dioxide. In the Trench in and on the surface of the semiconductor body polycrystalline silicon is deposited.

It includes a Polyrecessätzung in which the polycrystalline silicon in the upper region of the trench and on the surface of the semiconductor body is removed again.

• – am Chiprand aus dem Trench ausgeführt wird und dann konventionell kontaktiert oder
• – unmaskiert zurückgeätzt und über einen elektrisch inaktiven Trench, der mit Feldoxid ausgekleidet ist, kontaktiert wird.

The gate contact is achieved either by the fact that the gate material, in most cases polysilicon (gate poly),

• - Is performed on the chip edge of the trench and then conventionally contacted or
• - etched back unmasked and contacted via an electrically inactive trench lined with field oxide.

Of the Disadvantage of the first method is that on the one hand, a separate lithography level is necessary to structure the gate poly, and the other results from the structuring of the gate poly also topography, in the subsequent levels, such as the contact level, very disturbing can affect. Therefore, according to the current processes, it is necessary to the polysilicon (poly) after deposition from 950nm to 400nm thinning, as the Contact structuring with the high level not reliable too accomplish is. It is also to ensure the design that no contacts in the vicinity the polystep are present, which means more effort.

Of the Disadvantage of the second method is that this method is only for relative thick field oxide layers is applicable. This method can be used for trench transistors, which only need to lock 20V or even less, and therefore the field oxide in the range of 200nm thickness (or even less) and the poly with one Also have a width in the field oxide trench of only about 200 nm, not be applied. To get an adjusted contact on the inactive To be able to put Trench it is necessary to have a lithograph that can resolve 200nm, and that at very high demands on structure widths and adjustment accuracy.

It has therefore been proposed to make the electrically inactive trench wider at the exact location of the contact in order to have enough space for contact. The disadvantage is that the thickness of the polysilicon must be designed on the widest trench, so that it is also completely filled. However, this leads to more costs in the deposition and etching back. Broader trenches are not possible in all layout constructions because the narrower silicon mesa has the electrical function impaired. The trench etch process is also not as easy to master for wider trenches because the different trench widths in the layout are very risky in terms of black-silicon.

It There is therefore a need for high-performance transistors with a gate contact structure, which is easy to make, no topography on the Polyeben does not depend on the thickness of the field oxide and has a uniform design Trench width allows.

The The object is achieved by the Characteristics of claim 1 solved.

Of the The core of the invention is the processing of a self-aligning Gate contact on Trenchpoly by means of a liner stop layer.

The The object of the invention is achieved in that after the Recessätzung the Gatematerials a layer (liner) on the substrate surface substantially is conformally deposited, this liner layer between the Substrate and the intermediate oxide is arranged. The intermediate oxide and however, the liners should be etched selectively to each other can.

By the deposition of the liner layer can be dispensed with the poly-lithography which makes the subsequent level more flexible. The processing can continue after the deposition of the liner as usual, for Example by the deposition of the usual intermediate oxide (USG / BPSG stack). On the Photographic level contact, the intermediate oxide is patterned, with the etching selectively to the liner, so the depth of the polyrecess does not matter plays.

One An essential advantage of the invention is that the gatepoly contact self-aligning is etched, so that the lithography requirements in terms of structure width and adjustment are relaxed.

By the liner layer according to the invention it is even possible large areas inactive trenches in the contact etch, i. the BPSG between wegzuätzen the trenches.

Of the Another process can be done in a conventional way carried out become. The contacts can be used for Example filled with doped polysilicon or tungsten, before aluminum is used up. The metallization can be direct sputtered after liner removal, if that by the contact geometry possible is. It should also be noted that, if desired, silicon trenches may be etched.

There no poly on the surface guided will have to but the places that were previously realized as Polybahn than contacted Field oxide trenches are constructed.

Of the Liner can be made of any material. As an example, silicon nitride or silicon oxynitride.

The only requirement of the liner is that the liner and the intermediate oxide etched selectively to each other can be.

In a particular embodiment the liner is made of silicon oxynitride. This has the advantage that the hydrogen permeability better than a liner of e.g. Silicon nitride. The hydrogen permeability is desired because in the subsequent steps the structure with a forming gas from H2, possibly with N2, is treated to any open Bonds to the interface saturate the gate oxide. The hydrogen permeability is important in that respect, since the liner except in the contacts in the high-power transistor preserved.

The preferred gate material is polysilicon, even if the other materials. such as different silicides (eg WSi _x ) can be used.

According to the invention, the Liner layer for both the cell field as well the field oxide trenches are used.

It is also a invention High power transistor provided by the method of the invention according to claim 1.

following The invention will be explained in more detail with reference to the drawings. Show it:

1a FIG. 2 is a schematic sectional view of an intermediate stage in the production of a cell array according to the prior art; FIG.

1b : a sectional view of the cell array according to 1b after the deposition of the inventive liner, the intermediate oxide, and after the contact etching;

2a FIG. 3 is a sectional view of an intermediate stage in the production of field oxide trenches according to the prior art; FIG.

2 B : a sectional view of the Feldo xidtrenches according to 2 B after the deposition of the inventive liner and the intermediate oxide, after the contact etching;

3 : A sectional view of the field oxide trenches according to 2a after the deposition of the liner and the intermediate oxide according to the invention, after the contact etching at low gate excess.

4 : A representation of the self-aligned gate contact after metallization using the example of the S-FET3 with source poly in the trench bottom

1 shows in the sectional view an intermediate stage in the manufacture of a cell array of a high-power transistor. This intermediate arises after the introduction of a trench in the semiconductor substrate, for. B. using a conventional photoresist and etching technology; after the deposition of a gate dielectric 1 on the inner walls of the trenches; Deposition and structuring of the field oxide 2 , the gate material 3 , z. B. of polycrystalline silicon; and the step of polyetch etching, wherein the polycrystalline silicon in the upper region of the trench and on the surface of the semiconductor body is removed again. All these steps belong to the state of the art and are known to the person skilled in the art.

Like from the 2 B can the cell box after the excretion of the liner 4 and the intermediate oxide disposed thereon 5 be structured without problems, since the liner is not attacked in the etching of the intermediate oxide.

2a shows in the sectional view an intermediate stage in the production of a field oxide trench. The process steps to produce the field oxide trench correspond to the process steps described in the 1a are described.

Like in the 2 B can be shown after the deposition of the liner 4 , the intermediate oxide 5 and the structuring of the intermediate oxide contacting very simple. this will be the liner 3 etched selectively to the intermediate oxide and selectively to the field oxide to open the contacts (not shown).

The 3 illustrates the advantages of the invention. The dashed lines in the 3 describe the etching front 6 at the opening of the gate contact at a deep gate recess. The critical point is the interface between the intermediate oxide 5 , the field oxide 2 and the gate material 3 , When structuring the intermediate oxide 5 According to the prior art, the mask is not exactly over the gate poly or the opening is larger than the extent of the poly area, a certain area of the field oxide 2 through the intermediate oxide 5 can not be covered. As a result, part of the intermediate oxide would be etched away in the subsequent etching step. By erfindungemäßen liner 4 becomes the field oxide 2 not attacked.

As the 4 shows, the liner of the invention 4 come in a variety of transistors for use. 4 shows a representation of the self-aligned gate contact according to the invention, after metallization, using the example of the S-FET3 with source poly 7 in the trench floor. Like in the 4 As shown, the gatepoly may pass over a polyplug 8th be contacted.

1

Gate dielectric

2

field oxide

3

gate material

4

liner

5

intermediate oxide

6

etching front

7

Sourcepoly

8th

Polyplug

Claims (11)

A method of fabricating a gate contact structure in the manufacture of a trench high power transistor, comprising the steps of: providing a semiconductor substrate; - introducing a trench into the semiconductor substrate; Deposition of a gate dielectric ( 1 ) on the inner walls of the trenches; - deposition and structuring of a field oxide ( 2 ); Depositing the gate oxide depositing a gate material 3 ); Polyrecess etching of the gate material; and - depositing a liner ( 4 ), whereby the liner ( 4 ) and the intermediate oxide to be deposited ( 5 ) are etched selectively to each other. Method according to claim 1, characterized in that the liner ( 4 ) consists of silicon nitride or silicon oxynitride. Method according to claim 2, characterized in that the liner ( 4 ) consists of silicon oxynitride. Method according to one of the preceding claims, characterized in that the gate material ( 3 ) consists of polysilicon. Method according to one of the preceding claims, characterized in that the intermediate oxide ( 5 ) consists of a USG / BPSG stack. Method according to one of the preceding claims, characterized in that the gate oxide ( 1 ) consists of silicon oxide. Method according to one of the preceding claims, characterized in that the field oxide ( 2 ) consists of silicon oxide. Method according to one of the preceding claims, characterized in that the intermediate oxide ( 5 ) directly on the liner ( 4 ) is applied. Process according to claim 8, characterized in that the intermediate oxide ( 5 ) is subsequently structured. A high performance trench transistor made after the method according to a the claims 1-9. High-power trench transistor, characterized in that the gate material ( 3 ) through a polyplug ( 8th ) is contacted.