DE10354421B4 - Method for producing a gate contact structure of a trench high-power transistor and high-power transistor produced by this method - Google Patents

Abstract

A method for producing a gate contact structure in the manufacture of a trench high-power transistor, comprising the following steps:
- Providing a semiconductor substrate;
- introducing a trench into the semiconductor substrate;
- depositing a gate dielectric (1) on the inner walls of the trench;
- depositing a gate material (3) made of polysilicon;
- Polyrecessätzen the gate material (3);
- depositing a liner (4),
Separating an intermediate oxide (5),
- etching the intermediate oxide (5) selectively with respect to the liner (4) such that during the etching of the intermediate oxide (5) the liner (4) is exposed above the trenches;
- etching the liner (4) selectively to the intermediate oxide (5) such that contact holes to the gate material (3) are opened; and
- Contacting the gate material (3) via a contact (8) made of polysilicon.

Description

The The present invention relates to a process for the preparation of a Gate contact structure in the manufacture of a trench high-power transistor and a high power transistor produced by this method.

In the power electronics is for Transistors generally a reduction of their area-specific On resistance wanted. With a reduction of structure sizes and Increase the Cell density can be the goal of a smaller on-resistance over one Magnification of the area specific Channel width of a power transistor can be achieved. The more cells per unit area can be integrated the bigger the channel width and the smaller the on-resistance.

The Reduction of structure sizes achieved their limit at the minimum feature size, which is essentially through the accuracy of structuring by the photo technique set becomes. For modern power transistors and especially for low-voltage components the lithographic requirements are already close to the requirements to modern DRAM technologies. An adjustment accuracy around 50 nm and However, feature sizes of 250 nm will be necessary to work with the current process concepts power transistors of the next generation to develop.

The accuracy to be achieved in the structuring of individual semiconductor zones through mask steps is by the misalignment of the respective photo levels for forming these semiconductor zones relative to already formed in the semiconductor body Structures, by paint properties of the used in the exposure Photoresist and limited by aberrations. With the help of the latest Although exposure techniques can be accurate, with the smallest structures can be generated relative to each other, further improved. The effort is but extremely large and expensive.

at the manufacture of trench high-power transistors are with Help of a usual photoresist and etching technology and a hard mask of, for example, a silicon dioxide layer Trenches introduced. The width of a trench can be, for example ranging from 200 nm to several microns. She can, too smaller or possibly larger. The distance between the trenches is between 250 nm to several microns and can also be smaller. Instead of the silicon dioxide layer may also be a other suitable masking layer is used to form the trenches become.

To the removal of the silicon dioxide layer is by deposition the inner walls the trenches a gate dielectric for example, also deposited silicon dioxide. In the Trench in and on the surface of the semiconductor body polycrystalline silicon is deposited.

It includes a Polyrecessätzung in which the polycrystalline silicon in the upper region of the trench and on the surface of the semiconductor body is removed again.

• – am Chiprand aus dem Trench herausgeführt und dann konventionell kontaktiert wird oder
• – unmaskiert zurückgeätzt und über einen elektrisch inaktiven Trench, der mit Feldoxid ausgekleidet ist, kontaktiert wird.

The gate contact is achieved either by the fact that the gate material, in most cases polysilicon (gate poly),

• - led out of the trench on the chip edge and then contacted conventionally or
• - etched back unmasked and contacted via an electrically inactive trench lined with field oxide.

Of the Disadvantage of the first method is that on the one hand, a separate lithography level is necessary to structure the gate poly, and the other results from the structuring of the gate polyp also topography, in the subsequent levels, such as the contact level, very disturbing can. Therefore, according to current processes, the polysilicon is necessary (Poly) after the deposition of 950 nm to 400 nm back thinning, since the contact structuring with a high level not reliable too accomplish is. It also has to be ensured with this design that no contacts in the vicinity the polystep are present, which means more effort.

Of the Disadvantage of the second method is that these are only for relative thick field oxide layers is applicable. This method can be used for trench transistors only need to lock 20V or even less, so the field oxide in the range of 200 nm thickness (or even less) is and the poly also has a width in the field oxide trench of only about 200 nm, not be applied. To get an adjusted contact on the inactive Being able to put Trench is a lithography is necessary, which can resolve 200 nm, and this at very high demands on structure widths and adjustment accuracy.

It has therefore been proposed to make the electrically inactive trench at the exact location of the contact wider so as to have enough space for the contact. A disadvantage of this is that then the thickness of the polysilicon on the widest trench must be designed so that it is completely filled. However, this leads to more costs in the deposition and etching back. Broader trenches are not possible in all layout constructions because a thinner silicon mesa impairs the electrical function. Also is Tren It is not easy to master the process of chasing wider trenches because the different trench widths in the layout are very risky with regard to black silicon.

It It is therefore an object of the invention to provide a process for the preparation of a Gate contact structure of trench high-power transistors to provide with the gate contact structure easily is, this has no topography on the poly plane, not of the thickness of the field oxide depends and in the design allows a uniform trench width.

In detail is still from the DE 198 07 745 A1 a method for producing a trench transistor is known in which an insulating layer is applied to the surface of a semiconductor body provided with polysilicon-filled trenches. In this insulating layer holes are introduced, leading to the polysilicon fillings. These holes are then filled with polysilicon.

Furthermore, from the DE 101 20 929 A1 a method for. Producing transistors for memory cells known in which a liner layer of silicon nitride or silicon nitride as etch stop for a Siliziumoxidätzen used.

The The object is achieved by a Method solved with the features of claim 1. Advantageous developments The invention will become apparent from the dependent claims.

at The invention thus takes place the processing of a self-adjusting Gate contact on Trenchpoly by means of a liner stop layer. For this is after the Recessätzung of the gate material, a layer (liner) on the substrate surface substantially conformally deposited, this liner layer between the substrate and the intermediate oxide is arranged. The intermediate oxide and the liner are thereby selectively etchable to each other.

By the deposition of the liner layer can be dispensed with the poly-lithography which makes the subsequent level more flexible. The processing can continue after the deposition of the liner as usual, for Example by the deposition of the usual intermediate oxide (USG / BPSG stack). Above that Photographic level contact, the intermediate oxide is patterned, with the etching selectively to the liner, so the depth of the polyrecess does not matter plays.

One An essential advantage of the invention is that the gatepoly contact self-aligning is etched, so that the lithography requirements in terms of structure width and adjustment are very relaxed.

By the liner layer, it is even possible large areas inactive trenches to open in the contact etch, d. H. the BPSG between the Trenches wegzuätzen.

Of the Another process can be done in a conventional way carried out become. The contacts can be used for Example filled with doped polysilicon or tungsten, before aluminum is applied. The metallization can be direct sputtered after liner removal, if that by the contact geometry possible is. It should also be noted that, if desired, silicon trenches are etched can.

There no poly on the surface guided will have to but the places that were previously realized as Polybahn, as contacted field oxide trenches are constructed.

Of the Liner can be made of any material. As an example, silicon nitride or silicon oxynitride.

The only requirement of the liner is that this and the intermediate oxide etched selectively to each other can be.

In a particular embodiment, the liner is silicon oxynitride. This has the advantage that the hydrogen permeability is better than a liner of z. B. silicon nitride. Hydrogen permeability is desirable because in subsequent steps the structure is treated with a forming gas of Her optionally with N ₂ to saturate any open bonds at the gate oxide interface. The hydrogen permeability is important in that the liner is retained except in the contacts in the high power transistor.

The preferred gate material is polysilicon, although other materials such as various silicides (eg, WSi _x ) may be used.

The Liner layer can be used both for the cell field as well the field oxide trenches are used.

It Also, a high power transistor is provided which after the inventive method is made.

following The invention will be explained in more detail with reference to the drawings. Show it:

1A FIG. 2 is a schematic sectional view of an intermediate stage in the production of a cell array according to the prior art; FIG.

1B : a sectional view of the cell array according to 1A but after the deposition of the liner, the intermediate oxide and after the contact etching;

2A FIG. 3 is a sectional view of an intermediate stage in the production of field oxide trenches according to the prior art; FIG.

2 B : A sectional view of the field oxide trenches according to

2A but after the deposition of the liner and the intermediate oxide after the contact etch to explain the invention;

3 : A sectional view of the field oxide trenches according to

2A after the deposition of the liner and the intermediate oxide and after the contact etching at low gate access to explain the invention;

4 : A representation of the self-aligned gate contact after metallization using the example of the S-FET3 with source poly in the trench bottom to explain the invention.

1 shows in a sectional view an intermediate stage in the manufacture of a cell array of a high-power transistor. This intermediate arises after the introduction of a trench / trench in a semiconductor substrate, for. Example, using a conventional photoresist and etching technique with the steps: deposition of a gate dielectric 1 on the inner walls of the trenches, deposition and structuring of a field oxide 2 and a gate material 3 , z. As the polycrystalline silicon, and Polyrecessätzung in which the polycrystalline silicon in the upper region of the trench and on the surface of the semiconductor body is removed again. All these steps belong to the state of the art and are known to the person skilled in the art.

Like from the 1B can be seen, the cell field after the deposition of the liner 4 and the intermediate oxide disposed thereon 5 be easily structured as the liner 4 during the etching of the intermediate oxide 5 not attacked.

2A shows in a sectional view an intermediate stage in the production of a field oxide trench. The process steps to produce the field oxide trench correspond to the process steps described in the 1A are described.

Like in the 2 B can be shown after the deposition of the liner 4 , the intermediate oxide 5 and the structuring of the intermediate oxide 5 the contacting is very easy. This is the liner 3 selective to the intermediate oxide and selective to the field oxide 2 etched to open the contacts (not shown).

The 3 illustrates advantages of the invention. Dashed lines in the 3 describe an etching front 6 at the opening of the gate contact at a deep gate recess. The critical point is the interface between the intermediate oxide 5 , the field oxide 2 and the gate material 3 , When structuring the intermediate oxide 5 According to the prior art, the mask is not exactly above the gate poly or the opening is larger than the extent of the poly area, a certain area of the field oxide 2 through the intermediate oxide 5 not covered. As a result, in the subsequent etching step, a part of the intermediate oxide 5 be etched away. By using the liner 4 becomes the field oxide 2 not attacked.

As the 4 shows, the liner can 4 come in a variety of transistors for use. As an example, here is a self-aligned gate contact after metallization in an S-FET3 with source poly 7 shown in the trench floor. In this case, the gate poly 3 over a polyplug 8th contacted.

1

Gate dielectric

2

field oxide

3

gate material

4

liner

5

intermediate oxide

6

etching front

7

Sourcepoly

8th

Polyplug

Claims (9)

A method of fabricating a gate contact structure in the manufacture of a trench high power transistor, comprising the steps of: providing a semiconductor substrate; - introducing a trench into the semiconductor substrate; Deposition of a gate dielectric ( 1 ) on the inner walls of the trench; - depositing a gate material ( 3 ) of polysilicon; - Polyrecess etching of the gate material ( 3 ); - depositing a liner ( 4 ), - depositing an intermediate oxide ( 5 ), - etching the intermediate oxide ( 5 ) selectively to the liner ( 4 ) such that during the etching of the intermediate oxide ( 5 ) the liner ( 4 ) is exposed above the trenches; - etching the liner ( 4 ) selectively to the intermediate oxide ( 5 ) such that contact holes to the gate material ( 3 ) are open; and - contacting the gate material ( 3 ) via a contact ( 8th ) of polysilicon. Method according to claim 1, characterized in that the liner ( 4 ) consists of silicon nitride or silicon oxynitride. Method according to claim 2, characterized in that the liner ( 4 ) consists of silicon oxynitride. Method according to one of the preceding claims, characterized in that the intermediate oxide ( 5 ) consists of a USG / BPSG stack. Method according to one of the preceding claims, characterized in that the gate oxide ( 1 ) consists of silicon oxide. Method according to one of the preceding claims, characterized in that the field oxide ( 2 ) consists of silicon oxide. Method according to one of the preceding claims, characterized in that the intermediate oxide ( 5 ) directly on the liner ( 4 ) is applied. High performance trench transistor made after the Method according to one of claims 1-7. High-power trench transistor according to claim 8, characterized in that the gate material ( 3 ) through a polyplug ( 8th ) is contacted.