DE10345978A1 - Speichervorrichtung mit Redundanz und Verfahren zur Datenspeicherung - Google Patents

Speichervorrichtung mit Redundanz und Verfahren zur Datenspeicherung Download PDF

Info

Publication number
DE10345978A1
DE10345978A1 DE10345978A DE10345978A DE10345978A1 DE 10345978 A1 DE10345978 A1 DE 10345978A1 DE 10345978 A DE10345978 A DE 10345978A DE 10345978 A DE10345978 A DE 10345978A DE 10345978 A1 DE10345978 A1 DE 10345978A1
Authority
DE
Germany
Prior art keywords
controller
processor unit
control bus
bank select
select signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10345978A
Other languages
English (en)
Inventor
Erwin Thalmann
Sven Boldt
Manfred Moser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10345978A priority Critical patent/DE10345978A1/de
Priority to US10/956,615 priority patent/US20050108461A1/en
Priority to CNA2004100851382A priority patent/CN1604045A/zh
Publication of DE10345978A1 publication Critical patent/DE10345978A1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Die Erfindung schafft eine Speichervorrichtung mit einem Speichermodul (100), das eine Speicherbank (101a) aufweist, einer Controller-Prozessoreinheit, einem Steuerbus (104), einem Adressbus (105) und einem Datenbus (106) zum Datenaustausch zwischen der Controller-Prozessoreinheit (102) und dem Speichermodul (100), wobei das Speichermodul ferner mindestens eine weitere Speicherbank (101b-101n) aufweist, die mittels mindestens eines von der Controller-Prozessoreinheit (102) bereitgestellten und über den Steuerbus (104) zugeführten Bankauswahlsignals (205a, 205b) aktivierbar ist.
DE10345978A 2003-10-02 2003-10-02 Speichervorrichtung mit Redundanz und Verfahren zur Datenspeicherung Ceased DE10345978A1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE10345978A DE10345978A1 (de) 2003-10-02 2003-10-02 Speichervorrichtung mit Redundanz und Verfahren zur Datenspeicherung
US10/956,615 US20050108461A1 (en) 2003-10-02 2004-10-01 Memory apparatus having redundancy, and method for storing data
CNA2004100851382A CN1604045A (zh) 2003-10-02 2004-10-02 具冗余存储装置及储存资料方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10345978A DE10345978A1 (de) 2003-10-02 2003-10-02 Speichervorrichtung mit Redundanz und Verfahren zur Datenspeicherung

Publications (1)

Publication Number Publication Date
DE10345978A1 true DE10345978A1 (de) 2005-04-28

Family

ID=34399206

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10345978A Ceased DE10345978A1 (de) 2003-10-02 2003-10-02 Speichervorrichtung mit Redundanz und Verfahren zur Datenspeicherung

Country Status (3)

Country Link
US (1) US20050108461A1 (de)
CN (1) CN1604045A (de)
DE (1) DE10345978A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006343822A (ja) * 2005-06-07 2006-12-21 Fujitsu Ltd ライブラリ装置
CN101923495B (zh) * 2009-06-10 2012-11-14 Tcl集团股份有限公司 一种嵌入式容错系统及其容错方法
JP7392181B2 (ja) * 2021-03-24 2023-12-05 長江存儲科技有限責任公司 冗長バンクを使用した故障メインバンクの修理を伴うメモリデバイス

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725945A (en) * 1984-09-18 1988-02-16 International Business Machines Corp. Distributed cache in dynamic rams
US6360285B1 (en) * 1994-06-30 2002-03-19 Compaq Computer Corporation Apparatus for determining memory bank availability in a computer system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5774647A (en) * 1996-05-15 1998-06-30 Hewlett-Packard Company Management of memory modules
US6414868B1 (en) * 1999-06-07 2002-07-02 Sun Microsystems, Inc. Memory expansion module including multiple memory banks and a bank control circuit
US6301164B1 (en) * 2000-08-25 2001-10-09 Micron Technology, Inc. Antifuse method to repair columns in a prefetched output memory architecture
US6714433B2 (en) * 2001-06-15 2004-03-30 Sun Microsystems, Inc. Memory module with equal driver loading
US6662271B2 (en) * 2001-06-27 2003-12-09 Intel Corporation Cache architecture with redundant sub array
DE10226585C1 (de) * 2002-06-14 2003-12-11 Infineon Technologies Ag RAM-Speicherschaltung
US7123512B2 (en) * 2002-07-19 2006-10-17 Micron Technology, Inc. Contiguous block addressing scheme
DE10331543B4 (de) * 2003-07-11 2007-11-08 Qimonda Ag Verfahren zum Testen einer zu testenden Schaltungseinheit und Schaltungsanordnung zur Durchführung des Verfahrens

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725945A (en) * 1984-09-18 1988-02-16 International Business Machines Corp. Distributed cache in dynamic rams
US6360285B1 (en) * 1994-06-30 2002-03-19 Compaq Computer Corporation Apparatus for determining memory bank availability in a computer system

Also Published As

Publication number Publication date
US20050108461A1 (en) 2005-05-19
CN1604045A (zh) 2005-04-06

Similar Documents

Publication Publication Date Title
WO2004046940A3 (en) Active termination control through on module register
TW200611276A (en) De-coupled memory access system and method
PL1615787T3 (pl) Sposób i układ do wyrównywania nieruchomego pojazdu względem sztucznego horyzontu
WO2005066965A3 (en) Integral memory buffer and serial presence detect capability for fully-buffered memory modules
TW345635B (en) Bus analyzer and method for testing inner bus thereof
WO2005024561A3 (en) Memory module and method having on-board data search capabilites and processor-based system using such memory modules
WO2002073619A3 (en) System latency levelization for read data
KR970049631A (ko) 멀티 옵션을 지원하는 장치 및 그 제어방법
MY152831A (en) Adapting word line pulse widths in memory systems
TW200625334A (en) Memory system, memory device, and output data strobe signal generating method
ATE335641T1 (de) Überwachungssystem, fahrzeugüberwachungsvorrichtung, überwachungsverfahren, überwachungsprogramm, dieses enthaltendes rechnerlesbares aufzeichnungsmedium
MXPA06000453A (es) Recoleccion de datos de dispositivo de campo disipado en un sistema de control de proceso.
EP0366192A3 (de) Textverarbeitungsvorrichtung
WO2005006196A3 (en) Data integrety of a non valatile cache upon os cache driver operation
WO2005041055A3 (en) Echo clock on memory system having wait information
ATE549671T1 (de) Steuerungssystem
JP2008226423A5 (de)
AU7980898A (en) Method and apparatus for local control signal generation in a memory device
WO2006060073A3 (en) Method and apparatus for dual protection of a protected memory block
DE10345978A1 (de) Speichervorrichtung mit Redundanz und Verfahren zur Datenspeicherung
DE69618831D1 (de) ECC-geschützte Speicherorganisation mit Lese-Änderungs-Schreib-Pipelinezugriff
WO2003073285A3 (en) Memory subsystem including an error detection mechanism for address and control signals
TW200728946A (en) Control system and method thereof
DE102004046543A1 (de) Wortleitungssegment-Aktivierungsverfahren und zugehöriger Halbleiterspeicherbaustein
AU2002218274A1 (en) Robust voice recognition with data bank organisation

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection