DE10344113A1 - Vorrichtung und Verfahren zum Verbinden von Wafern - Google Patents

Vorrichtung und Verfahren zum Verbinden von Wafern Download PDF

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Publication number
DE10344113A1
DE10344113A1 DE10344113A DE10344113A DE10344113A1 DE 10344113 A1 DE10344113 A1 DE 10344113A1 DE 10344113 A DE10344113 A DE 10344113A DE 10344113 A DE10344113 A DE 10344113A DE 10344113 A1 DE10344113 A1 DE 10344113A1
Authority
DE
Germany
Prior art keywords
joining wafers
joining
wafers
wafers along
corresponding method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10344113A
Other languages
English (en)
Inventor
Erich Thallner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to DE10344113A priority Critical patent/DE10344113A1/de
Priority to US10/938,931 priority patent/US20050064680A1/en
Priority to KR1020040076207A priority patent/KR20050030138A/ko
Priority to JP2004278474A priority patent/JP2005101617A/ja
Publication of DE10344113A1 publication Critical patent/DE10344113A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching

Abstract

Bei der Erfindung handelt es sich um eine Vorrichtung und ein entsprechendes Verfahren zum Verbinden von Wafern entlang ihrer korrespondierenden Oberflächen.
DE10344113A 2003-09-24 2003-09-24 Vorrichtung und Verfahren zum Verbinden von Wafern Withdrawn DE10344113A1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE10344113A DE10344113A1 (de) 2003-09-24 2003-09-24 Vorrichtung und Verfahren zum Verbinden von Wafern
US10/938,931 US20050064680A1 (en) 2003-09-24 2004-09-11 Device and method for bonding wafers
KR1020040076207A KR20050030138A (ko) 2003-09-24 2004-09-23 웨이퍼 부착을 위한 장치 및 방법
JP2004278474A JP2005101617A (ja) 2003-09-24 2004-09-24 ウェハー結合装置及びその方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10344113A DE10344113A1 (de) 2003-09-24 2003-09-24 Vorrichtung und Verfahren zum Verbinden von Wafern

Publications (1)

Publication Number Publication Date
DE10344113A1 true DE10344113A1 (de) 2005-05-04

Family

ID=34306045

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10344113A Withdrawn DE10344113A1 (de) 2003-09-24 2003-09-24 Vorrichtung und Verfahren zum Verbinden von Wafern

Country Status (4)

Country Link
US (1) US20050064680A1 (de)
JP (1) JP2005101617A (de)
KR (1) KR20050030138A (de)
DE (1) DE10344113A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8118290B2 (en) 2006-06-02 2012-02-21 Erich Thallner Method for holding wafers and device for fixing two parallel arranged wafers relative to one another

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2091071B1 (de) * 2008-02-15 2012-12-12 Soitec Verfahren zum Bonden zweier Substrate
US20100089978A1 (en) * 2008-06-11 2010-04-15 Suss Microtec Inc Method and apparatus for wafer bonding
CN102237285B (zh) * 2010-04-20 2016-05-18 台湾积体电路制造股份有限公司 晶片接合机
FR2963157B1 (fr) * 2010-07-22 2013-04-26 Soitec Silicon On Insulator Procede et appareil de collage par adhesion moleculaire de deux plaques
FR2972848A1 (fr) * 2011-03-18 2012-09-21 Soitec Silicon On Insulator Appareil et procédé de collage par adhésion moléculaire avec minimisation de déformations locales
FR2997224B1 (fr) * 2012-10-18 2015-12-04 Soitec Silicon On Insulator Procede de collage par adhesion moleculaire
KR102586083B1 (ko) * 2022-07-15 2023-10-05 성균관대학교산학협력단 웨이퍼 본딩 방법 및 웨이퍼 본딩 시스템

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4404931A1 (de) * 1993-02-16 1994-08-18 Nippon Denso Co Verfahren und Vorrichtung zum Direktverbinden von zwei Körpern
US6180496B1 (en) * 1997-08-29 2001-01-30 Silicon Genesis Corporation In situ plasma wafer bonding method
DE10048374A1 (de) * 1999-10-01 2001-04-12 Max Planck Gesellschaft Verfahren zum großflächigen Verbinden von Verbindungshalbleitermaterialien
WO2001061743A1 (en) * 2000-02-16 2001-08-23 Ziptronix, Inc. Method for low temperature bonding and bonded structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6146463A (en) * 1998-06-12 2000-11-14 Applied Materials, Inc. Apparatus and method for aligning a substrate on a support member
US6780759B2 (en) * 2001-05-09 2004-08-24 Silicon Genesis Corporation Method for multi-frequency bonding
KR100480819B1 (ko) * 2002-03-20 2005-04-06 엘지.필립스 엘시디 주식회사 합착기 챔버의 크리닝 방법
US20030178145A1 (en) * 2002-03-25 2003-09-25 Applied Materials, Inc. Closed hole edge lift pin and susceptor for wafer process chambers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4404931A1 (de) * 1993-02-16 1994-08-18 Nippon Denso Co Verfahren und Vorrichtung zum Direktverbinden von zwei Körpern
US6180496B1 (en) * 1997-08-29 2001-01-30 Silicon Genesis Corporation In situ plasma wafer bonding method
DE10048374A1 (de) * 1999-10-01 2001-04-12 Max Planck Gesellschaft Verfahren zum großflächigen Verbinden von Verbindungshalbleitermaterialien
WO2001061743A1 (en) * 2000-02-16 2001-08-23 Ziptronix, Inc. Method for low temperature bonding and bonded structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ROBERDS,B.E., CHOQUETTE,K.D., GEIB,K.M., KRAVITZ, S.H., TWESTEN,R.D., FARRENS,S.N.: Wafer Bonding ofGaAs, InP and Si annealed without hydrogen for ad-vanced device technologies. In: Electrochemical Society Proccedings, Vol. 97-36, Seite 592-597 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8118290B2 (en) 2006-06-02 2012-02-21 Erich Thallner Method for holding wafers and device for fixing two parallel arranged wafers relative to one another
DE102006026331B4 (de) 2006-06-02 2019-09-26 Erich Thallner Transportable Einheit zum Transport von Wafern und Verwendung einer Gelfolie in einer transportablen Einheit

Also Published As

Publication number Publication date
US20050064680A1 (en) 2005-03-24
KR20050030138A (ko) 2005-03-29
JP2005101617A (ja) 2005-04-14

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OP8 Request for examination as to paragraph 44 patent law
8130 Withdrawal