DE10342996A1 - Semiconductor arrangement comprises a substrate with integrated electronic switching elements, layer stacks arranged over the substrate, and a dummy structure arranged in two layer stacks for mechanically stabilizing the stacks - Google Patents

Semiconductor arrangement comprises a substrate with integrated electronic switching elements, layer stacks arranged over the substrate, and a dummy structure arranged in two layer stacks for mechanically stabilizing the stacks Download PDF

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Publication number
DE10342996A1
DE10342996A1 DE10342996A DE10342996A DE10342996A1 DE 10342996 A1 DE10342996 A1 DE 10342996A1 DE 10342996 A DE10342996 A DE 10342996A DE 10342996 A DE10342996 A DE 10342996A DE 10342996 A1 DE10342996 A1 DE 10342996A1
Authority
DE
Germany
Prior art keywords
substrate
stacks
layer stacks
semiconductor arrangement
switching elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10342996A
Other languages
German (de)
Inventor
Hans-Joachim Barth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10342996A priority Critical patent/DE10342996A1/en
Publication of DE10342996A1 publication Critical patent/DE10342996A1/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Semiconductor arrangement comprises a substrate with integrated electronic switching elements, layer stacks arranged over the substrate, and a dummy structure arranged in two layer stacks for mechanically stabilizing the stacks. A part of the layer stacks has a dielectric layer containing metal structures. An independent claim is also included for a process for the production of the semiconductor arrangement.
DE10342996A 2003-09-17 2003-09-17 Semiconductor arrangement comprises a substrate with integrated electronic switching elements, layer stacks arranged over the substrate, and a dummy structure arranged in two layer stacks for mechanically stabilizing the stacks Ceased DE10342996A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10342996A DE10342996A1 (en) 2003-09-17 2003-09-17 Semiconductor arrangement comprises a substrate with integrated electronic switching elements, layer stacks arranged over the substrate, and a dummy structure arranged in two layer stacks for mechanically stabilizing the stacks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10342996A DE10342996A1 (en) 2003-09-17 2003-09-17 Semiconductor arrangement comprises a substrate with integrated electronic switching elements, layer stacks arranged over the substrate, and a dummy structure arranged in two layer stacks for mechanically stabilizing the stacks

Publications (1)

Publication Number Publication Date
DE10342996A1 true DE10342996A1 (en) 2005-04-21

Family

ID=34352908

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10342996A Ceased DE10342996A1 (en) 2003-09-17 2003-09-17 Semiconductor arrangement comprises a substrate with integrated electronic switching elements, layer stacks arranged over the substrate, and a dummy structure arranged in two layer stacks for mechanically stabilizing the stacks

Country Status (1)

Country Link
DE (1) DE10342996A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006046182A1 (en) * 2006-09-29 2008-04-03 Infineon Technologies Ag Semiconductor element for integrated circuits, has supporting structure, which is arranged in series of layers, which comprises number of dielectric layers
DE102009056562A1 (en) * 2009-12-03 2011-06-09 Telefunken Semiconductors Gmbh & Co. Kg Integrated circuit part, has metallic regions provided above gate region resting on covering layers, partially arranged between strip conductors and not connected with drain-contact, source-contact or gate-contact
DE102008028943B4 (en) * 2007-06-21 2012-11-29 Infineon Technologies Ag Integrated circuit chip with a stress buffering layer, semiconductor device, method for protecting a chip and single chip device
DE102008039939B4 (en) * 2007-09-13 2015-11-26 Infineon Technologies Ag Integrated circuit device with a vapor-deposited insulating layer and method for its production

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037668A (en) * 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure
US6124198A (en) * 1998-04-22 2000-09-26 Cvc, Inc. Ultra high-speed chip interconnect using free-space dielectrics
US6309956B1 (en) * 1997-09-30 2001-10-30 Intel Corporation Fabricating low K dielectric interconnect systems by using dummy structures to enhance process
US6452274B1 (en) * 1997-11-17 2002-09-17 Sony Corporation Semiconductor device having a low dielectric layer as an interlayer insulating layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6309956B1 (en) * 1997-09-30 2001-10-30 Intel Corporation Fabricating low K dielectric interconnect systems by using dummy structures to enhance process
US6452274B1 (en) * 1997-11-17 2002-09-17 Sony Corporation Semiconductor device having a low dielectric layer as an interlayer insulating layer
US6124198A (en) * 1998-04-22 2000-09-26 Cvc, Inc. Ultra high-speed chip interconnect using free-space dielectrics
US6037668A (en) * 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006046182A1 (en) * 2006-09-29 2008-04-03 Infineon Technologies Ag Semiconductor element for integrated circuits, has supporting structure, which is arranged in series of layers, which comprises number of dielectric layers
DE102006046182B4 (en) * 2006-09-29 2010-11-11 Infineon Technologies Ag Semiconductor element with a support structure and manufacturing method
US8592987B2 (en) 2006-09-29 2013-11-26 Infineon Technologies Ag Semiconductor element comprising a supporting structure and production method
DE102008028943B4 (en) * 2007-06-21 2012-11-29 Infineon Technologies Ag Integrated circuit chip with a stress buffering layer, semiconductor device, method for protecting a chip and single chip device
DE102008039939B4 (en) * 2007-09-13 2015-11-26 Infineon Technologies Ag Integrated circuit device with a vapor-deposited insulating layer and method for its production
DE102009056562A1 (en) * 2009-12-03 2011-06-09 Telefunken Semiconductors Gmbh & Co. Kg Integrated circuit part, has metallic regions provided above gate region resting on covering layers, partially arranged between strip conductors and not connected with drain-contact, source-contact or gate-contact

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OP8 Request for examination as to paragraph 44 patent law
8131 Rejection