DE10337418A1 - Integrated digital circuit, e.g. for chip card applications, has functional part receiving duty cycle that is changed in accordance with signal applied to control input of duty cycle change device - Google Patents

Abstract

The integrated digital circuit has a functional part (7) receiving a clock signal with a defined duty cycle, a clock signal generator (8) and a controllable duty cycle change device (2) that forwards the clock signal with altered duty cycle to the functional part, whereby the duty cycle is changed in accordance with a signal applied to the control input (4) of the duty cycle change device.

Description

The invention relates to an integrated Digital circuit according to claim 1.

Integrated digital circuits work usually depending from a fed System clock. Digital switching operations are either dependent from the occurrence of a "high level" or a "low level" being one as well the other simultaneously in the same digital circuit switching operations trigger can. The efficiency of a digital circuit it depends on the exact adherence to the intended timing of the switching operations.

For the exact functioning of the digital circuit is necessary that for For example, processes triggered by the occurrence of a "high level" ended are before switching operations triggered by the "low level" must duty cycle of the clock signal exactly follow certain specifications if this sequence should take place within a clock period.

Especially in the area of chip card applications, As a rule, the clock signals are not generated with quartz precision, but instead by means of a suitable oscillator circuit within the integrated Digital circuit with a relatively inaccurate duty cycle generated.

This often has the consequence that it is for one safe operation of such an integrated digital circuit is necessary is to reduce the clock frequency so that the specified Switching sequences can run safely.

The invention is therefore the object to provide an integrated digital circuit in which safe operation with the greatest possible Performance guaranteed is. This object is achieved by the claim 1 specified measures solved.

The fact that a controllable duty cycle changing device is provided, the functional part can be a clock signal with a for the Functional part so adapted duty cycle be fed so that Functional part can be operated with a maximum clock frequency, what the efficiency of the functional part and thus the integrated circuit maximized is.

Further advantageous configurations the invention are specified in the subordinate claims. By providing a programmable delay unit and a logical one Linking unit the clock signal generated can be changed in a suitable manner in the clock ratio. It is advantageous that a Provisioning unit in the integrated digital circuit in a non-volatile Memory for the functional part typical value of the programmable delay unit to disposal provides.

In particular by providing two clock signals with changed duty cycle can be independent from each other both the duration of the "high level" within a signal cycle and that Duration of the "low level" within one Clock can be set to a suitable value. following the invention with reference to the drawing based on a embodiment explained.

Show it:

1 2 shows a block diagram of an exemplary embodiment of the digital circuit,

2 a detailed design of the in 1 illustrated embodiment,

3 Waveforms to explain the operation of the in 2 circuit shown.

In 1 is an entrance 1 a duty cycle changing device 2 shown a clock signal generator 8th supplies a clock signal SYSCLK.

The clock signal delay unit 2 changes that at the entrance 1 supplied clock signal SYSCLK according to one at the control input 4 applied signal. It provides the clock signal SYSCLK ', which has a changed pulse duty factor, at the output 3 available with a functional part 7 connected is. This functional part 7 provides the actual functionality of the integrated digital circuit. A clock signal SYSCLK 'which is changed in terms of the duty cycle compared to the clock signal SYSCLK generated by the clock signal generator is thus supplied to it. It is now provided that in a functional test of the digital circuit for operation at the highest clock frequency of the functional part 7 the optimal duty cycle is determined. A value corresponding to this duty cycle is stored in a non-volatile memory 5 stored. During normal operation of the integrated digital circuit, a provision unit now reads 6 that in the non-volatile memory 5 stored value and this leads a control input 4 the duty cycle changing device 2 to. The touch change device 2 changes the pulse duty factor based on this supplied value, so that the functional part 7 can be operated at maximum clock frequency.

In detail this means according to 2 that the duty cycle changing unit 2 from a programmable delay chain 8th exists at the entrance 4 a register 6 provides a value according to which the delay chain 8th is programmed. The register 6 The value provided was previously from the non-volatile memory 5 read out. Non-volatile memory 5 can advantageously be an EEPROM memory or a flash memory. But it is also possible that it is a ROM programmed via so-called "E-fuses".

In the duty cycle changing device 2 is in the programmable delay chain 8th the clock signal SYSCLK is delayed and output as a delayed clock signal SYSCLK_g. At the same time, the clock signal SYSCLK is in a logic logic circuit 9 an AND gate 10 and an OR gate 11 fed. In addition, the delayed clock signal SYSCKL_g which is both the AND gate 10 as well as the OR gate 11 fed. At the exit 3 the duty cycle change unit 2 there are therefore two key signals SYSCLK_h and SYSCLK_l which have changed in the duty cycle. This is at the output of the duty cycle change unit 2 pending signal from the OR gate 11 comes changed in the duration of the "high level", while that of the AND gate 10 incoming signal is changed in the "low level".

Based on 3 the formation of the changed "high level duration" and the changed "low level duration" is explained below. a shows a section of a clock signal SYSCLK, which rises from "low level" to "high level" at time t1. In b this is due to the delay chain 8th Delayed clock signal SYSCLK_d shown, which is delayed by the duration δ, rises from "low level" to "high level" at time t2. A coincident course of the curves in a and b is now assumed, so that this is only about the delay 6 are moved. In c is the output of the AND gate 10 shown, which outputs the signal SYSCLK_l. The output signal of an AND gate then assumes the "high level" when a signal with a "high level" is present at both inputs. That means the output of the AND gate 10 rises only with the rising edge of curve b and falls back to the "low level" when the clock signal SYSCLK shown in b drops from the "high level" to the "low level". The signal curve shown in c thus has an extended duration of the "low level" and a shortened duration with the "high level" compared to the clock signal SYSCLK shown in a. In d is the waveform at the output of the OR gate 11 , that is, the signal SYSCLK_h. The OR gate then assumes the "high level" when a signal with a "high level" is present at one of the two inputs. If a signal with a "low level" is present at both inputs, the output of the OR gate assumes the "low level". The clock signal SYSCLK_h thus rises at the output of the OR gate 11 with the rise of the clock signal SYSCLK to the "high level" also to the "high level" and only with the drop in the delayed clock signal SYSCLK_d to the "low level" also falls to the "low level", which at time t4.

The above-described configuration of the integrated digital circuit with a controllable duty cycle change device was carried out on the assumption that a delay chain 8th is provided with a single output to which the delayed clock signal SYSCLK_-d is output. It is easy for the person skilled in the art to understand that different signals with different delays can be tapped from such a delay chain, which signals can be derived via corresponding logic links to clock signals with the same clock period and a corresponding number of different duty cycles.

Claims (4)

Integrated digital circuit with a functional part ( 7 ) to which a clock signal with a predetermined duty cycle is to be supplied, a clock signal generator ( 8th ), which generates a clock signal (SYSCKL), a controllable duty cycle changing device ( 2 ) which sends the clock signal to the functional part with a variable duty cycle ( 7 ) forwards, the pulse duty factor according to a control input ( 4 ) the duty cycle changing device ( 2 ) there is a signal from the duty cycle changing device ( 2 ) is changed. An integrated digital circuit according to claim 1, wherein the duty ratio changing means ( 2 ) a programmable delay unit ( 8th ) and a logical link unit ( 9 ), the clock signal (SYSCKL) of the delay unit ( 8th ) and the logical link unit ( 9 ) and a delayed clock signal (SYSCKL_d) from the delay unit ( 8th ) of the logical link unit ( 9 ) is supplied. Integrated digital circuit according to one of the preceding claims, wherein a provision unit ( 6 ) one in a non-volatile memory ( 5 ) stored value at the control input ( 4 ) the duty cycle changing device ( 2 ) feeds. Integrated digital circuit according to one of the preceding claims, in which the duty ratio changing device ( 2 ) two clock signals with variable duty cycle and the same frequency to the functional part ( 7 ) feeds.