DE10203892B4 - Method for generating a signal pulse sequence with a predetermined stable fundamental frequency - Google Patents

Abstract

Method for generating a signal pulse sequence (y (n)) with a predetermined stable fundamental frequency (f ₀ ) from a sequence of signal pulses (x (n)) whose frequency (f) fluctuates and which has spectral components, the frequency of which is at least a predetermined multiple is the fundamental frequency (f ₀ ), characterized in that the sequence of signal pulses (x (n)) is fed to a digital filter (2), the pass band of which is around the fundamental frequency (f ₀ ) and that by a predetermined half sampling frequency (f _a ) blocks and outputs a signed output signal (B) when energized, and a clock signal pulse (C) is generated each time the output signal (B) changes sign.

Description

The invention relates to a method for generating a signal pulse sequence with a predetermined stable Fundamental frequency, i.e. the restoration of a clock signal (Clock recovery) according to the preamble of claim 1.

In digital circuits, generally always uses a clock signal (clock) so that the individual Calculation and work steps can be processed synchronously. If now the period of the measure is not always the same and in one quite large Dimensions fluctuate (jitter), then it can lead to malfunctions in the circuit.

In the state of the art, i.a. trusts that the clock signal fluctuates so little (little "jitter") that the application not disturbed by it becomes. If necessary, the digital circuit is designed so that they are robust towards Frequency fluctuations in the clock signal is.

An example of the generation of a clock signal that is as accurate as possible in order to avoid interference in the application as far as possible with a clock signal with jitter is given in US 6,137,328 known. A half mixer is used in a conventional delay circuit.

An example of a circuit that is robust against frequency fluctuations in the clock signal is the receiver system according to EP 1 112 6053 , The received data are delayed in the receiver system by several delay circuits. The frequency of the received data determines how often the data was received.

But if you look at the outside Clock also other clock signals with higher frequencies is needed the external clock signal first into a PLL control loop that's so good is designed that as possible little jitter transmitted becomes. However, this means increased circuit complexity, i.e. you have expensive external building blocks use that prepare the clock signal and a complex PLL Regulation included.

Beyond that DE 694 21 834 known a digital clock recovery circuit that can be carried out without the use of multipliers. A symbol timing recovery technique with spectral line extraction is carried out.

Out US 5,425,060 the reduction of the time jitter in clock recovery is known, the parameters of a prefilter being adaptively set such that conjugated, antisymmetric components in the spectrum of the spectrum of interest are compensated.

By Keyhyun Kim et al. appears in "Icon Timing Recovery Using Digital Spectral Line Method For 16-CAP VDSL System ", Global Telecommunications Conference 1998, GLOBECOM 1998, The Bridge to Global Integration, IEEE, Vol. 6, 1998, pages 3467-3472, described a method for clock recovery, using a single sideband filter pair and a multiplier become.

The object of the invention is a to specify a simple method with which a frequency-stable clock signal can be recovered from a noisy clock signal.

This task is solved by the method of claim 1. Preferred embodiments of the invention are the subject of the subclaims.

In the method according to the invention with a "Jittered Clock recovery filter " the noisy clock signal as an ideal square wave signal in addition to the fundamental and the corresponding harmonics additionally has modulated frequencies, which then leads to deviation comes from the ideal rectangle. Now you can with a bandpass that is matched to the clock signal frequency (frequency of the fundamental oscillation), filter out the fundamental vibration. If the passband is very narrow, hardly any harmonics and therefore no jitter are transmitted.

The inventive method for generating a Signal pulse sequence with a predetermined stable basic frequency a sequence of signal pulses whose frequency fluctuates and the spectral Has portions whose frequency is at least a predetermined multiple the fundamental frequency is is characterized in that the sequence of signal pulses digital filter whose pass band is around the fundamental frequency and that locks by a predetermined half sampling frequency and this when excited outputs a signed output signal and every time the sign changes a clock signal pulse of the output signal is generated.

In particular, this includes digital Filter a band filter that is at zero frequency and half the sampling frequency locks, and a zero crossing detector, which occurs at each zero crossing generates a clock signal pulse.

In a preferred embodiment According to the invention, the band filter comprises an FIR filter and an IIR filter, which are connected in series, with the natural frequency of the IIR filter is equal to the fundamental frequency.

For The basic frequency is used in special applications by a PLL control loop multiplied after the digital filter. In this case, the multiplied basic frequency according to the PLL control loop as sampling frequency used by the bandpass filter and the zero crossing detector.

An advantage of the invention is that no complex and precise PLL control is required. The worse and slower control, which can contain the PLL control circuit, takes up less chip area and is therefore not only cheaper in terms of development effort. In addition, it saves expensive external chips that process the clock signal, which drives up the costs of boards etc., since a circuit that is supposed to be robust against jitter has to be designed for higher clock frequencies than the actual working clock. This means that stronger drivers and stronger "pipelining" must be provided, which is associated with more design effort. The stronger drivers also require more space, which means higher costs. Since a digital filter is used in the method according to the invention, hardly any chip area is required, external influences (temperature) are less important, and the method is easy to implement due to the simple structure of a digital filter.

Other features and advantages of Invention result from the following description of one Embodiment, reference is made to the accompanying drawings.

1 shows a filter structure with which the inventive method can be carried out.

2 shows the transmission curve of the filter 1 ,

3 shows a timing diagram for explaining the generation of the frequency-stable signal pulses from an input pulse sequence that is not frequency-stable.

4 shows an embodiment of the bandpass filter 1 ,

In 1 A filter structure for generating a signal pulse sequence with a predetermined stable fundamental frequency is shown, with which the method according to the invention can be carried out. The filter structure is via an input 1 supplied with a sequence of signal pulses x (n) whose frequency fluctuates and which therefore cannot be used directly for clocking time-critical processes in a circuit (not shown).

The frequency fluctuations of the input pulses can be understood such that the input pulses have spectral components in addition to their desired basic frequency f ₀ , the frequency of which is above the basic frequency and in particular is at least a predetermined multiple of the basic frequency f ₀ . The spectral component of the input pulses with f ₀ or a multiple thereof is used regardless of its amplitude in order to excite a system to (resonance) vibrations. The vibrations of the system then serve as a reference for the generation of the desired frequency-stable clock signal. For this purpose, the zero crossing of the (resonance) oscillation amplitude is recorded in a preferred embodiment of the invention. However, in order to allow zero crossings only at the resonance frequency, a corresponding blocking filter is provided, by means of which all undesired frequency components are suppressed.

According to the invention, the sequence of signal pulses x (n) becomes a digital filter 2 supplied, the pass band is around the fundamental frequency f ₀ and blocks by a predetermined half sampling frequency f _a / 2. In contrast, in the pass band, ie when energized, the filter is designed in such a way that it outputs a signed output signal. Such a filter is the band filter 4 , the part of the digital filter 2 is. If the incoming signal component therefore has a frequency that differs from the desired fundamental frequency f ₀ , the band filter blocks 4 and thus the digital filter 2 , so that no clock signal is present on the following circuit. In contrast, if the incoming signal has a component whose frequency corresponds to f ₀ , the band filter becomes 4 excited by this frequency component to oscillate, the oscillation frequency being the desired natural frequency.

The output signal of the band filter 4 becomes a zero point detector 5 coupled in with each change of sign of the output signal of the bandpass filter 4 generates a clock signal pulse. The functioning and the technical implementation of such a zero point detector 5 is known to the person skilled in the art and is therefore not explained further here. Otherwise, other elements can also be used, which pass through the output signal from the bandpass filter 4 generate a clock pulse by a certain value (maximum or minimum).

The clock pulses y (n) by the zero point detector 5 generated have the frequency f ₀ , which is the resonance frequency of the bandpass filter 4 and is equal to the desired frequency.

The frequency-stable clock pulses y (n) can now be processed further or used directly. In the second case they will have an exit 7 fed into the subsequent circuit (not shown), otherwise they are operated with a PLL control loop 8th converted to a higher frequency and only then via an output 9 fed into the subsequent circuit (not shown).

The multiplied frequency according to the PLL control loop 8th can also act as a control clock for the components of the digital filter described above 2 can be used to control oversampling of the input signal of these components. It is therefore shown in the embodiment shown 1 via a feedback line 10 looped back and lies on the belt filter 4 and the zero point detector 5 in the digital filter 2 on.

As for the supply of the digital filter 2 with the sampling frequency f _a the PLL control loop 8th to must oscillate next is a multiplexer in the embodiment shown 6 and a bypass line 3 provided, with which at the beginning of the clock signal recovery, ie immediately after switching on the filter structure of the PLL control loop 8th is first started up with the frequency-unstable clock, and after the settling process the input of the PLL control loop 8th with the multiplexer 6 switched to the frequency-stable clock signal.

In 2 the course of the transmission curve ∣⁣H (f) ∣⁣ is shown in relation to the frequency. As can be seen, this curve has its maximum at f ₀ or f _a . At f ₀ and f _a , the attenuation of the transmitted signal is minimal. Between these two maxima, the transmission curve decreases sharply, down to zero at half the sampling frequency, ie at f _a / 2.

It is clear from the course of the curve that essentially only vibrations with the frequency f _{0 are} excited.

In 3 the sequence of input pulses A is shown. These have approximately the desired frequency f ₀ , but are subject to frequency fluctuations, which are indicated by the deviations of their flanks from the "exact" vertical lines.

The deviation of the actual frequency of the input pulses A from the target frequency means that the spectral components in the input pulses A with the desired frequency f _{0 have} a different amplitude. Regardless, the band filter vibrates 4 however, at its resonance frequency f ₀ , excited by the spectral components with f ₀ in the input pulses. The vibration amplitude of the bandpass filter is in 3 designated with B. It fluctuates depending on the "correspondence" of the frequency of the input pulses A with the resonance frequency of the bandpass filter 4 ,

Each time the signal B crosses zero, which coincides with the "exact" vertical lines, is detected by the zero crossing detector 5 a rectangular pulse is output, so that the sequence of rectangular pulses has the exact frequency f ₀ . This sequence of exact clock signal pulses is labeled C.

In 4 is a possible embodiment of the bandpass filter 4 shown. The band filter 4 consists of a FIR filter 11 and an IIR filter 12 together, which are connected in series. The natural frequency of the IIR filter 12 is equal to the desired fundamental frequency f ₀ . The structure of the FIR filter 11 and the IIR filter 12 from delay elements 13 , Adder 14 and multipliers 15 is known to the person skilled in the art and is not further explained here. However, note that the multipliers 15 multiply each with its own value, which is not shown in the figure, but which in general differs from that of other multipliers l5 and can also be negative, if necessary.

In summary, it is an essential feature of the invention that a digital IIR filter is used to generate an oscillation with the desired frequency f ₀ 12 is used. This is because every time the clock signal C is switched over, the IIR filter is reinitialized 12 , This reinitialization always takes place regardless of whether there is a change in the amplitude of the signal B or not. With each of these reinitializations, the state of the IIR filter 12 changed so that the IIR filter is always in a steady state for the signal component with the frequency f ₀ .

Another feature of the invention is that the duty cycle that the filter itself needs to operate is from the PLL control loop 8th is provided, which in turn receives its frequency-stable clock signal from the filter. The filter 2 is only switched on when the PLL control loop 8th has settled. Before that, the clock signal on the filter 2 past.

The principle of the invention works the better the higher the oversampling (oversampling).

The delay elements are preferably registers with a width of 8 bits.

1

input line

2

digital mode filter

3

Bypass line

4

band filter

5

Zero crossing detector

6

multiplexer

7

output for fundamental frequency

8th

PPL-locked loop for frequency multiplication

9

output for multiples frequency

10

Feedback line for clocking of band filter and

Zero crossing detector

11

FIR filter

12

IIR filters

13

delay

14

adder

15

multipliers

Claims (5)

Method for generating a signal pulse sequence (y (n)) with a predetermined stable fundamental frequency (f ₀ ) from a sequence of signal pulses (x (n)) whose frequency (f) fluctuates and which has spectral components, the frequency of which is at least a predetermined multiple the fundamental frequency (f ₀₎ is characterized in that the sequence of signal pulses (x (n)) a digital filter ( 2 ) is supplied, the pass band of which is around the fundamental frequency (f ₀ ) and which blocks by a predetermined half sampling frequency (f _a ) and which outputs a signed output signal (B) when excited, and a clock signal pulse () with every change of sign of the output signal (B) C) is generated. A method according to claim 1, characterized in that the digital filter ( 2 ) a band filter ( 4 ), which blocks at zero and half the sampling frequency (f _a ), and a zero crossing detector ( 5 ), which generates a clock signal pulse at each zero crossing. A method according to claim 2, characterized in that the band filter ( 4 ) an FIR filter ( 11 ) and an IIR filter ( 12 ), which are connected in series, the natural frequency of the IIR filter ( 12 ) is equal to the fundamental frequency (f ₀ ). Method according to one of the preceding claims, characterized in that the fundamental frequency (f ₀ ) by a PLL control loop ( 8th ) after the digital filter ( 2 ) is multiplied. A method according to claim 4, characterized in that the multiplied fundamental frequency (f ₀ ) according to the PLL control loop ( 8th ) as the sampling frequency of the bandpass filter ( 4 ) and the zero crossing detector ( 5 ) is used.