WO2002007313A1

WO2002007313A1 - Method and device for evaluating the power of a driver

Info

Publication number: WO2002007313A1
Application number: PCT/DE2001/002543
Authority: WO
Inventors: Ralf Klein
Original assignee: Infineon Technologies Ag
Priority date: 2000-07-17
Filing date: 2001-07-05
Publication date: 2002-01-24
Also published as: DE10034713A1

Abstract

A method and device for controlling the power of a driver, in particular a pad driver for highly integrated electronic circuits, whereby an evaluation time point, temporally coupled with the driver input signal is determined, in particular recurrently, during each system cycle. Said evaluation time point is used to determine whether the power of the driver is to be changed or can be retained.

Description

description

Method and device for assessing the strength of a driver

The invention relates to a method and a circuit arrangement for assessing the strength of a driver, in particular a pad driver for highly integrated electronic circuits, the driver, triggered by a driver input signal, increasing or decreasing a value of a driver output signal.

In connection with electronic circuits, so-called drivers are used to generate voltage signals that can usually have a high and a low voltage value and can therefore be interpreted as binary signals. Furthermore, the drivers can be used to trigger processes in other electronic assemblies or circuits within a short time by generating a voltage rise or a voltage drop. In both cases, a suitable driver requires that the value of its output signal must be able to increase or decrease to a certain level within a predetermined maximum time period. In today's digital circuits, data rates occur e.g. from tens of millions of bits per second. With today's technologies, the driver concept is particularly suitable for edge times from approx. 10 ns to 50 ns.

Drivers can be part of the circuits to be operated with the output signals of the respective driver or can be implemented by a separate circuit. In the latter case, a driver can serve to provide output signals for a plurality of circuits to be operated. In microelectronics, so-called pad drivers (output contact drivers) are used to operate integrated circuits such as microcontrollers, microprocessors, ASICs, memory chips or the like serve microelectronic components. Such circuits represent differently sized, mostly capacitive loads for the driver, so that differently strong electrical currents are required in order to generate the desired voltage increase or voltage drop. Usually the strength of a driver, ie the ability to control a certain load with the desired signal in a certain time, is designed for the worst case operating conditions (worst case). In addition to the load size of the circuit to be operated, the operating conditions also include the driver's supply voltage and the ambient temperature. Furthermore, there are fluctuations in the manufacture of drivers of the same type, which lead to different driver strengths.

Particularly in the case of electronic controls of motor vehicles, in which microelectronic components are increasingly being used, there are extreme fluctuations in the ambient temperature of the electronics. For example, the electronic

Controls work at temperatures from -40 ° C to 140 ° C.

If the strength of a driver is designed for the worst case, the driver (outside the worst case) is usually too strong, i.e. unnecessarily large currents and unnecessarily short rise and fall times of a voltage signal occur. The result is unnecessarily large field strengths of the electromagnetic field that is generated when the driver output signal is generated. Such electromagnetic

However, fields can interfere with the functionality of electronic circuits and, in extreme cases, lead to failure or even destruction. In order to adapt the strength of a driver to the respective load capacitance of a component to be operated with the driver, DE 44 41 523 C1 proposes a digital driver circuit with an output stage, the output stage having at least two output branches which are connected in parallel and have output transistors. Furthermore, a control means for controlling the output stage and an input device for inputting a measure number are provided. The user, for example the buyer of a pad driver, can now enter a number so that the strength of the digital driver circuit is adapted to the respective load capacity of the component to be operated by driving the output stage. Furthermore, the digital driver circuit has a measuring device in order to take into account the dependence of the strength of the driver on variables such as process parameters, for example oxide layer thicknesses or other parameters which are subject to fluctuations due to the manufacturing process of the driver circuit. Furthermore, the supply voltage of the driver circuit and the temperature can be taken into account. The measuring device has one or more measuring transistors connected to the

Supply voltage of the driver circuit are connected. However, the measuring transistor (s) must be arranged and designed such that the transistor current is measured under conditions which essentially correspond to the conditions which apply to the output branches of the driver circuit.

In order to be able to take into account the factors that influence the strength of the driver, two different devices are therefore provided, the input device and the measuring device. The production engineering effort is therefore relatively large. Furthermore, there is no guarantee that the measuring device will actually be exposed to the same manufacturing and operating conditions as the output branches of the driver. From US 4,567,378 a pad driver is known, which with a

Ramp generator is used to generate a ramp-like rising or falling reference signal. The ramp-like reference signal is generated by charging or discharging a capacitor, wherein the capacitor can be connected to a supply voltage or can be decoupled from it. US 4,567,378 teaches to compare whether the output signal of the driver rises or falls faster or slower than the ramp-like reference signal. Accordingly, a control signal can be generated so that the driver produces a faster or slower rise or fall in its output signal.

With this concept, the driver strength can be adapted to different capacitive loads. However, the ramp-like reference signal is subject to the influences of fluctuations in the process parameters during its manufacture. In particular, the capacitor of the ramp generator can receive different capacitance values and transistors for controlling the charging and discharging of the capacitor can be different depending on the manufacturing process. Furthermore, the capacitor is charged using a supply voltage. The ramp-like reference signal is therefore also dependent on the supply voltage.

The object of the present invention is to provide a method and a circuit arrangement of the type mentioned at the outset which make it possible to determine the strength of a driver independently of operating conditions, such as e.g. Ambient temperature and supply voltage, and regardless of fluctuations in process parameters of the manufacturing process to a desired value.

The object is achieved by a method with the features of claim 1 and by a circuit arrangement with the features of claim 12 solved. Further developments are the subject of the dependent claims.

An essential idea of the present invention is to determine an evaluation time which is temporally coupled to the driver input signal. Using the time of evaluation, it is then evaluated whether the strength of the driver corresponds to a specification. For example, the value of the driver output signal can then be influenced, i.e. the driver strength can be changed or another driver can be selected.

Coupling the time of evaluation with the driver input signal is understood to mean that, based on an event or a time of the driver input signal that can be determined in some other way, the time of evaluation can be clearly determined. For example, the driver is triggered by a rising edge of the driver input signal to increase the value of its output signal. The event to which the evaluation time point is then the rise in the driver input signal. In particular, the time of evaluation is then a time interval of a predetermined length after the time at which the driver input signal has reached a certain threshold value when it rises.

The coupling of the evaluation time with the driver input signal can be implemented in different ways. One possibility is that the driver input signal is supplied to both the driver and a determination unit for determining the time of evaluation. Another possibility is to use an external clock signal of a system clock. The driver input signal is then synchronized with an event of the clock signal, so that the time of evaluation can be determined based on this event. In general, the signal used in determining the evaluation time can be a periodic signal coupled to the driver input signal. Such periodic signals can be generated particularly precisely with a constant period or frequency, for example by an external quartz crystal. When operating microelectronic circuits, such a periodic signal, usually a clock signal, is usually present anyway.

A major advantage of coupling the driver input

The signal with the evaluation time lies in the fact that the evaluation time can be determined independently of the operating conditions of the driver, such as ambient temperature and supply voltage, and independently of fluctuations in the production parameters during the production of the driver. Of course, it is possible that there are slight dependencies on manufacturing parameters and operating conditions when determining the time of evaluation. However, these dependencies can be kept negligibly small without great technical effort. For example, the time of evaluation can be determined on the basis of a time of activation of the driver input signal, a time interval being specified which begins at the time of activation and the end of which defines the time of evaluation. Such a time interval, as will be described in detail by way of example, can be generated precisely and independently of operating and manufacturing conditions. In particular, at least part of the time interval is specified by specifying a fixed delay time. In this way, delays can be taken into account, for example, which occur when the driver has been activated until it begins to change the value of its driver output signal. The fixed delay time is preferably fixed in connection with the control of a specific driver, but is adjustable so that other drivers can also be controlled in a suitable manner. When determining the time of evaluation, it may not only be useful, as in the case described above, but also otherwise, to generate a time interval at the end of which the time of evaluation lies. For this purpose, the period and or the frequency of a periodic signal, such as the above-mentioned clock signal of a system clock, is preferably used.

In particular, a time signal is generated from the periodic signal, the length of which is a multiple or a fraction of the period and the length of which defines at least part of the length of the time interval. The generation of such a time signal is particularly simple if the periodic signal contains a time signal of a certain length that is regularly repeated. In the simplest case, the generation of a time signal can then even be omitted and one of the time signals contained in the periodic signal can be used to determine the time of evaluation. In particular, the start of the time signal can be synchronized with an event of the driver input signal, for example an edge. However, in order to be able to generate time signals of different lengths, and thus to be able to determine the time of evaluation differently, it is preferred to generate a plurality of time signals of different lengths from an existing time signal.

In a particularly preferred embodiment, the driver has a plurality of driver units, which can be released or blocked individually, and determined by the

Combination of released drivers is the strength of the driver. In this case, depending on the evaluation result obtained using the evaluation time, one or more driver units can be released and / or blocked, if this is necessary. When operating microelectronic components, a driver usually generates an output signal not only once, but again and again. To do this, the driver is repeatedly activated (triggered). In this case in particular, it is proposed that the assessment of whether the strength of the driver can be maintained is carried out several times in a first time phase, for example an initial phase. However, the evaluation does not have to be repeated after the first time phase, since a suitable driver strength has already been found or has been set. It is then sufficient to repeat the evaluation in order to check a suitable driver strength at predetermined larger time intervals. This is particularly advantageous if one and the same control circuit is used to control the strengths of several drivers. After the initial phase, the control circuit can thus monitor a large number of the drivers, for example one driver in each system cycle.

The time of evaluation can be used in different ways when evaluating the driver strength. In one embodiment, it is evaluated whether a secondary signal obtained from the driver output signal and / or an event of the driver output signal is present or is occurring before, at and / or after the evaluation time. For this purpose, an event detector is used, for example, which is designed to determine which signal is present earlier or is present at it, or whether the event occurs before, at and / or after the evaluation time. The secondary signal is generated in particular using a comparator which has a first comparator input for receiving the driver output signal and a second comparator input for receiving a reference signal. The comparator is designed to output an event signal when the driver output signal reaches and / or exceeds and / or falls below a value. tet, which is predetermined by the reference signal. The comparator is connected to the event detector in order to output the event signal to it as a secondary signal.

In a particularly preferred embodiment, the value of the driver output signal is evaluated at the time of the evaluation. For this purpose, in particular an evaluation unit is provided which has a triggerable comparator. The triggerable comparator is connected to a determination unit for determining the time of evaluation. Furthermore, the triggerable comparator has a first comparator input for receiving the driver output signal and a second comparator input for receiving a reference signal. At the time of the evaluation, the triggerable comparator is triggered and evaluates whether the value of the driver output signal is less than, equal to or greater than a value of the reference signal. The reference signal is in particular a voltage signal with a voltage value that is constant over time.

Both of the embodiments described above by way of example have the advantage of being able to be implemented with minimal production outlay. All that is required is simple feedback and evaluation of the driver output signal using the evaluation time. However, the strength lies in the simple technical solution: the driver's output signal is evaluated immediately.

This was made possible by the invention, which is based on the essential finding that an evaluation independent of operating conditions and manufacturing parameters is possible if an evaluation time coupled with the driver input signal is determined, which in turn is independent of the operating conditions and the manufacturing parameters. The circuit arrangement according to the invention in particular has an input signal input for receiving an input signal coupled to the driver input signal and an output signal input for receiving the driver output signal. Furthermore, a definition unit for determining an evaluation time is provided, which is connected to the input signal input. In addition, an evaluation unit is provided for evaluating whether the strength of the driver corresponds to a specification. The evaluation unit is connected to the definition unit and to the output signal input, the evaluation unit having an evaluation signal output for outputting an evaluation result determined at the time of the evaluation.

The circuit arrangement and the driver are preferably arranged on a common microelectronic chip. This has the advantage that the remaining minimal dependencies on production parameters can be reduced further. For example, the influence of manufacturing parameters in components of the driver and the control circuit is the same with regard to the response to edges of input signals. For example, an external clock signal that is supplied to both the driver or an assembly connected upstream of the driver and the fixing unit does not have different effects.

It is further preferred that the driver has a plurality of driver units which can be released or blocked individually, the combination of the released driver units determining the strength of the driver. Here, at least a first of the driver units and a second of the driver units are designed such that the first driver unit with half the strength of the second driver unit can contribute to the overall strength of the driver. This configuration allows setting the driver strength in equidistant

Stages.

In a further development, the evaluation unit is connected to a binary control unit for controlling the strength of the driver, the control unit being connected to the driver units in such a way that the first and second driver units can be controlled by binary control signals. In this development, the control signals of the binary control unit no longer need to be converted in order to be able to control the driver units. In particular, the binary control unit can have a binary counter, the counter reading of which is increased or decreased when the driver strength is to be changed. The counter reading then corresponds directly to the combination of released and blocked driver units.

The determination unit preferably has a delay stage for delaying a time signal in order to shift the evaluation point in time. The time signal is, for example, a signal characterized by its length, which can be used in the manner described above.

In a development of the circuit arrangement according to the invention, the setting unit has a time signal unit for generating and / or receiving an evaluation time signal, the length of which at least partially corresponds to the time difference between the evaluation time and a triggering time which can be derived from the driver input signal.

If the evaluation time is to be determined based on an event of the driver input signal or at a specific time of the driver input signal, there are basically any number of possibilities for determining the time of evaluation independently of operating conditions and Position parameters. As already described, there is the possibility of specifying the length of a time interval, the beginning of which is defined by the event of the driver input signal and the end of which defines the evaluation time. For example, part of the length of the time interval can be defined by the length of a time signal and another part can be specified by specifying a delay time (see above). The length of the time interval does not have to be fixed, however, but can be changed, for example, by the user of the circuit arrangement. A plurality of the time signals with different lengths can also be generated in order to have a plurality of time intervals available. In the latter case, a time interval can be assigned to one of several drivers to be controlled.

In a preferred embodiment, the setting unit is designed to receive and / or generate an input time signal, wherein the setting unit has a delay chain with a plurality of delay stages for delaying the input time signal and wherein outputs of the delay stages are connected to a logic unit which supplies the input time signal receives, so that evaluation time signals of different lengths are present at the outputs of the logic unit. The different evaluation time signals can then be used in particular by a multiplexer to evaluate the driver strengths of a plurality of drivers.

In one development, the delay chain is connected to a synchronization unit for synchronizing an event of the input time signal with an event of the delayed input time signal. This ensures that the delay in the input time signals takes place in a defined manner and fluctuations due to changes in the operating conditions and influences of manufacturing parameters. Fluctuations can be corrected or are excluded.

In another development, at least one of the delay stages has a control input for supplying a control signal and the synchronization unit is connected to the control input in order to control the delay. The synchronization unit can thus bring about the synchronization in the desired manner by controlling the delay stage. This allows, in particular after the start of operation of the

Driver and the circuit arrangement, adjusting the delay.

The present invention will now be described in more detail by means of exemplary embodiments with reference to the accompanying drawing. However, it is not limited to the exemplary embodiments. The individual figures in the drawing show:

1 shows a first exemplary embodiment of a circuit arrangement for regulating the strength of a driver,

2 shows a second exemplary embodiment of such a circuit arrangement,

3 shows an exemplary embodiment for a time signal generator according to FIGS. 1 and 2, FIG. 4 shows an exemplary embodiment for a driver that is scalable with regard to its strength, with a control unit for controlling the strength,

5 shows the time course of a control signal at the output of an event detector according to FIG. 1 or a comparator according to FIG. 2,

6 shows the time profile of the output signal at the driver according to FIGS. 1 and 2 and the time profile of a time signal at the output of a delay unit according to FIGS. 1 and 2, 7 shows another time profile of the signal shown in FIG. 5, FIG. 8 different profiles of the signals shown in FIG. 6, FIG. 9a) time profiles of control signals at the output up to a driver strength control unit according to FIGS. 1 and FIG. 9d) Fig. 2,

10 shows two temporal profiles of current strengths at the output of the driver according to FIG. 1 and FIG. 2 with different driver strengths, and

11 shows two temporal profiles of the output signal of the

1 and 2 according to the temporal profiles of the current strengths according to FIG. 10.

1 shows a control circuit 1 for controlling the strength of a driver 3. The driver 3 is arranged together with the control circuit 1 on a microelectronic chip 4. The control circuit 1 has a user input 16 for entering a user signal, which is used to control the driver 3 so that the driver 3 increases or decreases the voltage value at a driver output signal present at the driver output 8 to a predetermined value.

From the user output 16, the user signal does not reach the driver 3 directly. Rather, an input unit 15 is connected between the user input 16 and a driver input 6. The input unit 15 is also connected to a system clock input 17 of the control circuit 1.

The driver output 8 is connected to an output contact 10 to which external capacitive loads, in the example of FIGS. 1 and 2 the load 2, can be connected. Furthermore, the driver output 8 is connected to the inverting input of a compa- rators 5 connected. The comparator 5 also has a non-inverting input to which a reference voltage can be applied. The output of the comparator 5 is connected to an event detector 9.

The system clock input 17 serves to receive a clock signal, in particular to receive a clock signal with equidistant rectangular signals of the same length. In addition to the input unit 15, the system clock input 17 is also connected to the input of a time signal generator 13. The output of the time signal generator 13 is in turn connected or connectable to the input of a delay unit 11. The output of the delay unit 11 is connected to an input of the event detector 9.

An output of the event detector 9 is connected to the input of a driver strength control unit 7, the output of which is in turn connected to a control input of the driver 3.

Is the control circuit 1 as shown in Fig. 1 with the

Load 2 connected and the clock signal shown, for example, is present at the system clock input 17, the mode of operation of the control circuit 1 is as follows: If a trigger signal, for example a step-wise increasing voltage signal, is input at the user input 16, the input unit 15 receives the trigger signal and the system clock - signal. If the trigger signal is shifted in time with respect to the rising edge of the temporally nearest rectangular signal of the system clock signal, input unit 15 waits for the trigger signal to be output to driver 3 until the next rising edge of a rectangular signal of the system clock signal has arrived at input unit 15. In this way, the trigger signal is synchronized with the system clock. There is thus a temporal coupling between see the trigger signal present at driver input 6 and the system clock signal.

The system clock signal in turn is received by a clock signal source that is independent of operating conditions such as temperature and supply voltage. A suitable clock signal source is in particular a system clock generator controlled by a quartz crystal.

After driver 3 has received the trigger signal from input unit 15, driver 3, possibly with a delay, begins to increase the voltage at its driver output 8. Alternatively, in another embodiment, the driver 3 begins to lower the voltage at its driver output 8. The time course of the voltage at driver output 8 is shown as an example in FIG. 6: The continuous curve in FIG. 6 represents the output voltage Vout at driver output 8. At time t = 0, driver 3 received the trigger signal from input unit 15. However, the increase in Vout in the representation of FIG. 6 only begins after about 6 ns. Vout rises to approximately 2.5 V in the further course. For the example case explained here, driver 3 is required to have a value of 2.0 V after receiving the trigger signal Vout 12.5 ns. As can be seen from FIG. 6, Vout reaches this value earlier, for example after 10.5 ns. This means that the strength of the driver 3 is too large and therefore unnecessarily large electromagnetic field strengths are generated by the Vout increasing too quickly. The interferers associated therewith can disrupt the function of other assemblies on the chip 4 or electronic circuits arranged outside the chip 4.

The driver output signal Vout is therefore at the inverting input of the comparator 5 to regulate the driver strength created. The reference voltage Vref, which is present at the non-inverting input of the comparator 5, is set to the value 2.0 V (see horizontal broken line in FIG. 6). Therefore, when Vout reaches this value, the output signal of the comparator 5 changes from logic "high" to logic "low". In the example, this is the case after 10.5 ns. The event detector 9 registers the change from "high" to "low" almost without delay, so that after about 10.5 ns the event "Vout reaches the reference voltage value" is determined there.

As already described, the trigger signal transmitted from the input unit 15 to the driver 3 is synchronized in time with the rising edge of a square-wave signal of the system clock signal. The rising edge therefore reaches the time signal generator 13 at the same time that the trigger signal arrives at the driver 3. The instantaneous signal generator 13 generates a secondary square-wave signal of a certain length without delay from the square-wave signal. The length is predetermined and defines a part of the length of the time interval which should elapse from the input of the trigger signal on driver 3 to an evaluation time. In the case shown in Fig. 6, the secondary square wave has a length of 7.5 ns.

The delay unit 11 receives the secondary square-wave signal and delays its forwarding to the event detector by a predetermined delay time, which here is 5 ns. The dashed line in FIG. 6 shows the inverted signal of the delayed secondary square-wave signal, which is output by the delay unit 11 to the event detector 9. The time of evaluation, in the example of FIG. 6 at t = 12.5 ns, is thus defined by the sum of the length of the secondary square-wave signal and the delay time, the time of evaluation at the time of the trigger signal being received on Driver 3 or with the time of receipt of the increasing

Edge of the square wave signal is coupled to the input unit 15 and to the time signal generator 13.

After the event detector 9 has already detected the event “Vout reaches the reference voltage”, it detects the input of the falling edge of the secondary square-wave signal at the time of evaluation. This corresponds to the rising edge of the inverted secondary square-wave signal at the time t = 12.5 ns in FIG 6. Between the two events there is a time span of length Δt (see FIG. 6). In response to this time span, ie to the earlier occurrence of the event “Vout reaches the reference voltage”, the event detector 9 outputs this in FIG. 5 shown voltage signal EDout to the driver strength control unit 7.

Before the evaluation time, EDout had a voltage value that logically corresponds to the "high" state. After the evaluation time, EDout is now logically "low". Therefore, as will be explained in more detail, the driver strength control unit 7 lowers the strength of the driver 3 by one level.

The entire control cycle is repeated every time a trigger signal arrives at driver input 6, in the example described in every system cycle. As described, this is always a point in time at which the rising edge of a square-wave signal is received at the time signal generator 13.

A further control cycle is shown in FIG. 6. The trigger signal is received at driver input 6 at time t = 30 ns. The evaluation time associated therewith is later by the predetermined time period of 12.5 ns, ie at time t = 42.5 ns. Since Vout again reaches the value Vref = 2.0 V before the evaluation time, EDout remains logically "low", see above that the strength of the driver 3 is reduced again by one level.

A later period of the same control phase is shown in FIGS. 7 and 8. The numbers 14, 15 and 16, which indicate the 14th, 15th and 16th evaluation time, are plotted on the time axis. Accordingly, the 14th, 15th and 16th control cycle can be seen in FIGS. 7 and 8. Up to and including the 14th control cycle, event detector 9 has always determined that Vout had reached the reference voltage before the time of evaluation. Accordingly, EDout (shown in FIGS. 5 and 7) has been logic “low” since the end of the first control cycle. For the first time in the 15th control cycle, Vout only reaches the reference voltage after the evaluation time. Therefore, EDout becomes logic “high” and the Driver 3 power increased again by one level.

In the 16th control cycle, Vout reaches the reference voltage again before the evaluation time, which is why EDout again becomes logic “low”. Thus, after the 14th control cycle, the driver 3 has reached a state in which its strength fluctuates around a mean value with a small amplitude.

An embodiment of the driver 3 and its control by the driver strength control unit 7 is shown by way of example in FIG. 4. Driver 3 has five driver units 45a-45e. The driver unit 45a has half the strength of the driver unit 45b, the driver unit 45b has half the strength of the driver unit 45c and so on. The driver units 45a-45e can be activated or deactivated individually. In general, such a driver that is scalable in terms of its strength has n sub-drivers that can be activated individually. The sub-drivers are implemented, for example, as MOSFETs (metal oxide semiconductor field effect transistors with insulated gate electrodes). In this case, with the same Channel length in the MOSFET, the possible contribution to the overall strength of the driver is set by the channel width W. The channel width W _{x of} the weakest driver part is therefore half the channel width W _{2 of} the second weakest driver part. In general

Wi = 2 • i_ _! i = 2, ..., n.

The following applies to the total channel width of all sub-drivers or, accordingly, to the overall strength of the driver:

Is the channel width of the transistor by the total length i ^ m _t _gesa words, the following applies:

Altogether k strength and width combinations with widths greater than zero are therefore possible, whereby the following applies:

k = 2 ⁿ - 1

W ^v, ι- = W "mι • n'2 '" W ^, πιι • n'3W " ^, ιιιι • n' ^{■ ■ ■} 'W" ^ total

^w _m i ^st in the width of the weakest part of the driver, the range of W to W _min that _total can be traversed in steps, the width W _min.

In the example of FIG. 4, driver 3 has five driver units 45a-45e, so that the strength of driver 3 is 31 steps. between the strength of the weakest driver unit 45a and the maximum strength of the driver 3 can be set. The difference in strength between two stages is equal to the strength of the weakest driver unit 45a.

The driver units 45a-45e each have three inputs. A first input is identical to or connected to driver input 6. A second input is a reset input 41 for resetting driver units 45a-45e to their initial state, which is preferably the state in which all driver units 45a-45e are activated. A third input of the driver units 45a-45e is connected to the driver strength control unit 7 via a bit line 43a-43e. Via the bit lines 43a-43e, the driver strength control unit 7 can transmit a bit signal, i.e. a binary

Signal transmitted to the driver units 45a-45e. If the binary signal is logically “high” or “1”, the respective driver unit 45a-45e is deactivated. In the opposite case, it is activated. The driver strength control unit 7 preferably has a binary five-digit counter, with states between the counter reading “0” and the counter reading “31” being possible accordingly. Counter reading "0" corresponds to "0" as a control signal on each of the bit lines 43a-43e, i.e. all driver units 45a-45e are activated. Counter reading “31” would accordingly correspond to the deactivated state of all driver units 45a-45e. However, this state does not make sense during operation of driver 3. Therefore, the highest permitted counter reading is “30”, which corresponds to the activation of only the weakest driver unit 45a.

If in the exemplary embodiment described with reference to FIG. 1 and in the exemplary embodiment still to be described with reference to FIG. 2, the signal is logically "high" at the input of the driver strength control unit 7 at a given point in time after the evaluation time, the counter reading changes "1" lowered. Conversely, the counter reading is increased by "1" if the input signal logically corresponds to "low".

9a) to d) show the binary signals at the output of the driver strength control unit 7, which are output to the driver units 45a-45d in the control phase described above. The signal output to the driver unit 45e is logic "0" during the entire control phase, i.e. the driver unit 45e is always activated. Fig. 9a) shows the binary signal output to the driver unit 45a via the bit line 43a, Fig. 9b) shows the signal output to the driver unit 45b via the bit line 43b, etc. Along the time axis in Fig. 9 (the horizontal axis) are Evaluation times of the first 16 control cycles marked. It can be seen that from the first to the 14th control cycle the sum signal of the four binary signals is increased by "1". This corresponds to a reduction in the driver strength of driver 3 by one step each. Only in the 15th control cycle is the sum signal lowered again by "1", which corresponds to the representation of the signal EDout in FIG. 7.

FIG. 3 shows an exemplary embodiment for the time signal generator 13 (FIG. 1). A delay chain 27 with five delay stages 29a-29e is provided. The input of the delay stage 29a is connected to the system clock input 17. The output of the delay stage 29a is connected to the input of the delay stage 29b and so on. The output of the delay stage 29e is connected to an input of a phase detector 31. Another input of the phase detector 31 is connected to the output of an inverter 35, the input of which is in turn connected to the system clock input 17. An output of the phase detector 31 is connected to an input of a delay controller 33. An output of the delay control 33 is connected to a control input 30a-30e of the delay stages 29a-29e. Furthermore, the output of the inverter 35 is connected to an input of a NOR gate 37a-37d. Another input of the NOR gates 37a-37d is connected to a corresponding output of one of the delay stages 29a-29d. Outputs of the NOR gates 37a-37d are connected to the time signal output 14 of the time signal generator 13. Another connection exists directly between the system clock input 17 and the time signal output 14.

A multiplexer control 25 allows each of the five partial outputs of the time signal output 14 to be connected individually to a connecting line connection. The connecting line connection leads in particular to the delay unit 11 (FIG. 1).

If a square-wave signal arrives at the system clock input 17, it is passed through the delay chain 27. Each of the delay stages 29a-29e delays the square wave signal by the same amount of time. At a certain point in time, which corresponds to the delay by the delay chain 27, the rising edge of the square-wave signal delayed five times arrives at the phase detector 31. The phase detector 31 determines whether this rising edge is received simultaneously or before or after the falling edge of the inverted square-wave signal received by the inverter 35. If these two edges do not come in at the same time, a corresponding signal is output to the delay control 33, which in turn sets the delay via a control signal to the inputs 30a-30e of the delay stages 29a-29e such that the time interval between the arrival of the two Flanks on the phase detector 31 becomes smaller and / or disappears. After a few control cycles at the latest, the two edges then arrive simultaneously at the phase detector 31. In this state, four rectangular pulses delayed by 1/5 the length of the rectangular pulse at the system clock input 17 are then available at the outputs of the delay stages 29a-29d. By means of a logical non-OR link (NOR) in the NOR gates 37a-37d with the inverted, undelayed square wave signal, four secondary square wave signals of different lengths are then available at the outputs of the NOR gates 37a-37d. These signals, which are available for tapping at the time signal output 14, are synchronized with one another in such a way that their rising edges are present at the time signal output 14 at the same time. Furthermore, the undelayed square wave signal is also present at the time signal output 14. The lengths of the five square-wave signals present there are 1/5 to 5/5 the length of the undelayed square-wave signal, ie the square-wave signal of the system clock.

Depending on requirements, one of the time signals of different lengths can thus be tapped to determine the time of evaluation, the start of the time signal being synchronized with the start or the rising edge of the undelayed square-wave signal. Depending on the application, this gives the option of specifying a different evaluation time and thus changing the strength of the driver 3. Furthermore or alternatively, several of the drivers 3 can be controlled with the time signals of the time signal generator 13, the controlled drivers also being able to tap part or all of the same time signal. In this way, the area of an integrated circuit can be kept significantly smaller than would be the case with one time signal generator per driver.

A significant advantage of the time signal generator 13 described is the exact generation of time signals, the length of which is clearly specified by an external square wave signal. Furthermore, the starting time of the various Time signals synchronized. It can therefore be influenced by

Manufacturing parameters and operating conditions reliably generate the respective time signal of the desired length.

Furthermore, the described DLL circuit (Delay-Locked Loop) allows the pulse length to be divided for a given pulse length of a pulse signal present at its input, for example the square-wave signal. The length of the external pulse therefore does not limit the possibilities when determining the time of evaluation. Furthermore, the system clock signal of a high-precision external system clock can be used as an input signal. Since the lengths of the square-wave signals or the pulse lengths of such a clock signal match with high precision and are independent of manufacturing parameters and operating conditions, the evaluation point can be done by itself

Specifying the desired time signal length at the output of the time signal generator 13 and optionally also by specifying a delay time. Manufacturing parameters and operating conditions are then without influence.

As an alternative or in addition, frequency dividers can also be provided, which can also divide the frequency of the external system clock signal or multiply the length of the pulse durations independently of manufacturing parameters and operating conditions. In particular if there is the possibility of freely changing the delay time by a delay unit such as the delay unit 11 in Fig. 1, a time interval of any length can be specified, the beginning of which is determined by the input of the trigger signal to the driver to be controlled and at the end of which Evaluation time is.

In the simplest case, the time signal generator can only consist of a signal line that passes an external time signal, for example to the delay unit 11. ne such solution is useful if no time signals are required that are shorter than the length of the external

Time signal.

In a preferred development of the time signal generator 13 according to FIG. 3, the rising edge of the square-wave signal present at the system clock input 17 is delayed in the manner described by the delay chain 27, but the falling edge of the square-wave signal is not or only slightly delayed. In this development, there is no risk of overlapping a delayed time signal at the output of delay stage 29e with a non-delayed time signal following the delayed time signal, the associated inverted signal of which could be present at the output of inverter 35. Malfunctions can thus be avoided precisely when the delay time has not yet been set in the desired manner by the delay controller 33. It is therefore guaranteed that the delay time can always be set correctly.

10 and 11 show the currents or voltages at driver output 8 at the beginning of the control phase and after the 14th control cycle. In FIG. 10 the line shown with short dashes corresponds to the current at the beginning of the regulation phase, in FIG. 11 the curve shown with uniformly long dashes corresponds to the voltage at the beginning of the regulation phase. It can be seen that both the temporal increase in the current and the value of the maximum flowing current could be reduced by the regulation (FIG. 10). This corresponds to the flatter rise in the voltage at driver output 6 (FIG. 11). The designation "t _a " in FIG. 11 marks the point in time at which the trigger signal arrives at driver input 6.

An alternative embodiment of a control circuit is shown in FIG. The control circuit 21 is largely correct with the control circuit 1 (Fig. 1). However, the

Comparator 5 and the event detector 9 replaced by a triggerable comparator 19. An inverting input of the triggerable comparator 19 is connected to the driver output 8. A reference voltage can be applied or applied to the non-inverting input of the triggerable comparator 19. Furthermore, the triggerable comparator 19 has a trigger input which is connected to the output of the delay unit 11.

The control circuit 21 operates as follows: The triggerable comparator 19 is triggered by the falling edge of the time signal present at the output of the delay unit 11, i.e. the time at which the edge is applied to the trigger input is the time of evaluation. At this time, a comparison is made as to whether the output voltage at driver output 8 is greater than, equal to or less than the reference voltage. Accordingly, a control signal is output at the output of the triggerable comparator 19, which is either logically "high" or "low".

The same rule can be obtained with the control circuit 21 as can be achieved with the control circuit 1. Therefore, the course of the curves according to FIGS. 5 to 11 corresponds to the control circuit 21. In order to clarify the variant in the evaluation of the driver output signal, the voltage difference ΔV is shown in FIG. 6, right-hand section of the diagram, which the triggerable comparator 19 at the time of evaluation t = 42.5 ns. Since ΔV, as in the previous and subsequent control cycles, is greater than zero, ie the driver output voltage is greater than the reference voltage, the triggerable comparator outputs an output signal according to FIG. 5, which logically corresponds to the "low" state. The control circuits 1; described with reference to FIGS. 1 and 2; 21 can be used in an analogous manner if the driver 3 is activated in order to output an output signal, the value of which is reduced, for example generating a falling edge of a voltage signal. A strength control of a driver can also be implemented in a corresponding manner, which driver can generate both rising and falling edges. The strength of the driver for falling edges and for rising edges can be the same or different. Accordingly, it is possible to set the strength of the driver by means of a single driver strength control unit 7, or a plurality of the driver strength control units 7 can be provided. Different strengths of the driver can also be set by a single driver strength control unit 7, for example by using a multiplexer, which sequentially applies the output signal of the driver strength control unit to different control inputs of the driver.

The invention enables a driver strength control to be implemented which means only low circuit complexity. There is great freedom in specifying the time of evaluation. Furthermore, the inertia of the driver can be taken into account and the value of the driver output signal at the time of evaluation can be freely selected. It is therefore not necessary to define the desired slope of the output signal using certain percentage values of the maximum increase.

Claims

claims

1. A method for assessing the strength of a driver (3), in particular a pad driver for highly integrated electronic circuits, the driver (3), triggered by a driver input signal, increasing or decreasing a value of a driver output signal, in which, in particular recurrently,

- An evaluation time coupled with the driver input signal is determined and

- Using the evaluation time it is evaluated whether the strength of the driver (3) corresponds to a specification.

2. The method of claim 1, d a d u r c h g e k e n n z e i c h n e t that the value of the driver output signal is influenced according to the evaluation result.

3. The method of claim 1 or 2 d a d u r c h g e k e n n z e i c h n e t that at the time of evaluation the value of the driver output

Signal is evaluated.

4. The method of claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that it is evaluated whether a secondary signal obtained from the driver output signal and / or an event of the driver output signal is present or occurs before, on and / or after the evaluation time.

5. The method according to any one of claims 1 to 4, characterized in that a periodic signal coupled to the driver input signal is used in the determination of the evaluation time. Det, in particular a clock signal of a system clock for a system with microelectronic assemblies.

6. The method of claim 5, d a d u r c h g e k e n n z e i c h n e t that a time interval is generated using the period and / or the frequency of the periodic signal and that the evaluation time is at the end of the time interval.

7. The method of claim 6, d a d u r c h g e k e n n z e i c h n e t that a time signal is generated from the periodic signal, the length of which is a multiple or a fraction of the period and the length of which defines at least part of the length of the time interval.

8. The method according to any one of claims 1 to 7, characterized in that the driver input signal drives the driver (3) at a control time, so that the driver (3), possibly delayed, begins to change the value of the driver output signal , and that a time interval is specified which begins at the activation time and by the end of which the evaluation time is defined.

9. The method according to claim 8, d a d u r c h g e k e n n z e i c h n e t that at least part of the time interval is specified by specifying a fixed delay time.

10. The method according to any one of claims 1 to 9, characterized in that the driver (3) has a plurality of driver units (45a-45e) which can be released or blocked individually, that the combination of the released driver units (45a 45e) determines the strength of the driver (3) and that, depending on the evaluation result, one or more of the driver units (45a-45e) may be released and / or blocked.

11. The method according to any one of claims 1 to 10, that the evaluation is carried out several times in a first time phase and that the evaluation is repeated at predetermined larger intervals to check a suitable driver strength.

12. viewing arrangement (1; 21) for assessing the strength of a driver (3), in particular a pad driver for highly integrated electronic circuits, the driver (3), triggered by a driver input signal, increasing or decreasing a value of a driver output signal

- an input signal input (17) for receiving an input signal coupled to the driver input signal, - an output signal input (8) for receiving the driver output signal,

- A determination unit (11, 13) for determining an evaluation time, which is connected to the input signal input (17), and - An evaluation unit (5, 9; 19) for evaluating whether the strength of the driver (3) corresponds to a specification, whereby the evaluation unit (5, 9; 19) is connected to the definition unit (11, 13) and to the output signal input (8) and the evaluation unit (5, 9; 19) has an evaluation signal output for outputting an evaluation result determined at the time of the evaluation ,

13. scarf device arrangement according to claim 12, characterized in that a device (7) for influencing the strength of the driver

(3) is provided, which is connected to the evaluation signal output. ^*

14. Circuit arrangement according to claim 12 or 13, so that the circuit arrangement (1) and the driver (3) are arranged on a common microelectronic chip (4).

15. Circuit arrangement according to claim 12 to 14, characterized in that the driver (3) has a plurality of driver units (45a-45e) which can be released or locked individually, the combination of the released driver units (45a-45e) being the strength of the Driver (3) determines, and that a first (45a-45d) of the driver units (45a-45e) with half the strength of a second (45b-45e) of the driver units (45a-45e) can contribute to the overall strength of the driver (3).

16. Circuit arrangement according to claim 15, characterized in that the evaluation unit (5, 9; 19) is connected to a binary control unit (7) for controlling the strength of the driver (3), and that the control unit (7) is connected to the driver unit in this way. units (45a-45e) that the first (45a-45d) and the second (45b-45e) driver unit can be controlled by binary control signals and the strength of the driver (3) can be set in equidistant steps.

17. Circuit arrangement according to one of claims 12 to 16, characterized in that the fixing unit (11, 13) has a delay unit (11) for delaying a time signal in order to shift the time of evaluation.

18. Circuit arrangement according to one of claims 12 to 17, characterized in that the setting unit (11, 13) has a time signal unit (13) for generating and / or receiving an evaluation time signal, the length of which is at least partially the time difference between the evaluation time and one of the driver input signal derivable trigger time corresponds.

19. Circuit arrangement according to claim 18, characterized in that the fixing unit (11, 13) is designed to receive and / or generate an input time signal that the fixing unit (11, 13) has a delay chain (27) with a plurality of delay stages (29a -29e) for delaying the input time signal and that outputs of the delay stages (29a-29e) are connected to a logic unit (37a-37d) which receives the input time signal or a signal derived therefrom, so that at an output (14) Logic unit (37a-37d) have evaluation time signals of different lengths.

20. Circuit arrangement according to claim 19, so that the delay chain (27) is connected to a synchronization unit (31, 33) for synchronizing an event of the input time signal with an event of the delayed input time signal.

21. Circuit arrangement according to claim 20, characterized in that at least one of the delay stages (29a-29e) has a control input (30a-30e) for supplying a control signal and that the synchronization unit (31, 33) is connected to the control input (30a-30e) to control the delay.

22. Circuit arrangement according to one of claims 18 to 21, characterized in that the fixing unit (11, 13) is designed to provide a plurality of the output time signals at a signal output (14), and in that a plurality of the drivers with the signal output (14 ) are connected and / or connectable.

23. Circuit arrangement according to one of claims 12 to 22, characterized in that the evaluation unit (5, 9) has an event detector (9) which is designed to determine whether an event which can be determined from the driver output signal occurs before, on and / or after the evaluation time ,

24. Circuit arrangement according to claim 23, so that the evaluation unit (5, 9) has a comparator (5) which has a first comparator input for receiving the driver output signal and a second comparator input for

Receiving a reference signal, the comparator (5) being designed to output an input signal when the driver output signal reaches and / or exceeds and / or falls below a value which is predetermined by the reference signal, and wherein the comparator with the event detector ( 9) is connected to output the event signal to it.

25. Circuit arrangement according to one of claims 12 to 22, d a d u r c h g e k e n n z e i c h n e t that the evaluation unit (19) has a triggerable comparator (19) which

a trigger input connected to the definition unit (11, 13),

- a first comparator input for receiving the driver output signal and has a second comparator input for receiving a reference signal.