DE10334805B4 - Analog multiplier circuit - Google Patents

Abstract

Apparatus for analog multiplying two input signals (V _in1 , V _in2 ), comprising:
- At least a first (T1) and at least one second (T2) field effect transistor, wherein the two field effect transistors (T1, T2) have the same conductivity type and a substantially equal transconductance factor and a substantially same threshold voltage and in each case a source (S1, S2 ), a gate (G1, G2) and a drain terminal (D1, D2), wherein the source terminal (S1) of the first field effect transistor (T1) is electrically connected to the source terminal (S2) of the second Feldeftekttransistors (T2), wherein the Gate terminal (G1) of the first field effect transistor (T1) forms a first input node (E1) and the gate terminal (G2) of the second field effect transistor (T2) forms a second input node (E2) and a first V _{in1 of} the input signals forms a potential difference between the first (E1) and the second (E2) input node and a second V _{in2 of} the input signals as the drain-source voltage (V _DS ) of the first field effect transistor rs (T1) and the second field effect transistor (T2) can be applied; and
- At least one current difference forming device, which for ...

Description

The The present invention relates to an apparatus and a method for analog multiplying two input signals.

A formally correct multiplication of two electrical signals was so far only possible in the digital domain, which is one of many reasons for the Advance of digital signal processing is. The absence of an analog Multiplication has resulted in a number of auxiliary circuits, with which approximates a multiplication, but not formally correct accomplished can be. Most frequently Such circuits are used in the classical receiver concept, the so-called Superhetprinzip, where in the mixing stage an analogous Multiplication under the boundary condition of an extreme signal dynamics is required. There are approximately 8 billion recipients in the world Use, which amounts to approximately 5 billion radios, 2 billion television sets and 1 Distribute billion mobile phones. There is therefore a great need on circuits that one possible can perform correct multiplication of two electrical input signals.

Brad Gilbert proposed a circuit for analog multiplication of two signals in the 1960s, which was incorporated into the literature as a so-called Gilbert cell. Within 30 years, the Gilbert cell has become established as a standard for analog multiplier circuits. A simple schematic representation of such a known Gilbert cell is in 1 shown. The two lower transistors form a differential amplifier, which amplifies the input signal V _in1 . With the quartet of four switch _transistors, the output current of the differential amplifier can be inverted as a function of the second input voltage V _in2 .

2 shows the static characteristic of a Gilbert cell with the voltage V _in2 as a parameter. How out 2 can be seen, the linear range of the characteristic is limited to about ± 50mV to V _in1 = 0. By inserting emitter resistors in the differential amplifier, it is possible to extend the linear range, but then increases to the same extent the noise figure, so that a substantial expansion of the dynamic range by emitter resistors is not possible.

The publication US 6 255 889 describes the application of reactive feedback networks to a four-quadrant multiplier used as a mixer.

The publication DE 100 32 802 describes a multiplier circuit for multiplying two input signals, in which two transistor pairs couple a first input to an output of the multiplier, wherein load connections of the transistor pairs are connected via a current mirror to a second input of the multiplier.

task The invention is an apparatus and a method for analog To provide multiplication of two input signals, with which a formally correct multiplication of two input signals is possible. It is another object of the invention to provide a device for analog To provide multiplication of two input signals, which compared to the previous solutions an improved dynamic range and increased linearity range having.

These Tasks are performed according to the present Invention by an apparatus for analog multiplying two Input signals with the specified in claim 1 and claim 13 Features and method for analog multiplying two input signals solved with the features specified in claim 23. Preferred embodiments are the subject of the dependent Claims.

• – zumindest einen ersten und zumindest einen zweiten Feldeftekttransistor, wobei die beiden Feldeffekttransistoren den gleichen Leitfähigkeitstyp (n- bzw. p-Kanal FET) und einen im wesentlichen gleichen Transkonduktanzfaktor und eine im wesentlichen gleiche Schwellspannung aufweisen und jeweils einen Source-, einen Gate- und einen Drainanschluss aufweisen, wobei der Sourceanschluss des ersten Feldeffekttransistors elektrisch mit dem Sourceanschluss des zweiten Feldeffekttransistors verbunden ist, wobei der Gateanschluss des ersten Feldeffekttransistors einen ersten Eingangsknoten und der Gateanschluss des zweiten Feldeffekttransistors einen zweiten Eingangsknoten bildet und ein erstes V_in1 der Eingangssignale als Potentialdifferenz zwischen dem ersten und dem zweiten Eingangsknoten anlegbar ist und ein zweites V_in2 der Eingangssignale als Drain-Source-Spannung des ersten Feldeffekttransistors und des zweiten Feldeffekttransistors anlegbar ist; und
• – zumindest eine Stromdifferenzbildungseinrichtung, welche zum Bilden eines dem Produkt der beiden Eingangssignale V_in1, V_in2 proportionalem Ausgangssignal ΔI_D = I_D1 – I_D2 durch Bilden der Differenz zwischen einer Drain-Source-Stromstärke I_D1 des ersten Feldeffekttransistors und einer Drain-Source-Stromstärke I_D2 des zweiten Feldeffekttransistors ausgelegt ist.

According to the invention there is provided an apparatus for analog multiplying two input signals, comprising:

• At least one first and at least one second field effect transistor, wherein the two field effect transistors have the same conductivity type (n- or p-channel FET) and a substantially equal transconductance factor and a substantially equal threshold voltage and a respective source, a gate and a drain terminal, wherein the source terminal of the first field effect transistor is electrically connected to the source terminal of the second field effect transistor, wherein the gate terminal of the first field effect transistor, a first input node and the gate terminal the second field effect transistor forms a second input node and a first V _{in1 of} the input signals can be applied as a potential difference between the first and the second input node and a second V _{in2 of} the input signals can be applied as drain-source voltage of the first field effect transistor and the second field effect transistor; and
• - At least one current difference forming means, which for forming a product of the two input signals V _in1 , V _in2 proportional output signal .DELTA.I _D = I _D1 - I _D2 by forming the difference between a drain-source current I _{D1 of} the first field effect transistor and a drain-source Current I _{D2 of} the second field effect transistor is designed.

In This application is under field effect transistors with substantially same transconductance factor and threshold voltage in particular Field effect transistors understood whose transconductance factors and threshold voltages in the context of typical manufacturing technology conditional deviations lie. The field effect transistors can, for example classic junction FETs or MOSFETs as they are in integrated Circuits often be applied.

wobei B₀ der Transkonduktanzfaktor, V_TH die Schwellspannung, V_GS die Gate-Source-Spannung und V_DS die Drain-Source-Spannung bezeichnen.A field effect transistor can be operated in simplified manner in three different work areas, namely in the so-called stopband, resistance range and saturation range. In the resistance region, which is also referred to as the triode region, the drain current I _{D of} the field effect transistor follows the relationship:

where B _{0 is} the transconductance factor, V _{TH is} the threshold voltage, V _{GS is} the gate-source voltage, and V _{DS is} the drain-source voltage.

For the difference of the drain currents of the first I _D1 and the second I _D2 field effect transistor of the transistor pair then applies: .DELTA.I D = I D1 - I D2 = B 0 · (V GS1 - V GS2 ) · V DS (2) wherein V _{DS denote} the drain-source voltage of the first and the second field effect transistor, V _GS1, the gate-source voltage of the first and V _GS2, the gate-source voltage of the second field effect transistor.

The difference between the gate-source voltages of the first and the second field-effect transistor V _{GS1 -V GS2} or the potential difference between the first and the second input node represents the first input signal V _in1 . The second input signal V _in2 is determined by the drain-source voltage V _{DS given} the two field effect transistors. The equation (2) can be rewritten as follows: .DELTA.I D = B 0 · V in1 · V in 2 (3)

As can be seen from equation (3), the output ΔI _{D is} proportional to the product of the first and second input signals. Thus, a formally correct multiplication of two input signals V _in1 and V _{in2 is} possible.

The current difference forming device preferably comprises at least one voltage follower device with one voltage follower and two voltage follower outputs, wherein the second input signal V _in2 can be applied to the voltage follower input by applying a voltage follower input signal. The voltage follower input signal may be current or voltage signal, which is proportional to V _in2 .

• – der Emitter und der Kollektor des ersten und des zweiten Bipolartransistors den gleichen Leitfähigkeitstyp wie derjenige des ersten und des zweiten Feldeffekttransistors aufweisen,
• – der Emitter des ersten Bipolartransistors mit dem Drainanschluss des ersten Feldeffekttransistors und der Emitter des zweiten Bipolartransistors mit dem Drainanschluss des zweiten Feldeftekttransistors elektrisch verbunden ist,
• – die Basis des ersten Bipolartransistors mit der Basis des zweiten Bipolartransistors elektrisch verbunden ist und
• – die Basen der Bipolartransistoren den Spannungsfolgereingang bilden.

Furthermore, the voltage follower device preferably comprises a first and a second bipolar transistor each having an emitter, a base and a collector, wherein

• The emitter and the collector of the first and the second bipolar transistor have the same conductivity type as those of the first and the second field effect transistor,
• The emitter of the first bipolar transistor is electrically connected to the drain terminal of the first field effect transistor and the emitter of the second bipolar transistor is electrically connected to the drain terminal of the second field effect transistor,
• - The base of the first bipolar transistor is electrically connected to the base of the second bipolar transistor and
• - The bases of the bipolar transistors form the voltage follower input.

Preferably, the collector of the first bipolar transistor forms a first output node and the collector terminal of the second bipolar transistor forms a second output node, and the current difference forming means is adapted to obtain the output ΔI _D by taking the difference between a collector-emitter current of the first bipolar transistor and a collector-emitter current of the second bipolar transistor.

A alternative embodiment the voltage follower device has field effect transistors instead of bipolar transistors on. In particular, allows the use of field effect transistors that the preferred device according to the invention can be realized as a monolithic integrated circuit. In In this case, however, the body effect must be considered, which to an additional undesirable nonlinearity to lead can.

• – der dritte und der vierte Feldeffekttransistor den gleichen Leitfähigkeitstyp wie derjenige des ersten und des zweiten Feldeftekttransistors aufweisen,
• – der Sourceanschluss des dritten Feldeffekttransistors mit dem Drainanschluss des ersten Feldeftekttransistors und der der Sourceanschluss des vierten Feldeffekttransistors mit dem Drainanschluss des zweiten Feldeffekttransistors elektrisch verbunden ist,
• – der Gateanschluss des dritten Feldeffekttransistors mit dem Gateanschluss des vierten Feldeffekttransistors elektrisch verbunden ist und
• – die Gateanschlüsse des dritten und vierten Feldeffekttransistors den Spannungsfolgereingang bilden.

Preferably, the voltage follower comprises a third and a fourth field effect transistor, each having a source, a gate and a drain terminal, wherein

• The third and fourth field effect transistors have the same conductivity type as those of the first and second field effect transistors,
• The source terminal of the third field effect transistor is electrically connected to the drain terminal of the first field effect transistor and the source terminal of the fourth field effect transistor is electrically connected to the drain terminal of the second field effect transistor,
• - The gate terminal of the third field effect transistor is electrically connected to the gate terminal of the fourth field effect transistor and
• - The gate terminals of the third and fourth field effect transistor form the voltage follower input.

Preferably, the drain terminal of the third field effect transistor forms a first output node, and the drain terminal of the fourth field effect transistor forms a second output node, and the current difference forming means is configured to output the signal ΔI _D by taking the difference between a drain-source current of the third field effect transistor and a drain-source current of the fourth field effect transistor.

More preferably, the current difference forming device comprises at least one current mirror device. Preferably, the current mirror device is designed to form a mirror current of the same current intensity flowing to a current flowing into the first output node of the voltage follower device, which current flows into the second output node of the voltage follower device, wherein the output signal ΔI _{D can be} tapped off at the second output node.

In an alternative embodiment, the current mirror means is arranged to form a mirror current of the same current flowing to a current flowing in the second output node of the voltage follower, which current flows into the first output node of the voltage follower, the negative output signal ΔI _{D being} tapped at the first output node.

Such Current mirror circuits are in integrated circuit technology known. A detailed description The current mirror circuits are described, for example, in the book "Analysis and Design of Analog Integrated Circuits "by Paul R. Gray and Robert G. Meyer, published in 1984 by John Wiley and Sons, chapter 4, the disclosure of which is in this respect as integral Part of the present application is to be considered.

Preferably the current mirror device has two field-effect transistors opposite conductivity type as that of the first and the second field effect transistor.

According to one another preferred embodiment the current mirror device has two bipolar transistors each of a base, an emitter and a collector, wherein the emitter and the base of the bipolar transistors of the current mirror device the opposite conductivity type as those of the first and the second field effect transistor.

According to one another preferred embodiment the current difference forming device comprises at least one transformer with two symmetrical input windings.

In the case of the preferred devices according to the invention described above, only positive voltage values are permitted for the drain-source voltage of the first and the second field-effect transistor, ie the input signal V _in2 may only be positive.

• – zumindest zwei Transistorpaare mit jeweils einem ersten und einem zweiten Feldeffekttransistor, wobei
• – die Feldeffekttransistoren der beiden Transistorpaare den gleichen Leitfähigkeitstyp und einen im wesentlichen gleichen Transkonduktanzfaktor und eine im wesentlichen gleiche Schwellspannung aufweisen und jeweils einen Source-, einen Gate- und einen Drainanschluss aufweisen,
• – die Sourceanschlüsse der ersten und der zweiten Feleffekttransistoren des ersten und des zweiten Transistorpaars elektrisch miteinander verbunden sind;
• – der Gateanschluss des ersten Feldeftekttransistors des ersten Transistorpaars mit dem Gateanschluss des ersten Feldeftekttransistors des zweiten Transistorpaars elektrisch verbunden ist und den ersten Eingangsknoten bildet;
• – der Gateanschluss des zweiten Feldeftekttransistor des ersten Transistorpaars mit dem Gateanschluss des zweiten Feldeftekttransistors des zweiten Transistorpaars elektrisch verbunden ist und den zweiten Eingangsknoten bildet;
• – ein erstes V_in1 der Eingangssignale als Potentialdifferenz zwischen dem ersten und dem zweiten Eingangsknoten anlegbar ist;
• – ein zweites V_in2 der Eingangssignale als Spannungsunterschied V_in2 zwischen einer Drain-Source-Spannung V I / DS = V II / DS + V_in2 des ersten Feldeftekttransistors und des zweiten Feldeftekttransistors des ersten Transistorpaars gegenüber einer Drain-Source-Spannung V II / DS des ersten Feldeftekttransistors und des zweiten Feldeftekttransistors des zweiten Transistorpaars anlegbar ist; und
• – zumindest eine Stromdifferenzbildungseinrichtung, welche zum Bilden eines dem Produkt der beiden Eingangssignale V_in1, V_in2 proportionalem Ausgangssignal ΔI_D = ΔI I / D – ΔI II / D durch Bilden der Differenz zwischen
• – einer Differenzstromstärke ΔI I / D einer Drain-Source-Stromstärke I I / D1 des ersten Feldeftekttransistors und einer Drain-Source-Stromstärke I I / D2 des zweiten Feldeftekttransistors des jeweils ersten Transistorpaars und
• – einer Differenzstromstärke ΔI II / D einer Drain-Source-Stromstärke I II / D1 des ersten Feldeftekttransistors und einer Drain-Source-Stromstärke I II / D2 des zweiten Feldeftekttransistors des jeweils zweiten Transistorpaars ausgelegt ist.

According to another aspect of the invention, there is provided an apparatus for multiplying two input signals, comprising:

• - At least two pairs of transistors each having a first and a second field effect transistor, wherein
• The field-effect transistors of the two transistor pairs have the same conductivity type and a substantially equal transconductance factor and a substantially equal threshold voltage and have in each case a source, a gate and a drain connection,
• - The sources of the first and the second Feleffekttransistoren of the first and the second transistor pair are electrically connected together;
• The gate terminal of the first field effect transistor of the first transistor pair is electrically connected to the gate terminal of the first field effect transistor of the second transistor pair and forms the first input node;
• The gate terminal of the second field effect transistor of the first transistor pair is electrically connected to the gate terminal of the second field effect transistor of the second transistor pair and forms the second input node;
• - A first V _{in1 of} the input signals can be applied as a potential difference between the first and the second input node;
• A second V _{in2 of} the input signals as a voltage difference V _in2 between a drain-source voltage VI / DS = V II / DS + V _{in2 of} the first field effect transistor and the second field effect transistor of the first transistor pair with respect to a drain-source voltage V II / DS the first Feldeftekttransistors and the second Feldeftekttransistors of the second transistor pair can be applied; and
• - At least one current difference forming means, which for forming a product of the two input signals V _in1 , V _in2 proportional output signal .DELTA.I _D = .DELTA.I I / D - .DELTA.I II / D by forming the difference between
• - A differential current intensity .DELTA.I I / D of a drain-source current II / D1 of the first Feldeftekttransistors and a drain-source current II / D2 of the second Feldeftekttransistors the respective first pair of transistors and
• - A differential current intensity .DELTA.I II / D of a drain-source current I II / D1 of the first Feldeftekttransistors and a drain-source current intensity I II / D2 of the second Feldeftekttransistors the respective second transistor pair is designed.

The superscript I or II in the designation of the currents indicates whether the transistor is a field effect transistor of the first transistor pair I or of the second transistor pair II. The drain-source voltage VI / DS of the first and the second field-effect transistor of the first transistor pair is preferably such a voltage sum of the second input signal V _in2 with a DC offset signal that the drain-source voltage VI / DS when using n Channel field effect transistors always positive and when using p-channel field effect transistors is always negative. The same DC voltage or offset signal can be applied as drain-source voltage V II / DS of the first and the second field-effect transistor of the second transistor pair. The input signal V _in2 is through V in 2 = V I DS - V II DS (4) given.

For the four drain currents of the respective first and the second field effect transistor of the two transistor pairs in the resistance region, the following applies:

The output ΔI _D is then calculated as follows: .DELTA.I D = ΔI I D - ΔI II D = (I I D1 - I I D2 ) - (I II D1 - I II D2 ) = B0 (V I GS1 - V I GS2 ) V in 2 (9)

As can be seen from equation (9), the offset voltage VI / DS does not enter the output signal ΔI _D. Thus, with such a device according to the invention also AC signals can be multiplied correctly. In particular, in a device according to this aspect of the invention, negative input signals can advantageously also be multiplied by the described crosswise connection of two transistor pairs.

Preferably, the current difference forming means comprises at least two voltage follower means each having a voltage follower and two voltage follower outputs, wherein the second input signal V _{in2 can be applied} by applying a voltage follower input signal as the potential difference between the voltage follower input of the first voltage follower means and the voltage follower input of the second voltage follower means.

• – der Emitter und der Kollektor der ersten und der zweiten Bipolartransistoren den gleichen Leitfähigkeitstyp wie derjenige des ersten und des zweiten Feldeffekttransistors aufweisen,
• – der Emitter des ersten Bipolartransistors der ersten Spannungsfolgereinrichtung mit dem Drainanschluss des ersten Feldeffekttransistors des ersten Transistorpaars und der Emitter des zweiten Bipolartransistors der ersten Spannungsfolgereinrichtung mit dem Drainanschluss des zweiten Feldeffekttransistors des ersten Transistorpaars elektrisch verbunden ist,
• – der Emitter des ersten Bipolartransistors der zweiten Spannungsfolgereinrichtung mit dem Drainanschluss des ersten Feldeffekttransistors des zweiten Transistorpaars und der Emitter des zweiten Bipolartransistors der zweiten Spannungsfolgereinrichtung mit dem Drainanschluss des zweiten Feldeffekttransistors des zweiten Transistorpaars elektrisch verbunden ist,
• – die Basen des ersten und des zweiten Bipolartransistors der ersten Spannungsfolgereinrichtung elektrisch miteinander verbunden sind;
• – die Basen des ersten und des zweiten Bipolartransistors der zweiten Spannungsfolgereinrichtung elektrisch miteinander verbunden sind; und
• – die Basen der Bipolartransistoren der ersten und der zweiten Spannungsfolgereinrichtung die beiden Spannungsfolgereingänge bilden.

Particularly preferably, the first and the second voltage follower device each comprise a first and a second bipolar transistor each having an emitter, a base and a collector, wherein

• The emitter and the collector of the first and the second bipolar transistors have the same conductivity type as those of the first and the second field effect transistor,
• The emitter of the first bipolar transistor of the first voltage follower device is electrically connected to the drain terminal of the first field effect transistor of the first transistor pair and the emitter of the second bipolar transistor of the first voltage follower is electrically connected to the drain terminal of the second field effect transistor of the first transistor pair,
• The emitter of the first bipolar transistor of the second voltage follower device is electrically connected to the drain terminal of the first field effect transistor of the second transistor pair and the emitter of the second bipolar transistor of the second voltage follower is electrically connected to the drain terminal of the second field effect transistor of the second transistor pair,
• - The bases of the first and the second bipolar transistor of the first voltage follower means are electrically connected to each other;
• - The bases of the first and the second bipolar transistor of the second voltage follower means are electrically connected together; and
• - The bases of the bipolar transistors of the first and the second voltage follower form the two voltage follower inputs.

• – der Kollektor des ersten Bipolartransistors der ersten Spannungsfolgereinrichtung elektrisch mit dem Kollektor des zweiten Bipolartransistors der zweiten Spannungsfolgereinrichtung verbunden;
• – der Kollektor des zweiten Bipolartransistors der ersten Spannungsfolgereinrichtung elektrisch mit dem Kollektor des ersten Bipolartransistors der zweiten Spannungsfolgereinrichtung verbunden;
• – die Stromdifferenzbildungseinrichtung ausgelegt, das Ausgangssignal ΔI_D durch Bilden der Differenz zwischen
• – der Summe einer Kollektor-Emitter-Stromstärke des ersten Bipolartransistors der ersten Spannungsfolgereinrichtung und einer Kollektor-Emitter-Stromstärke des zweiten Bipolartransistors der zweiten Spannungsfolgereinrichtung und
• – der Summe einer Kollektor-Emitter-Stromstärke des zweiten Bipolartransistors der zweiten Spannungsfolgereinrichtung und einer Kollektor-Emitter-Stromstärke des ersten Bipolartransistors der ersten Spannungsfolgereinrichtung

zu bilden.Preferably

• The collector of the first bipolar transistor of the first voltage follower means is electrically connected to the collector of the second bipolar transistor of the second voltage follower means;
• The collector of the second bipolar transistor of the first voltage follower means is electrically connected to the collector of the first bipolar transistor of the second voltage follower means;
• - The current difference forming means adapted to the output signal .DELTA.I _D by forming the difference between
• - The sum of a collector-emitter current of the first bipolar transistor of the first voltage follower means and a collector-emitter current of the second bipolar transistor of the second voltage follower means and
• - The sum of a collector-emitter current of the second bipolar transistor of the second voltage follower means and a collector-emitter current of the first bipolar transistor of the first voltage follower means

to build.

• – die dritten und die vierten Feldeffekttransistoren den gleichen Leitfähigkeitstyp wie derjenige des ersten und des zweiten Feldeffekttransistors aufweisen,
• – der Sourceanschluss des dritten Feldeffekttransistors der ersten Spannungsfolgereinrichtung mit dem Drainanschluss des ersten Feldeffekttransistors des ersten Transistorpaars und der Sourceanschluss des vierten Feldeffekttransistors der ersten Spannungsfolgereinrichtung mit dem Drainanschluss des zweiten Feldeffekttransistors des ersten Transistorpaars elektrisch verbunden ist,
• – der Sourceanschluss des dritten Feldeffekttransistors der zweiten Spannungsfolgereinrichtung mit dem Drainanschluss des ersten Feldeffekttransistors des zweiten Transistorpaars und der Sourceanschluss des vierten Feldeffekttransistors der zweiten Spannungsfolgereinrichtung mit dem Drainanschluss des zweiten Feldeffekttransistors der ersten Spannungsfolgereinrichtung elektrisch verbunden ist,
• – der Gateanschluss des dritten Feldeffekttransistors mit dem Gateanschluss des vierten Feldeffekttransistors der ersten Spannungsfolgereinrichtung elektrisch verbunden ist;
• – der Gateanschluss des dritten Feldeffekttransistors mit dem Gateanschluss des vierten Feldeffekttransistors der zweiten Spannungsfolgereinrichtung elektrisch verbunden ist; und
• – die Gateanschlüsse der ersten und der zweiten Spannungsfolgereinrichtung die beiden Spannungsfolgereingänge bilden.

Instead of bipolar transistors, the first and the second voltage-sequence device may respectively comprise a third and a respective fourth field-effect transistor, each having a source, a gate and a drain connection

• The third and the fourth field effect transistors have the same conductivity type as those of the first and the second field effect transistor,
• The source terminal of the third field effect transistor of the first voltage follower device is electrically connected to the drain terminal of the first field effect transistor of the first transistor pair and the source terminal of the fourth field effect transistor of the first voltage follower is electrically connected to the drain terminal of the second field effect transistor of the first transistor pair,
• The source terminal of the third field effect transistor of the second voltage follower device with the drain terminal of the first field effect transistor of the second transistor pair, and the source terminal of the second field effect transistor fourth field effect transistor of the second voltage follower means is electrically connected to the drain terminal of the second field effect transistor of the first voltage follower means,
• - The gate terminal of the third field effect transistor is electrically connected to the gate terminal of the fourth field effect transistor of the first voltage follower means;
• - The gate terminal of the third field effect transistor is electrically connected to the gate terminal of the fourth field effect transistor of the second voltage follower means; and
• - The gate terminals of the first and the second voltage follower form the two voltage follower inputs.

Of the Use of field effect transistors in particular allows the preferred device according to the invention can be realized as a monolithic integrated circuit. In In this case, however, the body effect must be considered, which an additional undesirable nonlinearity can generate.

• – der Drainanschluss des dritten Feldeffekttransistors der ersten Spannungsfolgereinrichtung elektrisch mit dem Drainanschluss des vierten Feldeffekttransistors der zweiten Spannungsfolgereinrichtung verbunden;
• – der Drainanschluss des vierten Feldeffekttransistors der ersten Spannungsfolgereinrichtung elektrisch mit dem Drainanschluss des dritten Feldeffekttransistors der zweiten Spannungsfolgereinrichtung verbunden;
• – die Stromdifferenzbildungseinrichtung ausgelegt, das Ausgangssignal ΔI_D durch Bilden der Differenz zwischen
• – der Summe einer Drain-Source-Stromstärke des dritten Feldeffekttransistors der ersten Spannungsfolgereinrichtung und einer Drain-Source-Stromstärke des vierten Feldeffekttransistors der zweiten Spannungsfolgereinrichtung und
• – der Summe einer Drain-Source-Stromstärke des dritten Feldeffekttransistors der zweiten Spannungsfolgereinrichtung und einer Drain-Source-Stromstärke des vierten Feldeffekttransistors der ersten Spannungsfolgereinrichtung

zu bilden.Preferably

• - The drain terminal of the third field effect transistor of the first voltage follower means is electrically connected to the drain terminal of the fourth field effect transistor of the second voltage follower means;
• - The drain terminal of the fourth field effect transistor of the first voltage follower means is electrically connected to the drain terminal of the third field effect transistor of the second voltage follower means;
• - The current difference forming means adapted to the output signal .DELTA.I _D by forming the difference between
• - The sum of a drain-source current of the third field effect transistor of the first voltage follower means and a drain-source current of the fourth field effect transistor of the second voltage follower means and
• - The sum of a drain-source current of the third field effect transistor of the second voltage follower means and a drain-source current of the fourth field effect transistor of the first voltage follower means

to build.

Preferably the current difference forming device comprises at least one current mirror device. The current mirror device may preferably bipolar or field effect transistors exhibit. Further, the current difference forming means may be a transformer with two symmetrical input windings.

At the Most preferred is when all the transistors of the device for analog multiplying two input signals monolithically a crystal are realized.

Further at least the first and the second field effect transistor are preferred Junction field effect transistors, most preferably junction field effect transistors with electrically insulated gate, in particular MOS transistors.

• – Bereitstellen von zumindest zwei Feldeffekttransistoren es gleichen Leitfähigkeitstyps und mit im wesentlichen gleichem Transkonduktanzfaktor und im wesentlichen gleicher Schwellspannung, wobei die beiden Feldeffekttransistoren jeweils einen Source-, einen Gate- und einen Drainanschluss aufweisen und der Sourceanschluss des ersten Feldeffekttransistors elektrisch mit dem Sourceanschluss des zweiten Feldeffekttransistors verbunden ist, wobei der Gateanschluss des ersten Feldeffekttransistors einen ersten Eingangsknoten und der Gateanschluss des zweiten Feldeffekttransistors einen zweiten Eingangsknoten bilden und wobei ein erstes V_in1 der Eingangssignale die Potentialdifferenz zwischen dem ersten und dem zweiten Eingangsknoten darstellt;
• – Betreiben der beiden Feldeffekttransistoren im Widerstandsbereich, wobei die Drain-Source-Spannung des ersten Feldeffekttransistors im wesentlichen gleich zu der Drain-Source-Spannung des zweiten Feldeffekttransistors ist und ein zweites V_in2 der Eingangssignale darstellt;
• – Anlegen des ersten V_in1 und des zweiten V_in2 der Eingangssignale;
• – Bilden eines dem Produkt V_in1 × V_in2 der beiden Eingangssignale V_in1, V_in2 proportionalem Ausgangssignal ΔI_D durch Bilden der Differenz zwischen einer Drain-Source-Stromstärke I_D1 des ersten Feldeffekttransistors und einer Drain-Source-Stromstärke I_D2 des zweiten Feldeffekttransistors; und
• – Ausgeben des Ausgangssignals ΔI_D.

Furthermore, according to the invention, a method is provided for analog multiplication of two input signals, comprising the following steps:

• - Providing at least two field effect transistors of the same conductivity type and having substantially the same transconductance factor and substantially the same threshold voltage, wherein the two field effect transistors each have a source, a gate and a drain terminal and the source terminal of the first field effect transistor electrically connected to the source terminal of the second field effect transistor wherein the gate terminal of the first field effect transistor forms a first input node and the gate terminal of the second field effect transistor forms a second input node, and wherein a first V _{in1 of} the input signals represents the potential difference between the first and second input nodes;
• - Operating the two field effect transistors in the resistance region, wherein the drain-source voltage of the first field effect transistor is substantially equal to the drain-source voltage of the second field effect transistor and a second V _{in2 represents} the input signals;
• - applying the first V _in1 and the second V _{in2 of} the input signals;
• - forming a product V _in1 × V _in2 the two input signals V _in1, V _in2 proportional output signal .DELTA.I _D by forming the difference between a drain-source current I _D1 of the first field effect transistor and a drain-source current I _D2 of the second field effect transistor ; and
• - Output of the output signal .DELTA.I _D.

Thus, according to the invention furthermore a method for analog multiplying two input signals is given, which is an analog, formally correct multiplication of two input signals allows. Such a correct multiplication of two input signals was so far only possible by digital multiplication methods, which for high frequency Applications not suitable and for Low-frequency applications often too expensive and power-intensive are. Alternatively, conventionally with circuits based on the Gilbert cell an approximation of Multiplication in a small dynamic range made.

The erfindugsgemäßen devices and methods can in particular application in the mixing stage of circuits of the classical Receiver concept, the so-called Superhetkonzepts, find. In particular, can with a device according to the invention a simplified receiver realization be achieved because on so-called broadband controls before the mixer can be omitted or a considerable effort for a given effort increased performance can be achieved. Other applications the device according to the invention lie, for example, in the field of level control, power measurement, RMS and vector voltmeters, i. wherever a correct Multiplication of two input signals is required.

The Invention will be more preferred in the following with reference to accompanying drawings Embodiments by way of example described. It shows:

1 a schematic representation of a conventional Gilbert cell;

2 the static characteristic of the Gilbert cell of 1 ;

3 a schematic representation of a conventional field effect transistor with counting arrows;

4 a simplified schematic representation of an interconnection of two field effect transistors as a basic element of a preferred device according to the invention;

5 a schematic representation of an embodiment of the device according to the invention;

6 the static characteristic of the in 5 embodiment shown; and

7 a schematic representation of another embodiment of the device according to the invention.

A first embodiment of the invention will be described with reference to FIG 3 to 5 described. The device according to the invention comprises two field effect transistors, which have the same conductivity type, substantially the same transconductance factor and substantially the same threshold voltage (threshold voltage).

3 shows a field effect transistor with the associated current and Spannungszählpfeilen. The field effect transistor has a drain terminal D, a source terminal S and a gate terminal G. With V _GS the voltage is gate-source, with V _DS the voltage drain-source and I _DS the drain current. In the resistance region, the drain current I _{DS of} the field effect transistor follows equation (1).

4 shows a schematic representation of a transistor pair with a first T1 (left transitor of 4 ) and a second T2 (right transistor of 4 ) Field effect transistor, which have a substantially equal transconductance factor B _o and a same threshold voltage V _TH . The source terminal S1 of the first field effect transistor T1 is electrically connected to the source terminal S2 of the second field effect transistor T2. The gate-source voltage of the first field effect transistor T1 is referred to as V _GS1 and the gate-source voltage of the second field effect transistor T2 as V _GS2 . Both field effect transistors are operated with substantially identical drain-source voltage V _DS . The drain current of the first field effect transistor T1 is denoted by I _D1 and the drain current of the second field effect transistor T2 by I _D2 .

The gate terminal G1 of the first field effect transistor T1 forms a first input node E1 and the gate terminal G2 of the second T2 field effect transistor forms a second input node E2. The first input signal V _in1 is _{indicative of the} potential difference between the first E1 and the second E2 input node can be laid. The second input signal V _in2 can be applied as a drain-source voltage of the first field effect transistor T1 and as a drain-source voltage of the second field effect transistor T2.

The difference ΔI _{D of} both drain currents I _D1 and I _D2 represents the output signal, which is proportional to the product of the two input signals V _in1 and V _in2 (see equations (2) and (3)). Thus, a formally correct, analog multiplication of the two input signals V _in1 and V _{in2 is} possible. The two field effect transistors T1 and T2 may in particular be barrier FETs, MOS FETs or GaAs FETs.

5 shows a preferred embodiment of a device according to the invention, which essentially comprises three circuit blocks B1-B3. In the lowest block B1, the pair of transistors are connected to the two as related to 4 shown interconnected field effect transistors T1 and T2 shown in the resistance region.

In the middle circuit block B2 is a voltage follower device which includes a first BT1 and a second BT2 bipolar transitor includes. The voltage follower allows the application of identical Drain-source voltages to the two field effect transistors T1 and T2.

Of the Emitter and the collector of the first bipolar transistor BT1 and the emitter and the collector of the second bipolar transistor BT2 have the same conductivity type as that of the first T1 and the second T2 Feldeftekttransistors. Further, the emitter of the first bipolar transistor BT1 is connected to the Drain terminal of the first field effect transistor T1 and the emitter of the second bipolar transistor BT2 to the drain terminal of the second Field effect transistor T2 electrically connected.

The bases of the first bipolar transistor BT1 and the second bipolar transistor BT2 are electrically connected to each other and thus form the voltage follower input SE. The second input signal V _in2 can be applied to the voltage follower input SE by applying a voltage follower input signal, wherein the voltage follower input signal can be a current or voltage signal that is proportional to V _in2 . The collector of the first bipolar transistor BT1 forms a first output node A1 and the collector terminal of the second bipolar transistor BT2 forms a second output node A2.

Instead of bipolar transistors, field-effect transistors can also be used. An exemplary embodiment comprising a voltage follower with field effect transistors is similar to that in FIG 5 constructed voltage follower device constructed with bipolar transistors. Instead of the two bipolar transistors BT1 and BT2 two field effect transistors of the same conductivity type as those of the first and the second field effect transistor are used, ie the circuit has in addition to the two field-effect transistors T1 and T2 described above, a third and a fourth field effect transistor, each having a source, a gate and a drain terminal.

Of the Source terminal of the third field effect transistor is in this Case with the drain terminal D1 of the first field effect transistor T1 and the source terminal of the fourth field effect transistor with the drain terminal D2 of the second field effect transistor T2 electrically connected. The gate terminal of the third field effect transistor is to the gate terminal of the fourth field effect transistor electrically connected and forms the voltage follower input SE. The drain connection of the third field effect transistor thus forms the first output node A1 and the drain terminal of the fourth field effect transistor second output node A2.

The uppermost circuit block B3 in FIG 5 1 shows a current mirror device, which in this embodiment comprises two bipolar transistors BT3 and BT4 each having a base, an emitter and a collector, the emitter and the base of the bipolar transistors BT3 and BT4 of the current mirror device having the opposite conductivity type as those of the first T1 and the second T2 Have field effect transistor.

The bases of the two bipolar transistors BT3 and BT4 of the current mirror device are electrically connected to one another and the two bipolar transistors are operated with the same base-emitter voltages. The collector of the first bipolar transistor BT3 of the current mirror device is electrically connected to the first output node A1 and the collector of the second bipolar transistor BT4 to the second output node A2. Thus, the current mirror device forms, for a current flowing in the first output node A1, a mirror current of the same current intensity which flows into the second output node A2, wherein the output signal ΔI _{D can be} tapped off at the second output node A2.

In particular, the drain currents I _D1 and I _{D2 of} the first T1 and the second T2 field effect transistors are forwarded by the voltage follower through the respective first A1 and the second output node A2 into the current mirror device which passes the drain current I _{D1 of} the first field effect transistor T1 through the voltage divider feeds left branch of the current mirror device in the right branch of the current mirror device again. When the node labeled I _{out is} low-ohmic, I _out is calculated to the desired current difference I _D1 -I _D2 according to equations (2) and (3).

At the in 5 In the embodiment shown, the current mirror device is formed with bipolar transistors. However, the current mirror device may alternatively be formed with field effect transistors. The field-effect transistors forming the current mirror in this case are field-effect transistors of opposite conductivity type to those of the first circuit block B1, ie if the first T1 and the second T2 field effect transistor are n-channel field-effect transistors, the field-effect transistors of the current mirror device as p-channel Field effect transistors executed.

The gate terminals of the two field-effect transistors of the current mirror device are electrically connected to one another, and the two field-effect transistors have identical source-gate voltages. The drain terminal of the first field effect transistor of the current mirror device is electrically connected to the first output node A1 and the drain terminal of the second field effect transistor is electrically connected to the second output node A2. Thus, the current mirror device forms, for a current flowing in the first output node A1, a mirror current of the same current intensity which flows into the second output node A2, wherein the output signal ΔI _{D can be} tapped off at the second output node A2.

6 shows the static characteristic, ie the course of an output voltage V _out in response to the input signal V _in1 of the 5 shown embodiment of the invention. The characteristic shown was determined by a numerical simulation of the in 5 obtained circuit, was dispensed with a current mirror device. In each case a resistor was inserted at the output node and the difference of the voltage drops across both resistors, which is designated as V _out , in FIG 6 normalized applied. In the standardization of the largest occurring voltage difference, the value "1 V" and the smallest occurring voltage difference was assigned the value "-1 V", which is always possible by the correct choice of the resistors according to Ohm's law. V _out is thus proportional to the difference between the two drain currents I _D1 - I _D2 . On the abscissa, the input voltage V _{in1 is} plotted in volts, which is applied as a differential voltage V _GS1 - V _GS2 between the gate terminals of the first and the second field effect transistor.

In 6 is a series of characteristics L1 to L5 shown with different drain-source voltages, ie characteristics for different V _in2 . Curve L1 shows the curve V _out as a function of V _in1 at V _in2 = 1.6 V, curve L2 at V _in2 = 1.4 V, curve L3 at V _in2 = 1.2 V, curve L4 at V _in2 = 1 , 0 V and characteristic L5 at V _in2 = 0.8 V. As out 6 As can be seen, the static characteristic is a linear characteristic in a range of ± 2 V around V _in1 = 0, ie a considerably larger linearity range than that of a conventional Gilbert cell. The static characteristic of in 5 shown circuit is by simulation of in 5 obtained circuit with basic JFET models. A further increase of the linear range is possible by using MOSFETs instead of JFETs.

As from the in 6 is shown, multiplication V _in1 × V _{in2 is} possible for positive values. In order to be able to detect negative input signals, preferably a preferred variant of an embodiment according to the invention is used, which in 7 is shown. In the 7 embodiment shown represents a so-called double-balanced mixer, which essentially two cross-connected circuits according to 5 includes.

In the 7 embodiment shown comprises two transistor pairs I and II, each having a first T1 and a second T2 field effect transistor. The field effect transistors of the two transistor pairs I and II have the same conductivity type, a substantially equal transconductance factor and a substantially equal threshold voltage.

The source terminals S1 and S2 of the first T1 and the second T2 field-effect transistors of the first I and the second II transistor pair are electrically connected to each other and preferably set to a predetermined reference potential. The gate terminals G1 and G2 of the first field effect transistors T1 of the first I and second II transistor pairs are electrically connected to each other and form the first input node. The gate terminals G2 of the second field effect transistors T2 of the first I and the second II transistor pair are also electrically connected to each other and form the second input node. The first input signal V _in1 can be applied as a potential difference between the first and the second input node.

Of the first T1 and the second T2 field effect transistor of the first transistor pair I are operated with the same drain-source voltage V I / DS. The same applies to the first T1 and the second T2 field effect transistor of the second Transistor pair II, which with the same drain-source voltage V II / DS are operated.

Furthermore, the in 7 shown embodiment, two voltage followers SF1 and SF2, each having a first BT1 and a second BT2 bipolar transistor. The emitter and the collector of the first BT1 and the second BT2 bipolar transistors have the same conductivity type as those of the first T1 and the second T2 field effect transistor.

Of the Emitter of the first bipolar transistor BT1 of the first voltage follower device SF1 is connected to the drain terminal D1 of the first field effect transistor T1 of the first transistor pair I and the emitter of the second bipolar transistor BT2 of the first voltage follower SF1 is connected to the drain D2 of the second field effect transistor T2 of the first transistor pair I electrically connected. The emitter of the first bipolar transistor BT1 of the second voltage follower SF2 is connected to the drain terminal D1 of the first field effect transistor T1 of the second transistor pair II and the emitter of the second bipolar transistor BT2 of the second Voltage follower SF2 is connected to the drain terminal D2 of second field effect transistor T2 of the second transistor pair II electrically connected. The bases of the first BT1 and the second BT2 Bipolar transistor of the first voltage follower SF1 are electrically connected to each other and thus form the voltage follower input SE1 of the first voltage follower SF1. The bases of the first BT1 and the second BT2 bipolar transistor of the second voltage follower device SF2 are electrically connected to each other and thus form the voltage follower input SE2 of the second voltage follower SF2.

The second input signal V _in2 can be applied by applying a voltage follower input signal, which may be a current or voltage signal, as a potential difference between the voltage follower input SE1 of the first voltage follower SF1 and the voltage follower input SE2 of the second voltage follower SF2.

Further is the collector of the first bipolar transistor BT1 of the first voltage follower device SF1 electrically connected to the collector of the second bipolar transistor BT2 of the second voltage follower SF2 connected and forms a first output node A1. The collector of the second bipolar transistor BT2 of the first voltage follower SF1 is electrically connected to the collector of the first bipolar transistor BT1 of the second voltage follower device SF2 and forms a second output node A2. The first A1 and the second A2 output node are connected to the current mirror device connected.

The current mirror device of in 7 The illustrated embodiment preferably comprises two bipolar transistors BT3 and BT4 each having a base, an emitter and a collector, the emitter and the base of the bipolar transistors BT3 and BT4 of the current mirror device having the opposite conductivity type as those of the first T1 and the second T2 field effect transistor.

The bases of the two bipolar transistors BT3 and BT4 of the current mirror device are electrically connected together and the two bipolar transistors BT3 and BT4 are operated with the same base-emitter voltage. The collector of the first bipolar transistor BT3 of the current mirror device is electrically connected to the first output node A1 and the collector of the second bipolar transistor BT4 to the second output node A2. Thus, the current mirror device forms, for a current flowing in the first output node A1, a mirror current of the same current intensity which flows into the second output node A2, wherein the output signal ΔI _{D can be} tapped off at the second output node A2.

Especially becomes the drain current I I / D1 of the first field effect transistor T1 of the first Transistor pair I and the drain current I II / D2 of the second field effect transistor T2 of the second transistor pair II through the first output node A1 from the voltage follower device into the current mirror device forwarded. Further, the drain current I I / D2 of the second field effect transistor T2 of the first transistor pair I and the drain current I II / D1 of the first Feldeftekttransistors T1 of the second transistor pair II by the second output node A2 forwarded to the current mirror device.

The current mirror device mirrors the sum of the drain currents II / D1 + I II / D2 in the left branch of the current mirror device, as in FIG 7 shown from the top in the right branch of the current mirror device again. When the node labeled I _out is then loaded with low resistance, I _out is calculated to be (II / D1 + I II / D 2) - (II / D 2 + I II / D1) which is required by equation (9).

The Current mirror device may further field effect transistors as described above instead of having bipolar transistors.

D

drain

G

gate terminal

S

source terminal

T1

first Field Effect Transistor

D1

drain of the first field effect transistor

G1

gate terminal of the first field effect transistor

S1

source terminal of the first field effect transistor

T2

second Field Effect Transistor

D2

drain of the second field effect transistor

G2

gate terminal of the second field effect transistor

S2

source terminal of the second field effect transistor

BT1 - BT4

bipolar transistors

E1

first input node

E1

second input node

SF1, SF2

first or second voltage follower device

SE

Voltage follower input

SE1

Voltage follower input the first voltage follower device

SE2

Voltage follower input the second voltage follower device

A1

first output node

A2

second output node

I

first transistor pair

II

second transistor pair

V _in1

first input

V _in2

second input

I _D1

Drain current of the first field effect transistor

I _D2

Drain current of the second field effect transistor

I I / D1

Drain current of the first field effect transistor of the second

transistor pair

I II / D1

Drain current of the first field effect transistor of

second transistor pair

I I / D2

Drain current of the second field effect transistor of the first

transistor pair

I II / D2

Drain current of the second field effect transistor of the second

transistor pair

V _GS1

Gate-source voltage of the first field effect transistor

V _GS2

Gate-source voltage of the second field effect transistor

V _DS

Drain-source voltage of the first and the second

Field-effect transistor

L1-L5

static characteristics

B1-B3

circuit blocks

Claims (23)

Apparatus for analog multiplying two input signals (V _in1 , V _in2 ), comprising: - at least one first (T1) and at least one second (T2) field effect transistor, the two field effect transistors (T1, T2) having the same conductivity type and a substantially equal transconductance factor and have a substantially equal threshold voltage and a respective source (S1, S2), a gate (G1, G2) and a drain terminal (D1, D2), wherein the source terminal (S1) of the first field effect transistor (T1) is electrically connected to the source terminal (S2) of the second Feldeftekttransistors (T2), wherein the gate terminal ( G1) of the first field effect transistor (T1) forms a first input node (E1) and the gate terminal (G2) of the second field effect transistor (T2) forms a second input node (E2) and a first V _{in1 of} the input signals forms a potential difference between the first (E1) and the second (E2) input node can be applied and a second V _{in2 of} the input signals as drain-source voltage (V _DS ) of the first Feldeftekttransistors (T1) and the second field effect transistor (T2) can be applied; and - at least one current difference forming means, which for forming a product of the two input signals V _in1 , V _in2 proportional output signal .DELTA.I _D - I _D1 - I _D2 by forming the difference between a drain-source current I _{D1 of} the first field effect transistor (T1) and a drain-source current intensity I _{D2 of} the second Feldeftekttransistors (T2) is designed. The apparatus of claim 1, wherein the current difference forming means comprises at least one voltage follower having a voltage follower (SE) and two voltage follower outputs, wherein the second input signal V _in2 can be applied to the voltage follower input (SE) by applying a voltage follower input signal. Apparatus according to claim 2, wherein - the voltage follower device a first (BT1) and a second bipolar transistor (BT2) with each comprising an emitter, a base and a collector, - the emitter and the collector of the first (BT1) and the second bipolar transistor (BT2) the same conductivity type as that of the first (T1) and the second (T2) field effect transistor exhibit, - of the Emitter of the first bipolar transistor (BT1) with the drain terminal (D1) of the first field effect transistor (T1) and the emitter of the second Bipolar transistor (BT2) to the drain terminal (D2) of the second Field effect transistor (T2) is electrically connected, - the base of the first bipolar transistor (BT1) with the base of the second bipolar transistor (BT2) is electrically connected and - The bases of the bipolar transistors (BT1, BT2) form the voltage follower input (SE). Device according to claim 3, wherein the collector of the first bipolar transistor (BT1) forms a first output node (A1) and the collector connection of the second bipolar transistor (BT2) forms a second output node (A2) and the current difference formation means is adapted to generate the output signal ΔI _D by forming the Difference between a collector-emitter current of the first bipolar transistor (BT1) and a collector-emitter current of the second bipolar transistor (BT2) to form. Apparatus according to claim 2, wherein - the voltage follower device a third and a fourth field effect transistor, respectively a source, a gate and a drain terminal, - the third and the fourth field effect transistor has the same conductivity type as that of the first (T1) and the second (T2) field effect transistor exhibit, - of the Source terminal of the third field effect transistor with the drain terminal (D1) of the first field effect transistor (T1) and the source terminal of the fourth field effect transistor with the drain terminal (D2) of the second Field effect transistor (T2) is electrically connected, - the gate connection of the third field effect transistor with the gate terminal of the fourth Field effect transistor is electrically connected and - the gate connections of the third and fourth field effect transistor, the voltage follower input Form (SE). The device of claim 5, wherein the drain of the third field effect arrester forms a first output node (A1) and the drain of the fourth field effector comprises a second output node (A2) and the current difference forming means is adapted to derive the output ΔI _D by forming the difference between a drain source Amount of current of the third field effect transistor and a drain-source current of the fourth field effect transistor to form. Device according to one of the preceding claims, wherein the current difference forming device at least one current mirror device includes. Apparatus according to claim 7, wherein the current mirror means is arranged to form, at a current flowing in the first output node (A1), a mirror current of the same current flowing into the second output node (A2), the output signal ΔI _D The second output node (A2) can be tapped off. Apparatus according to claim 7, wherein the current mirror means is arranged to form, at a current flowing in the second output node (A2), a mirror current of equal current flowing into the first output node (A1), the negative output signal -ΔI _D at the first output node (A1) can be tapped. Device according to one of claims 7 to 9, wherein the current mirror device two field effect transistors of opposite conductivity type as that of the first and the second field effect transistor. Device according to one of claims 7 to 9, wherein the current mirror device two bipolar transistors (BT3, BT4) each with a base, emitter and collector, wherein the emitter and the base of the bipolar transistors (BT3, BT4) of the current mirror device of the opposite conductivity type as that of the first (T1) and the second (T2) field effect transistor having. Device according to one of claims 1 to 6, wherein the current difference forming means at least one transformer comprising two symmetrical input windings. Device for multiplying two input signals (V _in1 , V _in2 ), comprising: - at least two transistor pairs (I, II) each having a first (T1) and a second (T2) field effect transistor, wherein - the field effect transistors (T1, T2) of the two Transistor pairs (I, II) have the same conductivity type and a substantially equal transconductance factor and a substantially equal threshold voltage and each having a source (S1, S2), a gate (G1, G2) and a drain terminal (D1, D2) In that the source terminals (S1, S2) of the first and the second field-effect transistors of the first (I) and the second (II) transistor pair are electrically connected to one another; - The gate terminal (G1) of the first field effect transistor (T1) of the first transistor pair (I) to the gate terminal (G1) of the first field effect transistor (T1) of the second transistor pair (II) is electrically connected and forms the first input node; - The gate terminal (G2) of the second field effect transistor (T2) of the first transistor pair (I) to the gate terminal (G2) of the second field effect transistor (T2) of the second transistor pair (II) is electrically connected and forms the second input node; - A first V _{in1 of} the input signals can be applied as a potential difference between the first and the second input node; A second V _{in2 of} the input signals as a voltage difference V _in2 between a drain-source voltage (VI / DS = V II / DS + V in ₂ ) of the first field effect transistor (T1) and the second field effect transistor (T2) of the first transistor pair (I) opposite to a drain-source voltage (V II / DS) of the first field effect transistor (T1) and the second field effect transistor (T2) of the second transistor pair (II) can be applied; and - at least one current difference formation device, which for forming a product of the two input signals V _in1, V _in2 proportional output signal .DELTA.I _D = .DELTA.I I / D - .DELTA.I II / D by taking the difference between: - a differential current .DELTA.I I / D a drain-source Current II / D1 of the first field effect transistor (T1) and a drain-source current II / D2 of the second field effect transistor (T2) of each first transistor pair (I) and - a differential current intensity .DELTA.I II / D of a drain-source current I II / D1 of the first field effect transistor (T1) and a drain-source current I II / D2 of the second field effect transistor (T2) of the respective second transistor pair (II) is designed. Apparatus according to claim 13, wherein the current difference forming means comprises at least two voltage followers (SF1, SF2) each having a voltage follower (SE1, SE2) and two voltage follower outputs, wherein the second input signal V _{in2 is applied} by applying a voltage follower input signal as the potential difference between the voltage follower input (SE1) first voltage follower means and the voltage follower input (SE2) of the second voltage follower means can be applied. The apparatus of claim 14, wherein - the first (SF1) and second (SF2) voltage follower means each comprise a first (BT1) and a second (BT2) bipolar transistor each having an emitter, a base and a collector, - the emitter and the collector the first (BT1) and the second (BT2) bipolar transistors have the same conductivity type as those of the first (T1) and the second (T2) field-effect transistor, - the emitter of the first bipolar transistor (BT1) of the first voltage follower (SF1) with the drain terminal ( D1) of the first field effect transistor (T1) of the first transistor pair (I) and the emitter of the second bipolar transistor (BT2) of the first voltage follower device (SF1) to the drain terminal (D2) of second field effect transistor (T2) of the first transistor pair (I) is electrically connected, - the emitter of the first bipolar transistor (BT1) of the second voltage follower device (SF2) to the drain terminal (D1) of the first field effect transistor (T1) of the second transistor pair (II) and the Emitter of the second bipolar transistor (BT2) of the second voltage follower means (SF2) to the drain terminal (D2) of the second field effect transistor (T2) of the second transistor pair (II) is electrically connected, - the bases of the first (BT1) and the second (BT2) bipolar transistor the first voltage follower means (SF1) are electrically connected together; - The bases of the first (BT1) and the second (BT2) bipolar transistor of the second voltage follower means (SF2) are electrically connected together; and - the bases of the bipolar transistors of the first (SF1) and the second (SF2) voltage follower form the two voltage follower inputs (SE1, SE2). An apparatus according to claim 15, wherein - the collector of the first bipolar transistor (BT1) of the first voltage follower means (SF1) is electrically connected to the collector of the second bipolar transistor (BT2) of the second voltage follower means (SF2); - the collector of the second bipolar transistor (BT2) of the first voltage follower means (SF1) is electrically connected to the collector of the first bipolar transistor (BT1) of the second voltage follower means (SF2); - The current difference forming means is adapted to the output signal .DELTA.I _D by forming the difference between - the sum of a collector-emitter current of the first bipolar transistor (BT1) of the first voltage follower means (SF1) and a collector-emitter current of the second bipolar transistor (BT2) of second voltage follower means (SF2) and - the sum of a collector-emitter current of the second bipolar transistor (BT2) of the second voltage follower means (SF2) and a collector-emitter current of the first bipolar transistor (BT1) of the first voltage follower means. Apparatus according to claim 14, wherein - the first and the second voltage follower means each have a third one and a fourth field effect transistor each having one Includes source, a gate and a drain terminal, - the third and the fourth field effect transistors have the same conductivity type like those of the first and second field effect transistors, - the source connection of the third field effect transistor of the first voltage follower device to the drain terminal of the first field effect transistor of the first Transistor pair and the source of the fourth field effect transistor the first voltage follower with the drain terminal of the second field effect transistor of the first transistor pair electrically connected is, - of the Source terminal of the third field effect transistor of the second voltage follower device to the drain terminal of the first field effect transistor of the second Transistor pair and the source of the fourth field effect transistor the second voltage follower with the drain terminal of second field effect transistor of the first voltage follower device is electrically connected, - of the Gate terminal of the third field effect transistor with the gate terminal of the fourth field effect transistor of the first voltage follower device electrically connected; - of the Gate terminal of the third field effect transistor with the gate terminal the fourth field effect transistor of the second voltage follower device electrically connected; and - the gate connections of the first and second voltage follower means forming the two voltage follower inputs. The device of claim 17, wherein: - the drain terminal of the third field effect transistor of the first voltage follower means (SF1) is electrically connected to the drain terminal of the fourth field effect transistor of the second voltage follower means (SF2); - The drain terminal of the fourth field effect transistor of the first voltage follower means (SF1) is electrically connected to the drain terminal of the third field effect transistor of the second voltage follower means (SF2); - The current difference forming means is adapted to the output signal .DELTA.I _D by forming the difference between - the sum of a drain-source current of the third field effect transistor of the first voltage follower means (SF1) and a drain-source current of the fourth field effect transistor of the second voltage sender means (SF2) and - the sum of a drain-source current of the third field effect transistor of the second voltage follower means (SF2) and a drain-source current of the fourth field effect transistor of the first voltage follower means (SF1) to form. Device according to one of claims 13 to 18, wherein the current difference forming means comprises at least one current mirror device. Device according to one of the preceding claims, wherein all transistors are realized monolithically on a crystal. Device according to one of the preceding claims, wherein at least the first (T1) and the second (T2) field-effect transistor Junction field effect transistors are. Device according to one of the preceding claims, wherein at least the first (T2) and the second (T2) field-effect transistor Junction field effect transistors with electrically insulated gate, in particular MOS transistors. Method for analog multiplication of two input signals (V _in1 , V _in2 ), comprising the following steps: - providing at least two field effect transistors (T1, T2) of the same conductivity type and having substantially the same transconductance factor and substantially the same threshold voltage, the two field effect transistors (T1 , T2) each having a source (S1, S2), a gate (G1, G2) and a drain terminal (D1, D2) and the source terminal (S1) of the first Feldeftekttransistors (T1) electrically connected to the source terminal (S2) of the second field effect transistor (T2) is connected, wherein the gate terminal (G1) of the first field effect transistor (T1) a first input node (E1) and the gate terminal (G2) of the second field effect transistor (T2) form a second input node (E2) and wherein a first V _{in1 of} the input signals represents the potential difference between the first (E1) and the second input node (E2); Operating the two field effect transistors (T1, T2) in the resistance region, wherein the drain source voltage (V _DS ) of the first field effect transistor (T1) is substantially equal to the drain source voltage (V _DS ) of the second field effect transistor (T2) and represents a second V _{in2 of} the input signals; - applying the first V _in1 and the second V _{in2 of} the input signals; - forming a product V _in1 × V _in2 the two input signals V _in1, V _in2 proportional output signal .DELTA.I _D by forming the difference between a drain-source current I _D, of the first field effect transistor (T1) and a drain-source current I _{D2 of} the second field effect transistor (T2); and outputting the output signal ΔI _D.