DE10308921A1 - Phase locked loop (PLL) for frequency syntehsis for HF PLL in digital circuit technique for mobile radio application, e.g. in blue tooth standard, with digitally controllable oscillator - Google Patents

Abstract

PLL contains DCO (1) with control, i.e. tuning, input (2) and output (3), and phase-frequency comparator (7), whose first input (10) receives reference signal (psi div) in dependence on DCO output frequency (fDCO).

Description

The present invention relates to a phase control arrangement for frequency synthesis.

Frequency synthesis is usually used Phase locked loops, so-called PLL, phase-locked loop, are used. For mobile applications, at which carrier frequencies in the gigahertz range become, it is common to use analog PLL. For example, with the Bluetooth mobile radio standard must be one carrier frequency in the order of magnitude of 2.4 gigahertz are generated on which user data is modulated on become.

With analog PLL is common an analog, voltage-controlled oscillator is provided, a so-called VCO, Voltage Controlled Oscillator, whose output signal, via a Divider frequency divided, a phase / frequency detector is supplied. This compares the divided oscillator signal with one Reference signal and controls depending from a phase and / or frequency deviation via a charge pump circuit and a loop filter to the oscillator. In further training of these The frequency divider can function as an analog PLL as a so-called multi-modulus divider accomplished be with a digital modulation signal, for example via a Sigma-delta converter is controlled.

Such analog PLL include both analog as well as digitally working function blocks. A major disadvantage such, so-called hybrid PLL in terms of their manufacturing capabilities in integrated circuit technology lies in the relatively large space requirement on the chip, especially regarding the charge pump circuit and the loop filter, and also in the high number of analog function blocks.

It is therefore desirable to have a high frequency PLL preferably largely build in digital circuitry, including the Oscillator.

A problem arises with a purely digital structure of the controlled oscillator of the necessarily present quantization error. There are in the case of a digitally controlled oscillator, only discrete frequencies can be generated with a quantization step size dependent on the least significant bit. Because of such a digital control of the oscillator undesirable side lines arise at a distance in its output spectrum the switching frequency with which frequency-determining components in the oscillator be switched. Because the switching frequency is usually clear is less than the oscillator frequency, this leads to the violation of the spectral transmission mask. With the mobile radio system Bluetooth, for example must be the broadcast Performance, more precisely the so-called in-band spurious emission a measuring bandwidth of one megahertz at a distance greater than 3 MHz, a value smaller than –40 dBm. This is stated in the Bluetooth specification.

This could result in the undesired switching frequency repressed be that on Input of the oscillator a digital-to-analog (DA) converter is connected which converts the digital control word into an analog tuning voltage. Through such averaging at the output of the DA converter the clock frequency is suppressed. This approach has the serious disadvantage, however, that a highly precise and above all, very fast-working DA converter is necessary, due to the bit depth required a very big one Effort related to the integration of the function block would mean.

Object of the present invention is an inexpensive one integrable phase control arrangement to specify which to use in mobile devices according to modern, digital mobile radio standards and the specifications provided there comply.

• – einen digital steuerbaren Oszillator mit einem Steuereingang und mit einem Ausgang,
• – eine Phasen-/Frequenzvergleichseinrichtung mit einem ersten Eingang zum Zuführen eines Referenzsignals, mit einem zweiten Eingang, der mit dem Ausgang des Oszillators gekoppelt ist, und mit einem Ausgang zur Abgabe eines Fehlersignals und
• – ein Mittel zur Erhöhung der Abtastrate des Fehlersignals, welches den Ausgang der Phasen-/Frequenzvergleichseinrichtung mit dem Steuereingang des Oszillators koppelt.

According to the invention, the object is achieved by a phase control arrangement comprising

• A digitally controllable oscillator with one control input and one output,
• A phase / frequency comparison device with a first input for supplying a reference signal, with a second input which is coupled to the output of the oscillator, and with an output for outputting an error signal and
• - A means for increasing the sampling rate of the error signal, which couples the output of the phase / frequency comparison device to the control input of the oscillator.

According to the proposed principle a digitally operating phase control arrangement is provided, which due to the special control of the oscillator with an increased sampling rate of the digitally coded voting signal.

The reference sidebands of the Output spectrum are due to the oversampling of the digital Output word of the phase / frequency comparator outside of the useful band.

By the proposed increase in Sampling rate of the control signal or tuning signal of the oscillator Is it possible, spectral transmission masks also of modern, digital mobile radio standards when using cheaper, digital function blocks, in particular of a digitally tunable oscillator.

The oversampling of the digital tuning word of the oscillator according to the proposed one The principle is also known as oversampling.

The clock frequency with which the oversampling takes place, and which can be supplied to the means for increasing the sampling rate, is preferably significantly larger than the reference frequency of the phase locked loop.

According to a preferred development the invention a converter is provided which the output of the digital controllable oscillator couples to the second input of the phase / frequency comparator and which is designed to emit a digitally coded phase signal dependent on from the output frequency of the oscillator.

By supplying only the phase information of the oscillator and the output signal of the digitally controllable Oscillators can be a simple digital phase / frequency comparator, preferably a so-called digital fractional phase comparator is used become.

Is preferred between the exit of the digitally controllable oscillator and the converter that the output frequency assigns the digitally encoded phase signal to the oscillator limiting amplifier connected. This is preferably used to convert the output signal of the oscillator into a square wave or trapezoidal signal and thus enables one improved convertibility of the clock signal thus obtained into a Phase signal.

The means to increase the Sampling rate preferably has a clock input for synchronization purposes, which is coupled to the output of the oscillator.

Due to the preferred coupling of the Clock input of the means for increasing the sampling rate with the output of the oscillator can be digital Tuning signal, which is fed to the oscillator for its control, be synchronized to a clock frequency, which is advantageous with little effort of the circuit is significantly larger than the reference frequency the phase control arrangement.

The clock frequency for synchronization of the means to increase the sampling rate is preferred by frequency division from the signal obtained with the output frequency of the oscillator.

The frequency divider value of the frequency divider, the the output of the oscillator with the clock input of the means for increase the sampling rate preferably couples, can have a fixed value. This division value can be, for example, two or four.

To supply the reference signal an accumulator is preferably provided for the phase / frequency comparator, of the digital channel word on the input side at its Output assigns a phase reference signal and to the first input outputs the phase / frequency comparison device.

Just like the phase / frequency comparison device the accumulator also preferably has an input for feeding one Synchronization signal.

A synchronization device is preferred for this provided that an unsynchronized reference frequency signal is fed to the input can. The synchronization device itself has a clock input, which preferably with the output of the oscillator for feeding a Synchronization clock is coupled. The output of the synchronization device is preferred with a synchronization input of the accumulator connected. The output of the synchronization device is advantageous with a synchronization input of the phase / frequency comparison device connected.

The means to increase the Sampling rate includes preferably several D flip-flops. These are particularly low Effort can be integrated in digital circuit technology.

The digitally controllable oscillator comprises preferably two switchable capacitance fields, each of which determines the frequency capacities include. One of these capacity fields comprises preferably binary graded Capacities, while the switchable capacities of the further capacity field all are the same size, this means same capacity values exhibit. The capacities of both capacity fields are preferably independent from each other, but dependent from the tuning signal, can be switched on and off.

The control of the same capacities in the second capacity field is preferably done via a thermometer code. This is a particularly fine tuning the oscillator frequency possible, for example with a modulation signal. At the same time with the binary graded Capacities very big Frequency range with a relatively small Effort to be covered.

More details and advantageous Refinements of the proposed principle are the subject of Dependent claims.

The invention will follow several embodiments based on the drawings explained.

Show it:

1a an embodiment of the proposed principle using a block diagram,

1b an embodiment of a synchronization device for generating a synchronized reference frequency for the circuit according to 1a .

2 an embodiment of a digitally tunable oscillator for use in a phase control arrangement according to 1a .

3 a further development of the circuit of 1a to an exemplary one-point modulator,

4 a further development of the circuit of 3 to an exemplary two-point modulator and

5 a synchronization device according to 1b to generate a synchronized Reference frequency for the circuits according to 3 and 4 ,

1a shows a phase control arrangement with a digitally controllable oscillator 1 , also known as DCO, Digitally Controlled Oscillator. The oscillator 1 has a digital tuning input 2 for supplying a digitally coded voting word and a signal output 3 , on which a signal is provided with a frequency which is different from that at the input 2 attached voting word is dependent. The output of the oscillator 3 on the one hand forms the output of the phase control arrangement according to 1a and on the other hand is via a limiting amplifier 4 and a downstream converter 5 to an entrance 6 a phase comparator 7 connected. The phase comparator is designed as a so-called digital fractional phase comparator. The limiting amplifier 4 converts the output signal of the oscillator 1 into a trapezoidal, ideally rectangular clock signal with the frequency of the oscillator output signal. The output signal of the limiting amplifier 4 is on the clock input of a D flip-flop 8th given whose input to the output of a summing element 9 is connected and its output with an input of the summing element 9 connected is. At the increment input of the summation element 9 becomes a constant 1 created. The output of the summator 9 which is the output of the converter 5 forms, is designed to tap a phase signal ⌀ _div depending on the output clock signal of the oscillator 3 ,

The digital frequency / phase detector 7 has another entrance 10 , on which a phase signal with a reference phase ⌀ _{ref can be} supplied. In addition, the digital frequency / phase detector 7 has a clock input 11 at which a reference frequency f _{ref is} supplied.

The reference phase input 10 is at the output of another converter 12 connected, which, like the converter, is a D flip-flop 13 and a summing element designed as an accumulator 14 includes. Another input of the summing element 14 is designed to supply a digitally coded channel word with which the desired output frequency of the phase control arrangement shown can be set. The output of the summator 14 is on the one hand at the entrance 10 of the digital frequency / phase comparator 7 connected and on the other hand to the data input of the D flip-flop 13 placed. The output of the D flip-flop 13 is at an input of the accumulator 14 connected. The D flip-flop 13 has a clock input to which a signal with a reference frequency f _{ref can be} fed.

The output of the phase comparator 7 is about a multiplier 29 to the receipt of a means for increasing the sampling rate 30 connected. The multiplier 29 has another input for supplying a signal α and fulfills the function of a loop filter in conventional PLL. Accordingly, by appropriately dimensioning the signal α and / or the multiplier 29 the control loop can be dimensioned.

The means to increase the sampling rate 30 includes two D-flip-flops connected in series 32 . 33 that the output of the multiplier 29 with the tuning input of the oscillator 1 couple. Any D flip-flop 32 . 33 has a clock input that has a frequency divider 31 is connected to the output of the oscillator.

1b shows a synchronization device 15 to provide a signal with a reference frequency f _ref which is already synchronized with the output frequency of the oscillator 1 , Accordingly, the output of the synchronization device 15 suitable to the clock input of the D flip-flop 13 and to control that of the phase / frequency comparator 7. The synchronization device 15 includes two D-flip-flops connected in series 16 . 17 with one clock input each. The clock inputs of the two D flip-flops 16 . 17 are at the output of the oscillator 1 , the reference number 3 carries, coupled. At the input of the D flip-flop on the input side 16 an unsynchronized reference frequency f _{ref, unsync can be} supplied.

The quantization error of the digitally tunable oscillator DCO can be described by ƒ out = ƒ 0 + x · ƒ LSB , with x = x n-1 2 n-1 + ... + x 1 2 1 + x 0 2 0 ,

Here, f ₀ denotes the oscillator frequency for the control variable x = 0 and f _LSB the quantization step size with regard to the discrete adjustable frequencies.

The output word of the digital fractional phase comparator 7 is clocked at the clock frequency f _ref of 13 megahertz in the present case. This output word is used to increase the sampling rate 30 oversampled and synchronized to the divided output clock frequency f _{clk, div of} the oscillator, which is significantly larger than the reference frequency f _ref. The divider value n of the frequency divider is fixed and is, for example, 2 or 4. The reference sidebands are therefore outside the Bluetooth frequency band. Compliance with the spectral transmission mask is possible without any problems. According to the Bluetooth specification, the transmitted power outside the 2.4 gigahertz ISM (Industrial Scientific and Medical) band must be less than -47 dBm. This transmitted power is referred to as out-of-band spurious emission. With Bluetooth this is only reduced by 7 dBm compared to the so-called in-band spurious emission. However, due to the suppression of a connected antenna filter and a matching circuit, which are normally present anyway in mobile radio devices according to Bluetooth or other modern mobile radio methods, this requirement can be met much more easily.

The phase control arrangement according to 1a with the synchronization device according to 1b is implemented as a purely digital high-frequency PLL. The system costs can thus be reduced considerably, since on the one hand there is no need for an external loop filter and on the other hand the complex analog function blocks mentioned at the beginning are also not necessary. Nevertheless, due to the over-sampling of the tuning signal of the oscillator, spectral transmission masks, which are specified in the respective specifications of mobile radio standards, can be adhered to without any problems.

A further reduction of undesirable emissions is possible with the present principle in that the energy of the switching frequency is not concentrated on discrete frequency components, but rather the energy is distributed. This is also known as noise shaping or dithering. This dithering method is known from analog / digital converters and can also be used to control the digital oscillator 1 be used.

2 shows an embodiment of a digitally tunable oscillator 1 , which is designed as an LC oscillator with a symmetrical structure. A power source 18 is to a supply potential connection 19 connected. To the power source 18 are two inductors 20 . 21 connected, which with their free connections the output 3 form the oscillator. To this exit 3 is a first and a second capacity field 22 . 23 connected as well as a damping amplifier 24 , the two cross-coupled MOS transistors 25 . 26 includes. The transistors 25 . 26 of the damping amplifier 24 are each with a load connection to a reference potential connection 27 placed. The two capacity fields 22 . 23 each include several capacities that can be switched on and off independently of one another. In the first capacity field 22 the capacities are graduated in binary. This means that, for example, a first capacitance has the capacitance value C, a second has twice the capacitance value, a third has four times, a fourth has eight times, and so on. In the second capacity field 23 however, all switchable capacities are equipped with the same capacity value. The entrance 2 of the oscillator 1 is on the one hand with a control input of the first capacity field 22 connected to the rough channel selection, while a fine tuning by means of the second capacity field 23 takes place, the control input via a converter 28 according to a thermometer code at the entrance 2 of the oscillator.

In order to avoid monotonous errors, the low-order bits of the tuning word with unit capacities in the capacity field 23 realized and controlled via a thermometer code. The capacity fields are expedient 22 . 23 designed in such a way that they are used for the modulation. With Bluetooth, for example, Gaussian frequency shift keying (GFSK modulation) with a modulation deviation of ± 160 kHz is used. To quantize this area with a resolution of about 5 kHz and taking into account a certain reserve, 7 bits are required. This corresponds to a frequency change of about 2 ppm, which in turn corresponds to a change in capacity in the Attofarad area. This very fine frequency resolution is preferably achieved by interpolation, for example by means of a sigma-delta modulator, in which a quantization is achieved by switching between the capacitance values, which is smaller than the smallest switchable frequency-determining capacitance of the oscillator. The higher bits control a binary weighted capacity field 22 used for the channel setting. 8 bits are required to cover the 85 MHz wide Bluetooth frequency band.

The high-frequency oscillator shown 1 has a high quality. A very fine frequency resolution is achieved with the very small, switchable capacities that are controlled with a thermometer code.

3 shows a development of the circuit of 1a , which largely coincides with this in the components used, their interconnection with one another and the advantageous mode of operation. In this respect, the description of the figures should not be repeated here. In addition, when switching from 3 at the entrance of the accumulator 12 the output of an adder 34 connected. The adding node 34 has two digital inputs, a first of which is designed for supplying a channel word and a second is designed as a modulation input for supplying a modulation signal MOD.

The reference phase signal φ _ref is therefore formed not only as a function of the channel word, but also from the modulation signal.

With the present feed of modulation data in the reference branch of the phase control arrangement one also speaks of a direct modulation of the reference phase or a single point modulation.

Such phase control arrangements are particularly suitable for use in mobile radio transmission arrangements suitable.

4 shows a development of the circuit of 3 which largely coincides with this in the components used, their interconnection with one another and the advantageous mode of operation. In this respect, the description of the figures should not be repeated here. In addition, when switching from 4 another adder 35 provided which the output of the means for increasing the sampling rate 30 with the voting entrance 2 of the oscillator 1 combines. The further adding node 35 has an additional input for supplying the modulation signal MOD.

This is a two-point modulator arrangement created. An advantage is that the bandwidth of the modulation signal can be larger than the bandwidth of the phase controller itself.

Such phase control arrangements are particularly suitable for use in mobile radio transmission arrangements with high transfer rates suitable.

5 shows a development of the synchronization device 15 of 1b , with which it largely corresponds in structure and advantageous mode of operation. In this respect, the description should not be repeated here. When switching from 5 becomes the unsynchronized reference frequency f _{ref, unsync} , which corresponds to the data input of the input flip-flop 16 is supplied by means of a quartz oscillator 36 . 37 generated. This quartz oscillator comprises a quartz crystal 37 to which an active circuit 36 is connected, which includes capacitors and an attenuation amplifier. At the output of the oscillator, which with the reference signal input of the synchronization device 15 is connected, a very precise and highly stable quartz frequency is thus provided.

1

oscillator

2

entrance

3

output

4

limiter

5

converter

6

entrance

7

digital fractional phase detector

8th

D flip-flop

9

summing

10

entrance

11

clock input

12

accumulator

13

D flip-flop

14

summing

15

synchronizer

16

D flip-flop

17

D flip-flop

18

power source

19

supply terminal

20

Kitchen sink

21

Kitchen sink

22

capacity field

23

capacity field

24

amplifier

25

transistor

26

transistor

27

Reference potential connection

28

Thermometer code converter

29

multipliers

30

medium to increase the sampling rate

31

frequency divider

32

D flip-flop

33

D flip-flop

34

adding node

35

adding node

36

oscillator

37

quartz crystal

Claims (10)

Phase control arrangement for frequency synthesis, comprising - a digitally controllable oscillator ( 1 ) with a control input ( 2 ) and with an output ( 3 ), - a phase / frequency comparison device ( 7 ) with a first entrance ( 10 ) for supplying a reference signal (φ _ref ), with a second input ( 6 ) with the output ( 3 ) of the oscillator ( 1 ) is coupled, and with an output for emitting an error signal and - a means for increasing the sampling rate ( 30 ) of the error signal, which the output of the phase / frequency comparison device ( 7 ) with the control input ( 2 ) of the oscillator ( 1 ) couples. Phase control arrangement according to Claim 1, characterized in that a converter ( 5 ) is provided, which is the output ( 3 ) of the oscillator with the second entrance ( 6 ) of the phase / frequency comparison device ( 7 ) couples, designed to deliver a digitally coded phase signal (φ _div ) depending on the output frequency (f _dco ) of the oscillator. Phase control arrangement according to claim 2, characterized in that a limiting amplifier ( 4 ) is provided between the output ( 3 ) of the oscillator ( 1 ) and an input of the converter ( 5 ) is switched. Phase control arrangement according to one of Claims 1 to 3, characterized in that the means for increasing the sampling rate ( 30 ) has a clock input that is connected to the output ( 3 ) of the oscillator ( 1 ) is coupled to synchronize the means for increasing the sampling rate ( 30 ). Phase control arrangement according to claim 4, characterized in that a frequency divider ( 31 ) is provided, which is the output ( 3 ) of the oscillator with the clock input of the means for increasing the sampling rate ( 30 ) couples. Phase control arrangement according to one of Claims 1 to 5, characterized in that at the first input of the phase / frequency comparison device ( 7 ) an accumulator ( 12 ) is connected to its output, which assigns the reference signal (φ _ref ) as a phase signal to a digital channel word at its input and outputs it at its output. Phase control arrangement according to one of Claims 1 to 6, characterized in that a synchronization device ( 15 ) is provided with an output that is connected to a synchronization input of the accumulator ( 12 ) is coupled with a first input for supplying an unsynchronized reference signal (f _{ref, unsync} ) and with a clock input which is connected to the output ( 3 ) of the oscillator ( 1 ) for supplying the output frequency (f _dco ) of the oscillator ( 1 ) is coupled. Phase control arrangement according to claim 7, characterized in that the output of the synchronization device ( 15 ) with a synchronization input ( 11 ) of the phase / frequency comparator ( 7 ) connected is. Phase control arrangement according to one of Claims 1 to 8, characterized in that the means for increasing the sampling rate ( 30 ) at least one D flip-flop ( 32 ) includes. Phase control arrangement according to one of Claims 1 to 9, characterized in that the oscillator ( 1 ) a binary staggered, switchable capacity field ( 22 ) and another capacity field ( 23 ) each with the same size, switchable capacities.