DE10239642B3 - Complementary metal oxide semiconductor/bipolar complementary metal oxide semiconductor - integrated circuit for camera chip has single individual layer as last layer of passivation system sealing off integrated circuit - Google Patents
Complementary metal oxide semiconductor/bipolar complementary metal oxide semiconductor - integrated circuit for camera chip has single individual layer as last layer of passivation system sealing off integrated circuit Download PDFInfo
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- DE10239642B3 DE10239642B3 DE2002139642 DE10239642A DE10239642B3 DE 10239642 B3 DE10239642 B3 DE 10239642B3 DE 2002139642 DE2002139642 DE 2002139642 DE 10239642 A DE10239642 A DE 10239642A DE 10239642 B3 DE10239642 B3 DE 10239642B3
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- cmos
- passivation
- electrically conductive
- integrated circuit
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- 238000002161 passivation Methods 0.000 title claims abstract description 16
- 230000000295 complement effect Effects 0.000 title 2
- 229910044991 metal oxide Inorganic materials 0.000 title 2
- 150000004706 metal oxides Chemical class 0.000 title 2
- 239000004065 semiconductor Substances 0.000 title 2
- 238000007789 sealing Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 13
- 230000003287 optical effect Effects 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 2
- 230000005540 biological transmission Effects 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
Die Erfindung bezieht sich auf CMOS/BiCMOS-Technologien mit integrierten fotoempfindlichen Strukturen, vorzugsweise Fotodioden, speziell auf den Schichtaufbau von Abdeckschichten und elektrisch leitfähigen transparenten Schichten zur elektronischen Abschirmung der fotoelektrisch aktiven Regionen.The invention relates to CMOS / BiCMOS technologies with integrated photosensitive structures, preferably photodiodes, especially on the layer structure of cover layers and electrically conductive transparent layers for electronic shielding of the photoelectric active regions.
Integrierte Schaltkreise moderner CMOS-Technologien haben als essentiellen Bestandteil durch pn-Übergänge isolierte Gebiete unterschiedlicher Leitfähigkeit, die als Drain/Source, Wannen, bzw. integrierte Widerstände wirken. Es bietet sich an, diese dem Prozeß immanenten Diodenstrukturen auch als Detektoren für optische Signale zu verwenden (Fotodioden) und damit auf einem Chip Sensor und Auswerteelektronik zu integrieren.Integrated circuits of modern CMOS technologies have as essential ingredient by pn junctions isolated areas of different Conductivity, which act as drain / source, wells, or integrated resistors. It makes sense, these intrinsic diode structures in the process also as detectors for to use optical signals (photodiodes) and thus on a chip sensor and to integrate evaluation electronics.
Mittlerweile ist es Stand der Technik, solche Dioden zu integrieren. Insbesondere Kamerachips auf CMOS-Basis sind echte Alternativen gegenüber CCD-Kameras. Das einfallende Licht erreicht im allgemeinen auch die Diodenstruktur im Silizium-Chip, da die über dem Silizium liegenden isolierenden Deckschichten aus Siliziumoxid und Siliziumnitrid bestehen, die für Licht im sichtbaren Bereich transparent sind, wie auch spezielle elektrisch leitfähige Schichten. Letztere sind notwendig, um z.B. bei Optokopplern kapazitive Einkopplungen zu vermeiden, die ansonsten zu Signalstörungen führen. Ein wesentliches Problem liegt nun darin, daß die auf der fertig prozessierten Siliziumscheibe liegenden Schichten in ihrer Dicke nicht auf maximale optische Transparenz angepaßt sind, so daß es zu Intensitätsverlusten kommt. Im allgemeinen liegen 3 bis 5 und teilweise noch mehr verschiedene Schichten übereinander, die eine Gesamtschichtdicke von 1 bis 3 μm und mehr ergeben. Die Dicke dieses Schichtaufbaus liegt also in der Größenordnung der Lichtwellenlängen (bis einige Vielfache) so daß infolge von Interferenzen an dünnen Schichten je nach Wellenlänge und aktueller Schichtdicke der Anteil des durchgehenden Lichtes reduziert sein kann. Speziell zum quanti tativen Detektieren monochromatischen Lichtes kann bereits die normale Prozeßtoleranz der Dicke bei der Schichtabscheidung (+/– 10%) auf einer einzelnen Siliziumscheibe Gebiete maximaler Transmission und auch Gebiete maximaler Reflexion ergeben, d.h. die transmittierte Lichtmenge einer monochromatischen Lichtquelle, die in der Fotodiode ankommt, kann bezogen auf eine Siliziumscheibe bis 40% schwanken.Meanwhile, it is state of the art, to integrate such diodes. In particular camera chips based on CMOS are real alternatives to CCD cameras. The incident light generally also reaches the diode structure in the silicon chip, there the above the silicon lying insulating layers of silicon oxide and silicon nitride, which are visible to light are transparent, as well as special electrically conductive layers. The latter are necessary, e.g. with optocouplers capacitive couplings to avoid, which otherwise lead to signal interference. A major problem lies now in the fact that the on the finished silicon wafer are not matched in their thickness to maximum optical transparency, so that it to intensity losses comes. In general, there are 3 to 5 and sometimes even more different Layers on top of each other, which give a total layer thickness of 1 to 3 microns and more. The fat This layer structure is therefore in the order of the wavelengths of light (to a few multiples) so that as a result from interferences to thin ones Layers depending on the wavelength and current layer thickness reduces the proportion of transmitted light can be. Especially for quantitative monochromatic detection Light may already have the normal process tolerance of thickness in the Layer deposition (+/- 10%) areas of maximum transmission on a single silicon wafer and also provide areas of maximum reflection, i. the transmitted Amount of light from a monochromatic light source in the photodiode arrives, can vary with respect to a silicon wafer to 40%.
Aus der
Weiterhin ist eine sich auf dem lichtempfindlichen
Gebiet eines IC mit integrierter Fotodiodebe findliche Siliziumnitridschicht
aus der Schrift
Es ist Aufgabe der Erfindung, im Bereich der fotoempfindlichen und vor fremder elektrischer Einkopplung zu schützenden Strukturen der Schaltung die Kombination von Abdeckschichten und transparenten elektrisch leitfähigen Schichten so zu gestalten, daß die Lichtverluste durch Interferenz weitestgehend vermindert werden (Maximierung der Transmission) und eine größere Gleichmäßigkeit der Lichttransparenz in der Verteilung über die einzelne Siliziumscheibe und bezogen auf die verschiedenen Siliziumscheiben untereinander gewährleistet ist.It is the object of the invention in the Range of photosensitive and external electrical coupling to be protected Structures of the circuit the combination of cover layers and transparent electrically conductive Layers to be designed so that the Loss of light due to interference are largely reduced (Maximizing transmission) and greater uniformity the light transparency in the distribution over the single silicon wafer and based on the different silicon wafers with each other guaranteed is.
Zweck der Erfindung ist die Verbesserung der CMOS/BiCMOS-Technologien mit integrierten fotoempfindlichen Strukturen und elektrischer Abschirmung bezüglich Kosten durch Ausbeutesteigerung und durch möglichst geringen Fertigungsmehraufwand.The purpose of the invention is the improvement of CMOS / BiCMOS technologies with integrated photosensitive structures and electrical shielding in terms of Costs due to yield increase and as little as possible additional production costs.
Die Aufgabe wird so gelöst, daß dafür gesorgt wird, daß über den Gebieten der fotoempfindlichen Strukturen ein Doppelschichtsystem, bestehend aus der im Prozeß zuletzt folgenden Isolatorschicht des üblichen Abschlußschichtsystems und der dieser folgenden transparenten elektrisch leitfähigen Schicht mit so abgestimmten einzelnen Dicken vorhanden ist, die in der Summe einer optischen Dicke des Schichtsystems mit maximaler Transparenz bei vermindertem Dickentoleranzeinfluß vorhanden ist.The task is solved so that ensured will that about the Areas of photosensitive structures a double layer system, consisting of the last in the process following insulator layer of the usual Close layer system and the following transparent electroconductive layer with such tuned single thicknesses is present, which in total an optical thickness of the layer system with maximum transparency diminished thickness tolerance influence is present.
Über den entsprechenden lichtempfindlichen Gebieten, insbesondere Fotodioden aber auch Fotogates, wird also ein nur aus zwei Schichten bestehendes Schichtsystem angeordnet, dessen optische Dicke (Brechzahl Schichtdicke) dahingehend auf die Wellenlänge abgestimmt wird, daß die Transmission maximal ist (D = λ/4 bzw. ungerade Vielfache davon) und die unvermeidliche Toleranz der Dicke nach dem Abscheiden (i.a. +/– 10%) noch nicht von Verstärkung zur Auslöschung des durchgehenden Lichtes führt.over the corresponding photosensitive areas, in particular photodiodes but also photogates, so it will be only two layers Layer system arranged whose optical thickness (refractive index layer thickness) to the wavelength it is agreed that the Transmission is maximum (D = λ / 4 or odd multiples thereof) and the inevitable tolerance of Thickness after deposition (i.a. +/- 10%) not yet from reinforcement to extinction of the passing light leads.
In der Praxis sieht das so aus, daß der CMOS- bzw. BiCMOS-Prozeß unverändert bis einschließlich der letzten Metallisierung abläuft. Das üblicherweise danach abzuscheidende Passivierungsschichtsystem hat mehrere Aufgaben zu erfüllen: elektrische Isolation zur Umwelt, mechanischer Schutz, Schutz gegenüber Feuchte und gegebenenfalls auch Getterwirkung (z.B. durch eingebauten Phosphor). Beispielhaft wird von einem solchen Doppelschichtsystem der Passivierung, bestehend aus einer ersten Schicht aus Siliziumoxinitrid, gefolgt von einer Schicht aus Siliziumnitrid ausgegangen. In der erfindungsgemäßen Prozeßfolge wird das Siliziumoxinitrid standardgemäß abgeschieden (falls dieses gettern soll, können Getterzentren eingebracht werden). Danach erfolgt ein fotolithografischer Prozeß, beidem die lichtempfindlichen Gebiete freigelegt werden. Dabei werden im Bereich der fotoempfindlichen Strukturen alle Schichten über der Siliziumoberfläche entfernt, was bedingt durch die Grenzfläche SiO2/Si ausreichend präzise möglich ist. Es versteht sich, daß die Öffnungen der Fotomaske hinreichend großen Abstand zu Metallleitbahnen und zu an die Oberfläche stoßenden pn-Übergängen haben müssen (pn-Übergänge dürfen nicht freigelegt werden). Nach dem Entfernen der Lackmaske wird dann die das Passivierungssystem komplettierende Siliziumnitridschicht mit einer definierten Schichtdicke abgeschieden, die zu der Dicke der später noch aufzubringenden transparenten elektrisch leitfähigen Schicht paßt. Zunächst folgt die Öffnung der Kontakte in der Passivierungsschicht, für die Verbindung zwischen der oberen Metallschicht und der abschirmenden Schicht. Nach Öffnen der Kontakte erfolgt die Abscheidung der transparenten leitfähigen Schicht, gefolgt von deren Strukturierung. Die optische Dicke des Schichtsystems Passivierungsschicht/transparente leitfähige Schicht wird in an sich bekannter Weise so gewählt, daß für einen gegebenen Lichtwellenlängenbereich maximale Transmission auftritt. Bei Bedarf können die Schichtdicken so modifiziert werden, daß für eine gegebene Wellenlänge maximale Transmission auftritt.In practice, this looks like the CMOS or BiCMOS process is unchanged until a finally the last metallization expires. The passivation layer system usually to be deposited thereafter has several tasks to fulfill: electrical insulation to the environment, mechanical protection, protection against moisture and possibly also gettering effect (eg by means of incorporated phosphorus). By way of example, it is assumed that such a double-layer system of the passivation, consisting of a first layer of silicon oxynitride, followed by a layer of silicon nitride. In the process sequence according to the invention, the silicon oxynitride is deposited by default (if this is to getter, getter centers can be introduced). Thereafter, a photolithographic process is performed, exposing the photosensitive areas. In the process, all layers above the silicon surface are removed in the region of the photosensitive structures, which is sufficiently precisely possible due to the SiO 2 / Si interface. It is understood that the openings of the photomask must be sufficiently large distance to metal tracks and to the surface pending pn junctions (pn junctions must not be exposed). After removal of the resist mask, the silicon nitride layer which completes the passivation system is then deposited with a defined layer thickness, which matches the thickness of the transparent electrically conductive layer to be applied later. First, the opening of the contacts in the passivation layer, for the connection between the upper metal layer and the shielding layer follows. After opening the contacts, the deposition of the transparent conductive layer takes place, followed by its structuring. The optical thickness of the layer system passivation layer / transparent conductive layer is chosen in a manner known per se so that maximum transmission occurs for a given wavelength range of light. If necessary, the layer thicknesses can be modified so that maximum transmission occurs for a given wavelength.
Schichtdickentoleranzen um 10% haben nur noch marginalen Einfluß. Nach dieser Schichtabscheidung erfolgt standardmäßig die Strukturierung der Bondpads. Wenn die Isolatorschicht aus Siliziumnitrid besteht und die darüber befindliche transparente leitfähige aus Indiumzinnoxid (ITO-Schicht), liegt der Fall vor, daß die Brechzahlen beider Schichten annähernd gleich sind, so daß die Dickenoptimierung des Doppelschichtsystems relativ einfach ist.Have layer thickness tolerances of 10% only marginal influence. After this layer deposition, the structure of the Bond pads. If the insulator layer consists of silicon nitride and the above located transparent conductive from indium tin oxide (ITO layer), there is the case that the refractive indices approximate both layers are the same, so that the Thickness optimization of the double layer system is relatively simple.
Claims (6)
Priority Applications (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2002139642 DE10239642B3 (en) | 2002-08-29 | 2002-08-29 | Complementary metal oxide semiconductor/bipolar complementary metal oxide semiconductor - integrated circuit for camera chip has single individual layer as last layer of passivation system sealing off integrated circuit |
DE50311172T DE50311172D1 (en) | 2002-08-29 | 2003-08-29 | MINIMIZING LIGHT LOSSES AND ELECTRONIC SHIELDING IN INTEGRATED PHOTODIODS |
EP03750301A EP1535339A2 (en) | 2002-08-29 | 2003-08-29 | Integrated photosensitive structures and passivation method |
DE10393435T DE10393435D2 (en) | 2002-08-29 | 2003-08-29 | Integrated photosensitive structures and passivation processes |
AU2003269691A AU2003269691A1 (en) | 2002-08-29 | 2003-08-29 | Integrated photosensitive structures and passivation method |
AT03753262T ATE422712T1 (en) | 2002-08-29 | 2003-08-29 | MINIMIZATION OF LIGHT LOSS AND ELECTRONIC SHIELDING ON INTEGRATED PHOTODIODES |
AU2003271515A AU2003271515A1 (en) | 2002-08-29 | 2003-08-29 | Minimisation of light losses and electronic shielding on integrated photodiodes |
PCT/DE2003/002873 WO2004021452A2 (en) | 2002-08-29 | 2003-08-29 | Integrated photosensitive structures and passivation method |
EP03753262A EP1532691B1 (en) | 2002-08-29 | 2003-08-29 | Minimisation of light losses and electronic shielding on integrated photodiodes |
PCT/DE2003/002874 WO2004021453A2 (en) | 2002-08-29 | 2003-08-29 | Minimisation of light losses and electronic shielding on integrated photodiodes |
DE10393329T DE10393329D2 (en) | 2002-08-29 | 2003-08-29 | Minimization of light losses and electronic shielding on integrated photodiodes |
Applications Claiming Priority (1)
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DE2002139642 DE10239642B3 (en) | 2002-08-29 | 2002-08-29 | Complementary metal oxide semiconductor/bipolar complementary metal oxide semiconductor - integrated circuit for camera chip has single individual layer as last layer of passivation system sealing off integrated circuit |
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DE10239642B3 true DE10239642B3 (en) | 2004-06-24 |
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DE2002139642 Expired - Fee Related DE10239642B3 (en) | 2002-08-29 | 2002-08-29 | Complementary metal oxide semiconductor/bipolar complementary metal oxide semiconductor - integrated circuit for camera chip has single individual layer as last layer of passivation system sealing off integrated circuit |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102009012546A1 (en) | 2009-03-10 | 2010-09-23 | X-Fab Semiconductor Foundries Ag | Mono anti-reflection silicon nitride layer for use on switching circuits with e.g. photodiodes, by single-step plasma enhanced chemical vapor deposition method, is designed as protective layer against data degradation of elements |
US8058086B2 (en) | 2005-10-10 | 2011-11-15 | X-Fab Semiconductor Foundries Ag | Self-organized pin-type nanostructures, and production thereof on silicon |
US8350209B2 (en) | 2005-10-10 | 2013-01-08 | X-Fab Semiconductor Foundries Ag | Production of self-organized pin-type nanostructures, and the rather extensive applications thereof |
DE102005048365B4 (en) * | 2005-10-10 | 2015-01-22 | X-Fab Semiconductor Foundries Ag | Method of anti-reflection of an integrated silicon photodiode by self-organized nanostructures and photosensitive device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6449282A (en) * | 1987-08-19 | 1989-02-23 | Mitsubishi Electric Corp | Integrated circuit device with built-in photodiode |
DE3851784T2 (en) * | 1987-06-12 | 1995-03-02 | Canon Kk | Photosensor, manufacturing process and image reader with such a sensor. |
DE69519983T2 (en) * | 1995-01-11 | 2001-06-28 | At&T Corp., New York | Metal semiconductor metal photodetectors |
-
2002
- 2002-08-29 DE DE2002139642 patent/DE10239642B3/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3851784T2 (en) * | 1987-06-12 | 1995-03-02 | Canon Kk | Photosensor, manufacturing process and image reader with such a sensor. |
JPS6449282A (en) * | 1987-08-19 | 1989-02-23 | Mitsubishi Electric Corp | Integrated circuit device with built-in photodiode |
DE69519983T2 (en) * | 1995-01-11 | 2001-06-28 | At&T Corp., New York | Metal semiconductor metal photodetectors |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8058086B2 (en) | 2005-10-10 | 2011-11-15 | X-Fab Semiconductor Foundries Ag | Self-organized pin-type nanostructures, and production thereof on silicon |
US8350209B2 (en) | 2005-10-10 | 2013-01-08 | X-Fab Semiconductor Foundries Ag | Production of self-organized pin-type nanostructures, and the rather extensive applications thereof |
DE102005048365B4 (en) * | 2005-10-10 | 2015-01-22 | X-Fab Semiconductor Foundries Ag | Method of anti-reflection of an integrated silicon photodiode by self-organized nanostructures and photosensitive device |
DE102009012546A1 (en) | 2009-03-10 | 2010-09-23 | X-Fab Semiconductor Foundries Ag | Mono anti-reflection silicon nitride layer for use on switching circuits with e.g. photodiodes, by single-step plasma enhanced chemical vapor deposition method, is designed as protective layer against data degradation of elements |
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