DE102022211478A1 - Circuit and method for operating the same - Google Patents

Abstract

Circuit (10), with the following features: a converter circuit (12) which has a DC voltage connection with two potential taps (20a, 20b) and one or more phase connections (18a, 18b, 18a', 18b', 18c'); and a controller (25), wherein the controller (25) is designed to control switchable elements (14) of the converter circuit (12) such that a voltage at one of the two potential taps (20a, 20b) and/or at one of the one or more phase connections (18a, 18b, 18a', 18b', 18c') is modulated based on a common mode voltage; wherein the common mode voltage is calculated.

Description

Embodiments of the present invention relate to an (electrical) circuit with a power converter circuit and to a corresponding operating method. According to different aspects of the invention, there are circuits designed for different applications (for example TN-C-S system, TN-S system or TT system). Further embodiments relate to a computer-implemented method. Preferred embodiments relate to a method for reducing leakage currents for non-insulating rectifiers.

When operating non-isolating rectifiers (AC-DC conversion, unidirectional or bidirectional), the common mode voltage of the rectifier creates leakage currents in the Y capacitors of the rectifier and the connected DC source or sink.

1 shows a simplified common mode equivalent circuit of a typical rectifier 100 and its EMC filter 102. High frequency components of the common mode voltage can be reduced by the common mode inductances L _CM of the filter 102. For low frequency components, e.g. 50 Hz, practically impossible to realize inductance values for L _CM would be necessary in order to reduce the occurring operating currents through C _CM (galvanic coupling to the neutral conductor) below the limit value (cf. [1]).

In the publication [1] it is described that with the B6 topology and the EMC filter used it is not possible to reduce the leakage currents below the limit. In a later publication [2] it is described that the problem of leakage currents for the three-phase topology can be reduced by a DC link symmetry controller for the capacitors.

In single-phase operation, the usual H4 bridge topology produces a high low-frequency common-mode voltage and thus leakage currents, which, as described, cannot be meaningfully reduced with common-mode filter chokes.

In the publication [3] the 2 The circuit topology shown is presented, in which the neutral conductor connection 108 (area V2-PFC) is connected to the intermediate circuit center 110 (area V2-PFC). The additional intermediate circuit symmetrization 112 (area BC) keeps the voltages ν _C1 and ν _C2 symmetrical during operation (ν _C1 = _νC2 ). This is necessary because the phase current i ₁ in single-phase operation would otherwise cause a periodic fluctuation in the voltages ν _C1 and ν _C2 . The active filter 114 (ripple port RP) balances out the power consumption from the power grid, which pulsates at 100 Hz, by making the total power constant through antiphase control. This allows the total voltage ν _C1 + ν _C2 to be kept constant.

Since the voltage at ν _C2 is kept constant in theory, the low-frequency leakage current through C _CM can be greatly reduced.

A major challenge is the precise control of the power of the active filter 114 (range RP). This can only be done with limited dynamics. Furthermore, displacement voltages and potential differences between the operational and system earthing cannot be compensated.

In the area of modulation methods, there are a number of approaches in the literature for reducing leakage currents. The publication [4] describes an approach that is intended to reduce leakage currents when driving a motor. In this approach, as in the solution described in Chapter 3, the impedance of the filter elements is taken into account. However, a fourth leg/half bridge is required for control. A fluctuating intermediate circuit voltage is not taken into account.

Therefore, there is a need for an improved approach.

The object of the present invention is to create a concept that minimizes common mode voltages and currents over a wide frequency range.

The problem is solved by the subject matter of the independent patent claims.

• - Schwankung der Gesamt-Zwischenkreisspannung
• - Spannungsabfall an Filter- und Netzimpedanz
• - Verlagerungsspannung
• - Potentialdifferenz zwischen Betriebs- und Anlagenerder
• - Schwankungen der Zwischenkreisspannung ν_DC, besonders wichtig im einphasigen Betrieb
• - unsymmetrische Ströme im dreiphasigen Betrieb z.B. Oberschwingungen oder Schieflast

Embodiments of the present invention provide a circuit with a power converter circuit and a corresponding control. The power converter circuit has a DC voltage connection with two potential taps and one or more phase connections. The control is made of formed to control switchable elements of the converter circuit, such as transistors of an H4 or B6 bridge or generally transistors of the converter circuit, namely in such a way as to modulate a voltage at one of the two potential taps and/or at one or more phase connections based on a common mode voltage. The common mode voltage ν _CCM is influenced by the following factors, among others:

• - Fluctuations in the total intermediate circuit voltage
• - Voltage drop across filter and mains impedance
• - Displacement stress
• - Potential difference between operational and system earthing
• - Fluctuations in the intermediate circuit voltage ν _DC , particularly important in single-phase operation
• - asymmetrical currents in three-phase operation, e.g. harmonics or unbalanced load

Embodiments of the invention show four methods for determining the common mode voltage V _CM for the modulation of the converter circuit, which partially or completely take into account the (above) factors influencing the common mode voltage ν _CCM . Based on the calculation of the common mode voltage ν _CCM using these methods, the calculated common mode voltage ν _CCM can be compensated by modulating the voltage at one of the two potential taps and/or at one or more phase connections, taking into account the calculated common mode voltage ν _CCM . The methods for calculating the common mode voltage ν _CCM and thus also for compensating it can be used separately or in combination.

Individual calculation methods and preferred combinations are explained below.

berechnet werden. ν_DC ist der Messwert der Spannung zwischen zwei Potenzialabgriffen des Gleichspannungsanschlusses. Die Spannung $\overline{V_{DC}}$

ist der Mittelwert der gemessenen Spannung oder z.B. der Sollwert einer geregelten Zwischenkreisspannung.A fluctuating total intermediate circuit voltage ν _DC leads to a fluctuating common mode voltage ν _CCM during operation. This influence can be calculated according to a first method based on the formula $$v_{CM}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}$$

ν _DC is the measured value of the voltage between two potential taps of the DC voltage connection. The voltage $\overline{V_{DC}}$

is the mean value of the measured voltage or, for example, the setpoint of a regulated intermediate circuit voltage.

auf Basis folgender Formel berechnet. $$v_{CM}^{*}=v_{DC-PE}+\frac{\overline{V_{DC}}}{2}$$

According to a second method, the common mode voltage $v_{CM}^{*}$

calculated based on the following formula. $$v_{CM}^{*}=v_{DC-PE}+\frac{\overline{V_{DC}}}{2}$$

auf Basis folgender Formel berechnet: $$v_{CM}^{*}=-v_{CX}+\frac{\overline{V_{DC}}}{2}-v_{C2}$$

According to a third method, the common mode voltage $v_{CM}^{*}$

calculated based on the following formula: $$v_{CM}^{*}=-v_{CX}+\frac{\overline{V_{DC}}}{2}-{\mathrm{<figure-callout\; id="2"\; label="v\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_C$$

berechnet werden.According to a fourth method, the common mode voltage ν _CM can alternatively be calculated based on the formula $$v_{CM}=R\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$$

be calculated.

The methods partially allow the composition of different influencing factors, as will be explained in detail below. Preferred, exemplary combinations are methods 1+2 and 1+4, because (firstly) all essential influencing factors (including filter influences) can be compensated and (secondly) good dynamics are achieved.

Embodiments of the present invention are based on the knowledge that the leakage currents of a capacitor C _CM connected on the DC side or generally of a capacitance present or formed on the DC side can be reduced by a clever control method (for the converter circuit, such as a non-isolated rectifier or AC-DC converter). By choosing half the average fluctuation as the modulation size, the common mode voltage is modulated with respect to ground potential so that this voltage ν _CCM is kept constant at the capacitance C _CM and leakage currents via the capacitor C _CM are avoided. This advantageously enables the control method for the common mode modulation of, for example, the B6 bridge in three-phase operation or an H4 bridge in single-phase operation to greatly reduce the fluctuation of the voltage ν _CCM and thus also reduce leakage currents through C _CM . It should be noted that ν _CM represents the modulation voltage with which the semiconductors are controlled. ν _CCM is the actual voltage across the capacitor C _CM . The two voltages are interdependent but different, as 9a to 9d show.

$v_{CM}^{*}=v_{DC-PE}+\frac{\overline{V_{DC}}}{2}$

$v_{CM}^{*}=-v_{CX}+\frac{\overline{V_{DC}}}{2}-v_{C2}$

$v_{CM}=R\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$

Kompensation der Schwankung der Zwischenkreisspannung Kompensation eines Spannungsabfall an Filter- und Netzimpedanz Kompensation Verlagerungsspann ung, Potentialdifferenz, und/oder Betriebs-/ Anlagenerder The following table shows an overview of the calculation methods for the common mode voltage, which is then used for modulation in accordance with the implementation examples. The table for the calculation methods for the common mode voltage also assigns the different quantities to be compensated to the individual calculation methods. The calculation methods can also be used in combination. Combination 1+4 is explained below as an example. Method 1 Method 2 Method 3 Method 4 $v_{cm}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}$

$v_{CM}^{*}=v_{DC-PE}+\frac{\overline{V_{DC}}}{2}$

$v_{CM}^{*}=-v_{CX}+\frac{\overline{V_{DC}}}{2}-{\mathrm{<figure-callout\; id="2"\; label="v\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_C$

$v_{CM}=R\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$

Compensation of DC link voltage fluctuations Compensation of a voltage drop at filter and mains impedance Compensation of residual voltage, potential difference, and/or operational/system earthing

According to the embodiment, ν _DC can be measured. According to further embodiments, ν _CCM (for low-frequency components: V _CCM = ν _DC-PE ) can be measured. Alternatively, it would also be conceivable that ν _CCM is determined on the basis of the measured voltage of ν _CX and ν _C2 . In one or more of the methods discussed, it would be conceivable that phase current measurement i(t) of the mains current or the inductances L _D1 is carried out as input. For the measurements, the circuit according to embodiments has a measuring unit which is designed to determine or measure the corresponding voltage (see table or phase) and to pass it on to the calculation unit as an input variable.

It should be noted at this point that the concept described above is designed for different network types, such as TN-CS or TN-S. The concept for common mode voltage suppression can also be used in different modes. According to one embodiment, the currents in one or more phases are symmetrical. One example of this is three-phase operation of the converter circuit. According to other embodiments, the currents in one or more phases can also be asymmetrical. One example of this would be single-phase operation of the converter circuit. Depending on the current operating mode, the calculation method of ν _CM can vary. In the symmetrical, for example three-phase case, one of the calculations for ν _CM explained above is used, e.g. according to method 1.

mit $$\begin{array}{c}{v}_{LD1CM}=\frac{1}{3}(R_{LD1}\cdot \left(i_{LD\mathrm{1,}L1}+i_{LD\mathrm{1,}L2}+i_{LD\mathrm{1,}L3}\right)+L_{LD1}\\ \cdot \left(\frac{d}{dt}{i}_{LD\mathrm{1,}L1}+\frac{d}{dt}{i}_{LD\mathrm{1,}L2}+\frac{d}{dt}{i}_{LD\mathrm{1,}L3}\right))\end{array}$$

$$\begin{array}{c}{v}_{LD2CM}=\frac{1}{3}(R_{LD2}\cdot \left(i_{LD\mathrm{2,}L1}+i_{LD\mathrm{2,}L2}+i_{LD\mathrm{2,}L3}\right)+L_{LD2}\\ \cdot \left(\frac{d}{dt}{i}_{LD\mathrm{2,}L1}+\frac{d}{dt}{i}_{LD\mathrm{2,}L2}+\frac{d}{dt}{i}_{LD\mathrm{2,}L3}\right))\end{array}$$

$$v_{GCM}=\frac{1}{3}\left(R_G\cdot \left(i_{L1}+i_{L2}+i_{L3}\right)+L_G\cdot \left(\frac{d}{dt}{i}_{L1}+\frac{d}{dt}{i}_{L2}+\frac{d}{dt}{i}_{L3}\right)\right)$$

In an asymmetrical case, such as an unbalanced load, the common mode voltage of the filter elements L _D1 , L _D2 and the network impedance must be compensated in addition to the fluctuation of the intermediate circuit voltage. The following formula can be used for this (combination of calculation methods 1 and 4 from Table 1): $$v_{CM,B6}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

with $$\begin{array}{c}{v}_{LD1CM}=\frac{1}{3}({\mathrm{<figure-callout\; id="1"\; label="R\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">R</figure-callout>}}_{LD}\cdot \left(i_{\mathrm{<figure-callout\; id="1"\; label="L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}D\mathrm{1,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}+{\mathrm{<figure-callout\; id="1"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}+{\mathrm{<figure-callout\; id="1"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}\right)+{\mathrm{<figure-callout\; id="1"\; label="L\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}}_{LD}\\ \cdot \left(\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{1,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}+\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{1,}\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}2}+\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{1,}L3}\right))\end{array}$$

$$\begin{array}{c}{v}_{LD2CM}=\frac{1}{3}({\mathrm{<figure-callout\; id="2"\; label="R\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">R</figure-callout>}}_{LD}\cdot \left(i_{\mathrm{<figure-callout\; id="2"\; label="L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}D\mathrm{2,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}+{\mathrm{<figure-callout\; id="2"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}+{\mathrm{<figure-callout\; id="2"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}\right)+{\mathrm{<figure-callout\; id="2"\; label="L\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}}_{LD}\\ \cdot \left(\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{2,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}+\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{2,}\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}2}+\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{2,}L3}\right))\end{array}$$

$$v_{GCM}=\frac{1}{3}\left(R_G\cdot \left(i_{L1}+{\mathrm{<figure-callout\; id="2"\; label="i\; L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">i</figure-callout>}}_L+i_{L3}\right)+L_G\cdot \left(\frac{d}{dt}{i}_{L1}+\frac{d}{dt}{i}_{L2}+\frac{d}{dt}{i}_{L3}\right)\right)$$

bzw. allgemein (für drei Phasen) $$v_{B6}=v_{AC}+v_{CM,B6}$$

bzw. allgemein $$v_M=v_{AC}+v_{CM}$$

At this point, it should be noted that according to embodiments, the modulation voltage at the phase connections is calculated from the mains voltage or mains voltage measurement ν _L1 , ν _L2 , ν _L3 and the common mode voltage ν _{CM, B6} as follows: $$\begin{array}{l}{v}_{B\mathrm{6,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}={\mathrm{<figure-callout\; id="1"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\\ v_{B\mathrm{6,}\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}2}={\mathrm{<figure-callout\; id="2"\; label="v\; L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\\ v_{B\mathrm{6,}\mathrm{<figure-callout\; id="3"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0100.png"\; state="\{\{state\}\}">L</figure-callout>}3}={\mathrm{<figure-callout\; id="3"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0100.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\end{array}$$

or general (for three phases) $$v_{B6}=v_{AC}+v_{CM,B6}$$

or generally $$v_M=v_{AC}+v_{CM}$$

This relationship between the modulation voltage and the common mode voltage is to be applied in such a way that the individual calculation methods, e.g. 1 + 4 or 1 + 2/3, can be calculated using these formulas. The exact application is explained in the figure description.

This applies to the symmetrical as well as the asymmetrical case.

mit $$\begin{array}{c}{v}_{LD1CM}=R_{LD1}\cdot i_{LD\mathrm{1,}N}+L_{LD1}\frac{d}{dt}{i}_{LD\mathrm{1,}N}\\ v_{LD2CM}=R_{LD2}\cdot i_{LD\mathrm{2,}N}+L_{LD2}\frac{d}{dt}{i}_{LD\mathrm{2,}N}\\ v_{GC\text{}M}=R_G\cdot i_N+L_G\frac{d}{dt}{i}_N\end{array}$$

According to another variant, the converter circuit is designed for single-phase operation or only for single-phase operation. In this case, the common mode voltage can be calculated as follows (combination of calculation methods 1 and 4 from Table 1): $$v_{CM,\mathrm{<figure-callout\; id="4"\; label="H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">H</figure-callout>}4}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

with $$\begin{array}{c}{v}_{LD1CM}={\mathrm{<figure-callout\; id="1"\; label="R\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">R</figure-callout>}}_{LD}\cdot {\mathrm{<figure-callout\; id="1"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}+L_{LD1}\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{1,}N}\\ v_{LD2CM}={\mathrm{<figure-callout\; id="2"\; label="R\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">R</figure-callout>}}_{LD}\cdot {\mathrm{<figure-callout\; id="2"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}+L_{LD2}\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{2,}N}\\ v_{GCM}=R_G\cdot i_N+L_G\frac{d}{dt}{i}_N\end{array}$$

für den einphasigen Fall definiert ist.At this point it should be noted that the modulation voltage ν _H4,L1 and ν _{H4,N are} calculated from the mains voltage or mains voltage measurement ν _L1 and the common mode voltage ν _CM,H4 by the formulas: $$\begin{array}{c}{\mathrm{<figure-callout\; id="4"\; label="v\; H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_H={\mathrm{<figure-callout\; id="1"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,H4}\\ {\mathrm{<figure-callout\; id="4"\; label="v\; H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_H=v_{CM,\mathrm{<figure-callout\; id="4"\; label="H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">H</figure-callout>}4}\end{array}$$

is defined for the single-phase case.

With regard to the above formulas, it should be noted that L defines the inductance, R the resistance, i the associated current and v the associated voltage. The index marks the position in the circuit, with 1 representing the inductances or resistances between the center tap of the converter circuit and an optional filter, 2 the inductances or resistances between the optional filter and the phase connection, and G the inductances or resistances on the mains side. With reference to the indices, it should be noted that the indices for 1 and 2 together create an LCL filter/sine filter. The concept can also be applied to other filter structures.

According to embodiments, a capacitance (one capacitance per phase connection) or generally a capacitance arrangement can be provided at the phase connections. According to further embodiments, an intermediate circuit or a split intermediate circuit can be provided on the DC voltage side. The intermediate circuit or the split intermediate circuit is arranged, for example, between two potential taps of the DC voltage connection. According to embodiments, a center point of the intermediate circuit or the symmetrical intermediate circuit can be connected to one phase via a capacitance or to several phases via a capacitance arrangement.

As already mentioned at the beginning, the circuit can be used as part of a rectifier or a non-isolated rectifier or a battery charger. According to one embodiment, the rectifier, such as a non-isolated rectifier or a rectifier of a battery charger, is connected to a TN-C, TN-C-S or TN-S network for operation.

berechnet wird oder wobei die Common-Mode-Spannung ν_CM auf Basis einer Formel, die den Term $\frac{\overline{V_{DC}}-v_{DC}}{2}$

enthält, berechnet wird, wobei ν_DC die Spannung zwischen zwei Potenzialabgriffen (20a, 20b) des Gleichspannungsanschlusses darstellt; und/oder wobei die Common-Mode-Spannung $v_{CM}^{*}$

auf Basis der Formel $$v_{CM}^{*}=v_{DC-PE}-\frac{\overline{V_{DC}}}{2}$$

berechnet wird, wobei ν_DC die Spannung zwischen zwei Potenzialabgriffen (20a, 20b) des Gleichspannungsanschlusses darstellt; und/oder
wobei die Common-Mode-Spannung $v_{CM}^{*}$

auf Basis der Formel $$v_{CM}^{*}=-v_{CX}+\frac{\overline{V_{DC}}}{2}-v_{C2}$$

berechnet wird, wobei ν_DC die Spannung zwischen zwei Potenzialabgriffen (20a, 20b) des Gleichspannungsanschlusses darstellt; und/oder
wobei die Common-Mode-Spannung ν_CM auf Basis der Formel $$v_{CM}=R\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$$

berechnet wird.A further embodiment provides a corresponding method with the step of modulating a voltage at one of the two potential taps and/or at one of the phase connections based on a common mode voltage, wherein the common mode voltage V _CM is based on the formula $$v_{CM}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}$$

or where the common mode voltage ν _CM is calculated based on a formula that contains the term $\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}$

is calculated, where ν _DC represents the voltage between two potential taps (20a, 20b) of the DC voltage connection; and/or where the common mode voltage $v_{CM}^{*}$

based on the formula $$v_{CM}^{*}=v_{DC-PE}-\frac{\overline{V_{DC}}}{2}$$

is calculated, where ν _DC represents the voltage between two potential taps (20a, 20b) of the DC voltage connection; and/or
where the common mode voltage $v_{CM}^{*}$

based on the formula $$v_{CM}^{*}=-v_{CX}+\frac{\overline{V_{DC}}}{2}-{\mathrm{<figure-callout\; id="2"\; label="v\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_C$$

is calculated, where ν _DC represents the voltage between two potential taps (20a, 20b) of the DC voltage connection; and/or
where the common mode voltage ν _CM is based on the formula $$v_{CM}=R\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$$

is calculated.

According to embodiments, the method can be computer-implemented.

erreicht werden, da diese für alle Netzformen geeignet ist. Die Schaltung umfasst eine Stromrichterschaltung, die einen ersten Spannungsanschluss mit zwei Potenzialabgriffen und ein oder mehreren Phasenanschlüssen aufweist. Die Steuerung ist ausgebildet, die schaltbaren Elemente der Stromrichterschaltung so zu steuern, dass eine Spannung an einem der zwei Potenzial abgriffe und/oder an einem der Phasenanschlüsse basierend auf einer Common-Mode-Spannung moduliert wird. Ferner umfasst die Schaltung eine Messeinheit, die ausgebildet ist, um eine Spannung zwischen einem der Potenzialabgriffe und dem lokalen Erdpotential PE (z.B. Schutzleiteranschluss des Geräts) zu bestimmen. Diese Messung kann eine auftretende Verlagerungsspannung oder Potentialdifferenz zwischen Netz- und Anlagenerder erfassen. Die Common-Mode-Spannung wird unter Verwendung der durch die Messeinheit gemessenen Spannung ermittelt.All the above-described embodiments are optimized for common mode compensation in TN-C, TN-S or TN-CS systems. Common mode voltage suppression in TT systems can be achieved according to further embodiments using the variant with the formula $v_{CM}^{*}=v_{DC-PE}-\frac{\overline{V_{DC}}}{2}$

can be achieved because it is suitable for all network types. The circuit comprises a converter circuit which has a first voltage connection with two potential taps and one or more phase connections. The controller is designed to control the switchable elements of the converter circuit such that a voltage at one of the two potential taps and/or at one of the phase connections is modulated based on a common mode voltage. Furthermore, the circuit comprises a measuring unit which is designed to determine a voltage between one of the potential taps and the local earth potential PE (e.g. protective conductor connection of the device). This measurement can detect an occurring displacement voltage or potential difference between the network and system earth. The common mode voltage is determined using the voltage measured by the measuring unit.

A further embodiment provides a rectifier, non-isolated rectifier or battery charger with a circuit as described. The rectifier is preferably designed for operation on a TT system, but can also be operated on another network system, such as TN-C or TN-C-S or TN-S system, according to further embodiments.

A further embodiment provides a method for operating a corresponding circuit with the step of modulating a voltage at one of the two potential taps and/or at one of the phase connections based on a common mode voltage, wherein the common mode voltage is determined using a voltage measured by a measuring unit. In this respect, the method can also comprise the step of measuring a voltage between one of the two potential taps and a protective conductor/PE (with the special feature that this protective conductor in the TT system is connected to the system earthing instead of to the earthing of the network/transformer).

According to further embodiments, the method can be computer-implemented. In this respect, a computer program is created for carrying out the method.

According to a further aspect, a voltage measurement can also be carried out to determine the common mode voltage. Preferably, at least one voltage on the DC voltage side is determined in relation to PE. An example of this would be the voltage of a midpoint of an intermediate circuit that is arranged between the potential taps in relation to PE. This can be determined, for example, by measuring the midpoint of the intermediate circuit in relation to one of the potential taps. An additional voltage measurement between a phase on the AC voltage side and the midpoint can also be taken into account here.

In this respect, further embodiments provide a circuit with a converter circuit that has a DC voltage connection with two potential taps and one or more phase connections; and a controller, wherein the controller is designed to control switchable elements of the converter circuit such that a voltage at one of the two potential taps and/or at one of the phase connections is modulated based on a common mode voltage; measuring unit designed to determine a voltage on the DC voltage side with respect to ground; wherein the common mode voltage is determined using the voltage measured by the measuring unit.

According to embodiments, the voltage between a center point of an intermediate circuit arranged between the two potential taps and one of the potential taps can be measured. Furthermore, for example, the voltage between a center point of an intermediate circuit arranged between the two potential taps and one of the potential taps can be measured, wherein an additional voltage on the AC voltage side is measured between one of the phases and the center point of the intermediate circuit or wherein the additional voltage is measured between one of the phases and ground.

Another embodiment relates to a rectifier, such as a non-isolated rectifier or specifically to a battery charger with a circuit according to one of the previous Claims with a measuring device. Preferably, this rectifier can be operated in a TT system. A further embodiment provides a method for operating this circuit. The method comprises the step of modulating a voltage at one of the two potential taps and/or at one of the phase connections based on a common mode voltage, wherein the common mode voltage is determined using the voltage measured by the measuring unit on the DC side with respect to earth.

Of course, this procedure can also be computer-implemented.

• 1 ein vereinfachtes Common-Mode-Ersatzschaltbild inklusive Struktur eines EMV-Filters (gemäß [1]);
• 2 ein vereinfachtes Blockschaltbild eines V2-PFC mit zusätzlicher aktivierter Zwischenkreissymmetrierung (BC) (gemäß [3]);
• 3 eine schematische Tabelle zur Illustration von verschiedenen Berechnungsmethoden der Common-Mode-Spannung zur Verwendung in Ausführungsbeispielen; Auflistung von Messgrößen, Dynamik und Nachteilen
• 4a/b/c unterschiedliche Netzformen;
• 5a/b zeigt schematische Darstellungen für den einphasigen und dreiphasigen Fall, der Common-Mode-Spannungskompensation gemäß Ausführungsbeispielen;
• 5c ein schematisches Blockschaltbild einer elektrischen Schaltung mit Common-Mode-Spannungsreduzierung für den einphasigen Betrieb gemäß einem erweiterten Ausführungsbeispiel;
• 6 ein schematisches Blockschaltbild einer Schaltung mit Common-Mode-Spannungsreduzierung für den dreiphasigen Betrieb gemäß einem erweiterten Ausführungsbeispiel;
• 7a/b/c schematische Blockschaltbilder einer elektrischen Schaltung mit Common-Mode-Spannungsreduzierung mittels Spannungsmessung gemäß einem weiteren Ausführungsbeispiel;
• 8a/b schematische Blockschaltbilder Darstellung der Berechnung der Modulationsspannung aus der Netzspannung und der Common Mode Spannung; und
• 9a-d Simulationsergebnisse zu Ausführungsbeispielen.

Embodiments of the present invention are explained below with reference to the accompanying drawings. They show:

• 1 a simplified common-mode equivalent circuit including the structure of an EMC filter (according to [1]);
• 2 a simplified block diagram of a V2-PFC with additional activated DC link balancing (BC) (according to [3]);
• 3 a schematic table to illustrate various calculation methods of the common mode voltage for use in embodiments; listing of measured variables, dynamics and disadvantages
• 4a /b/c different network shapes;
• 5a /b shows schematic representations for the single-phase and three-phase case of the common-mode voltage compensation according to embodiments;
• 5c a schematic block diagram of an electrical circuit with common-mode voltage reduction for single-phase operation according to an extended embodiment;
• 6 a schematic block diagram of a circuit with common mode voltage reduction for three-phase operation according to an extended embodiment;
• 7a /b/c schematic block diagrams of an electrical circuit with common-mode voltage reduction by means of voltage measurement according to a further embodiment;
• 8a /b schematic block diagrams showing the calculation of the modulation voltage from the mains voltage and the common mode voltage; and
• 9a -d Simulation results for implementation examples.

Before exemplary embodiments of the present invention are explained below with reference to the accompanying drawings, it should be noted that elements and structures with the same effect are provided with the same reference numerals, so that the description of them is applicable to one another or interchangeable.

Before the following embodiments of the present invention are explained, the problem is briefly explained by different network forms, as they are used in 4a , 4b and 4c as well as 6 presented, before then in connection with 5c a corresponding control concept is explained.

4a shows the connection of a consumer 150 to a TN-CS system. As can be seen, the TN-CS system on the system side comprises the three phases L ₁ , L ₂ and L ₃ as well as the neutral conductor and PE conductor. At the transition to the network 152, PE and N are combined to form a PEN. The star point of the three phases and PEN is connected to the operational earthing electrode 153. An earthing electrode 154 is also provided on the system side.

This in 4b The TN-S system shown is extended in that the PE conductor is led directly to the power grid 152'. The star point consisting of L ₁ , L ₂ , L ₃ , N and PE is connected to the operational earth 153. No system earth is provided on the consumer 150 side. A potential difference can occur between the earth (depending on whether it is the system earth or operational earth) and one of the potential taps of a converter circuit. If one assumes that a capacitance/parasitic capacitance of any kind arises between the potential tap on the one side and earth on the other side, a current flow can result due to the potential difference or in particular fluctuating potential difference. These currents are called leakage currents. The capacitor is shown in the figure below. In the examples given, it is referred to as C _CM and can be present on both the negative intermediate circuit potential side DC- and the positive intermediate circuit potential side DC+. An example of this would be a non-isolated charger for electric cars, where the capacitance C _CM is represented by Y capacitors in the battery or in the vehicle.

In the 4c In the TT network shown, the connection between the operational and system earthing is made via the ground. Furthermore, potential differences can arise between the operational earthing and system earthing due to the spreading resistance between the earthing electrodes. In all network types, displacement voltage can also occur as a result of earth faults or unbalanced loads in the network. This leads to a fluctuating potential difference between the DC-side potential tap and PE and thus to leakage currents. Leakage currents or unbalanced loads from other devices in the same network section can increase the potential fluctuation.

Below we explain a concept on how to optimally reduce the leakage current.

5c shows an electrical circuit 10 comprising a converter circuit 12 with, for example, two half-bridges 12a and 12b. The two half-bridges 12a and 12b are provided between the potential taps 20a and 20b. Each half-bridge comprises, for example, two switchable elements, which are provided with the reference number 14. The two switchable elements 14 are connected in series, with a respective center node 16 being connected to the phases 18a and 18b with a phase connection 18.

In addition to the converter circuit 12 with the potential taps 20a and 20b, a capacitor C _CM with the voltage ν _DC-PE is also shown as an example to illustrate the common mode fluctuation on the common mode side 20a + 20b, as well as an example control 25 for controlling the switchable elements. Now that the structure has been explained, the functionality will be explained.

The converter circuit 12 can, for example, be a rectifier which, based on a voltage applied to the voltage connection 18, here an alternating voltage connection, provides a direct voltage ν _DC between the direct voltage connections 20a and 20b or generally the potential taps 20a and 20b. For this purpose, the switchable elements 14 are controlled accordingly, namely by the controller 25. The controlled variable is ν _DC , i.e. the controller 25 controls the specific sequence and control times of the switchable elements 14 such that a corresponding value ν _DC is achieved. According to embodiments, this value ν _DC can of course also be measured. In this case, the output voltage ν _DC between 20a and 20b can fluctuate, which results in a common mode voltage component ν _CM . The intermediate circuit or generally the voltage potential of 20a and 20b can be shifted relative to the earth potential by a corresponding modulation of the elements 14 (change in the voltage ν _DC-PE ). This voltage shift drops across C _CM . As a result of the fluctuation, a corresponding current flow occurs through C _CM (leakage current).

bestimmt.By clever modulation in the control process, the voltage ν _DC-PE or ν _CCM can be kept constant or as constant as possible in order to avoid leakage currents via the capacitor C _CM . For this purpose, a control process is used according to which the voltage ν _H4 of the switchable elements of the converter circuit (voltage ν _H4 is defined as a voltage averaged over a switching period, applied to the semiconductors or resulting from the modulation of the PWM (cf. 5a) voltage) is modulated with the common mode voltage ν _CM . In order to keep the voltage ν _CCM constant at the capacitor C _CM , the voltage between potential taps 20a and 20b and PE is shifted by half a fluctuation of the intermediate circuit voltage ν _DC (deviating from the desired mean value). Consequently, ν _CM is calculated using the formula $$v_{CM}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}$$

certainly.

stellt die Differenz zum Mittelwert der jeweiligen Spannung dar. Die Zwischenkreisspannung ν_DC ist deshalb prädestiniert, da dieser Wert in der Regel die geregelte Größe ist. Insofern kann für $\overline{V_{DC}}$

statt der Mittelwertbildung aus den Messwerten auch der Sollwert aus der Regelung verwendet werden. ν_DC ist eingezeichnet als Spannung zwischen dem Potenzialabgriff 20a und dem Potenzialabgriff 20b.The difference in the formula with e.g. $\overline{V_{DC}}-v_{DC}$

represents the difference to the mean value of the respective voltage. The intermediate circuit voltage ν _DC is therefore predestined, since this value is usually the controlled variable. In this respect, $\overline{V_{DC}}$

Instead of averaging the measured values, the target value is also calculated from the control. ν _DC is shown as the voltage between the potential tap 20a and the potential tap 20b.

Using the control method just explained, the common mode modulation of the converter circuit 12, here an H4 bridge in single-phase operation or also in other converter circuits, such as a B6 bridge in three-phase operation, can greatly reduce the fluctuation in the voltage ν _CCM and thus also reduce the leakage currents through C _CM by compensating for the fluctuation resulting from the fluctuation in the intermediate circuit voltage ν _DC . By taking this formula into account during modulation, ν _CCM is advantageously kept constant.

$$

typischerweise eine Differenz zum Mittelwert der jeweiligen Spannung darstellen. Da in der Regel dieser Wert eine geregelte Größe ist (z. B. die (messbare/gemessene) Zwischenkreisspannung ν_DC), kann für $\overline{V_{DC}}$

statt der Mittelwertbildung aus dem Messwert auch der Sollwert aus der Regelung verwendet werden. Insofern stellt entsprechend Ausführungsbeispielen $\overline{V_{DC}}$

den Regelwert, wie z. B. den Sollwert auf DC-Seite oder den Mittelwert auf DC-Seite, dar.At this point it should be noted that differences in the formulas with e.g. $\overline{V_{DC}}-v_{DC}$

$$

typically represent a difference to the mean value of the respective voltage. Since this value is usually a controlled value (e.g. the (measurable/measured) intermediate circuit voltage ν _DC ), $\overline{V_{DC}}$

Instead of averaging the measured value, the setpoint from the control system can also be used. In this respect, according to the examples $\overline{V_{DC}}$

the control value, such as the setpoint on the DC side or the mean value on the DC side.

dargestellt. Ausgehend von oben erläuterten Störeffekten, kann es zwischen einem der Gleichspannungsanschlüsse, hier DC-, der Gleichspannungsseite und PE zu einer Common-Mode-Spannung ν_CCM über die Kapazität C_CM kommen, welche mittels der modulierten Spannungsquelle $v=\frac{v_{DC}}{2}+v_{CM}$

an die Common-Mode-Spannung ν_CCM an dem Kondensator C_CM kompensiert werden. 5a shows an equivalent circuit diagram for the single-phase case. The single-phase voltage connection is provided with the reference number 18. The modulated voltage of the semiconductors is separated into push-pull component V _L and floating-mode component (common mode) $v=\frac{{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{CM}$

Based on the interference effects explained above, a common mode voltage ν _CCM can occur between one of the DC voltage connections, here DC, the DC voltage side and PE, via the capacitance C _CM , which can be modulated by means of the voltage source $v=\frac{{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{CM}$

to the common mode voltage ν _CCM on the capacitor C _CM .

dargestellt. Auch hier können unsymmetrische Ströme i oder Netzspannungen 18' in den einzelnen Phasen L1, L2 und L3 zu unsymmetrischen Spannungsabfällen V_ZL an z.B. den Filterkomponenten führen, so dass auf Gleichspannungsseite ν_DC eine Common-Mode-Spannung ν_CCM gegenüber PE abfällt. Eine Verlagerungsspannung oder Ableitströme können zu einem Spannungsabfall V_ZPE an der Impedanz zwischen lokaler Erdung und dem Betriebserder führen, welcher sich zur Common-Mode-Spannung ν_CCM addiert. Diese Common-Mode-Spannungen können über die Spannungsquelle $v=\frac{v_{DC}}{2}+v_{CM}$

mittels Aufschaltung der Common-Mode-Spannung ν_CM kompensiert werden.In 5b the same situation is shown starting from a three-phase voltage source 18'. The modulated voltage of the semiconductors is again separated into push-pull component V _L and floating-mode component (common mode) $v=\frac{{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{CM}$

shown. Here too, asymmetrical currents i or mains voltages 18' in the individual phases L1, L2 and L3 can lead to asymmetrical voltage drops V _ZL on, for example, the filter components, so that on the direct voltage side ν _DC a common mode voltage ν _CCM drops compared to PE. A displacement voltage or leakage currents can lead to a voltage drop V _ZPE at the impedance between the local earthing and the operational earthing, which is added to the common mode voltage ν _CCM . These common mode voltages can be fed via the voltage source $v=\frac{{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{CM}$

by applying the common mode voltage ν _CM .

The following refers to 6 an extended embodiment is explained.

6 shows a converter circuit 12' with three half-bridges 12a', 12b' and 12c', each of which is arranged between two potential taps 20a and 20b. Each of these three half-bridges 12a', 12b' and 12c' is connected to one of the phases via a respective center node 16. The phases are provided with the reference symbols 18a', 18b' and 18c'.

In addition, the converter circuit can also have an additional intermediate circuit 22, here a symmetrical intermediate circuit with two intermediate circuit capacitances 22C1 and 22C2. According to embodiments, one or all of the phases 18a', 18b' and 18c' are capacitively coupled via a center node between the two capacitances 22C1 and 22C2, which is provided with the reference symbol 22m. For this purpose, a capacitance arrangement 24 with three capacitances is provided between the phases 18a', 18b' and 18c'.

Each of the phase connections has one or more inductances and resistors L _D1 , R _D1 , L _D2 , R _D2 , L _G and R _G drawn here. It should be noted at this point that R _D1 , R _D2 are not shown in the figures, whereby R _D1 , R _D2 are the resistors or the ohmic part of the respective inductances L _D1 and L _D2 . Regarding L _G and R _G it should be noted that the inductance L _G or the resistor R _G is not drawn in the attached drawings and is only mentioned for the sake of completeness. This is the network impedance (network inductance and network resistance) on the side of the voltage source V _G .

The elements L _D1 , L _D2 , R _D1 and R _D2 are arranged on the side of the converter circuit, i.e. in the charger (see reference symbol L), while the elements L _G and R _G (not shown) are arranged on the side of the AC voltage connection N. A separation between the charger side L and the mains side N is shown by means of a dashed line. The inductance L _G and the resistor R _G (marked G) are each on the mains side. The inductance L _D1 and the resistor R _D1 represent the inductances connected in series and their ohmic resistances between the capacitance arrangement 24 and the respective center point 16, while the inductance L _D2 and the resistor R ₂ are arranged between the capacitance arrangement 24 and the mains connection. As a result, the elements L _D1 , R _D1 , L _D2 , R _D2 , L _G and R _G are arranged in series, ie connected in series, for each phase connection 18a', 18b' and 18c'. It should also be noted that the inductances and resistors do not necessarily have to be explicitly provided electrical components, but can also be formed by the line itself.

Now that the structure has been explained in detail, we will look at how it works.

By connecting the capacitors C _X to the intermediate circuit center 22m, the high-frequency components of the common mode interference voltage ν _CM are already greatly reduced via L _D1 and C _X , but this is not absolutely necessary for the control method to work. The inductances L _D1 , L _D2 , L _G and the resistors R _D1 , R _D2 , R _G were assumed to be the same for the illustration. However, the method also works with different values for these elements.

The output voltage of the B6 bridge 12' can be modulated with a common mode voltage ν _{CM, B6} . The intermediate circuit or the potential taps 20a' and 20b' can thereby be shifted relative to the earth potential PE (change in the voltage ν _DC-PE ).

$$v_{CM,B6}=\frac{\overline{V_{DC}}-v_{DC}}{2}$$

The aim of the control method is to keep the voltage ν _CCM constant in order to avoid leakage currents via the capacitor C _CM . This is achieved by modulating the output voltage of the three phases ν _B6 (1) with the common mode voltage ν _{CM, B6} (2). In this case, the intermediate circuit is shifted relative to ground potential by half the fluctuation of the intermediate circuit voltage (deviating from the desired mean value) and thus ν _CCM is kept constant. $$\begin{array}{l}{v}_{B\mathrm{6,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}={\mathrm{<figure-callout\; id="1"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\\ v_{B\mathrm{6,}\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}2}={\mathrm{<figure-callout\; id="2"\; label="v\; L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\\ v_{B\mathrm{6,}\mathrm{<figure-callout\; id="3"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0100.png"\; state="\{\{state\}\}">L</figure-callout>}3}={\mathrm{<figure-callout\; id="3"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0100.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\end{array}$$

$$v_{CM,B6}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}$$

$$\begin{array}{c}{v}_{LD1CM}=\frac{1}{3}(R_{LD1}\cdot \left(i_{LD\mathrm{1,}L1}+i_{LD\mathrm{1,}L2}+i_{LD\mathrm{1,}L3}\right)+L_{LD1}\\ \cdot \left(\frac{d}{dt}{i}_{LD\mathrm{1,}L1}+\frac{d}{dt}{i}_{LD\mathrm{1,}L2}+\frac{d}{dt}{i}_{LD\mathrm{1,}L3}\right))\end{array}$$

$$\begin{array}{c}{v}_{LD2CM}=\frac{1}{3}(R_{LD2}\cdot \left(i_{LD\mathrm{2,}L1}+i_{LD\mathrm{2,}L2}+i_{LD\mathrm{2,}L3}\right)+L_{LD2}\\ \cdot \left(\frac{d}{dt}{i}_{LD\mathrm{2,}L1}+\frac{d}{dt}{i}_{LD\mathrm{2,}L2}+\frac{d}{dt}{i}_{LD\mathrm{2,}L3}\right))\end{array}$$

$$v_{GCM}=\frac{1}{3}\left(R_G\cdot \left(i_{L1}+i_{L2}+i_{L3}\right)+L_G\cdot \left(\frac{d}{dt}{i}_{L1}+\frac{d}{dt}{i}_{L2}+\frac{d}{dt}{i}_{L3}\right)\right)$$

$$v_{CM,B6}=\frac{\overline{V_{DC}}-v_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

The relationship shown in formulas (1) and (2) can, as shown in the table above, compensate for the common mode voltage resulting from the fluctuation in the intermediate circuit voltage (and a voltage drop across the filter components + possibly line impedance). Asymmetrical mains currents also lead to a common mode voltage at C _CM due to deviating voltages across the elements L _D1 , L _D2 and L _G . This can be calculated using the relationship shown in formulas (3) to (7). The common mode voltages ν _LD1CM and ν _LD2CM across the chokes and resistors of the rectifier and ν _GCM across the impedance of the mains connection can be determined using formulas (4), (5) and (6). In this case, an LCL filter structure was assumed (L _D1 -C _X -L _D2 ). Other components in the current path of the rectifier must be taken into account accordingly. $$\begin{array}{l}{v}_{B\mathrm{6,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}={\mathrm{<figure-callout\; id="1"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\\ v_{B\mathrm{6,}\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}2}={\mathrm{<figure-callout\; id="2"\; label="v\; L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\\ v_{B\mathrm{6,}\mathrm{<figure-callout\; id="3"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0100.png"\; state="\{\{state\}\}">L</figure-callout>}3}={\mathrm{<figure-callout\; id="3"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0100.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\end{array}$$

$$\begin{array}{c}{v}_{LD1CM}=\frac{1}{3}({\mathrm{<figure-callout\; id="1"\; label="R\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">R</figure-callout>}}_{LD}\cdot \left(i_{\mathrm{<figure-callout\; id="1"\; label="L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}D\mathrm{1,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}+{\mathrm{<figure-callout\; id="1"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}+{\mathrm{<figure-callout\; id="1"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}\right)+{\mathrm{<figure-callout\; id="1"\; label="L\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}}_{LD}\\ \cdot \left(\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{1,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}+\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{1,}\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}2}+\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{1,}L3}\right))\end{array}$$

$$\begin{array}{c}{v}_{LD2CM}=\frac{1}{3}({\mathrm{<figure-callout\; id="2"\; label="R\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">R</figure-callout>}}_{LD}\cdot \left(i_{\mathrm{<figure-callout\; id="2"\; label="L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}D\mathrm{2,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}+{\mathrm{<figure-callout\; id="2"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}+{\mathrm{<figure-callout\; id="2"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}\right)+{\mathrm{<figure-callout\; id="2"\; label="L\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}}_{LD}\\ \cdot \left(\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{2,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}+\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{2,}\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}2}+\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{2,}L3}\right))\end{array}$$

$$v_{GCM}=\frac{1}{3}\left(R_G\cdot \left(i_{L1}+{\mathrm{<figure-callout\; id="2"\; label="i\; L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">i</figure-callout>}}_L+i_{L3}\right)+L_G\cdot \left(\frac{d}{dt}{i}_{L1}+\frac{d}{dt}{i}_{L2}+\frac{d}{dt}{i}_{L3}\right)\right)$$

$$v_{CM,B6}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

In the above formulas, especially formula 6, R _G and L _G are still listed for the sake of completeness. It is not absolutely necessary to take the network impedance into account, as this is usually unknown. In this respect, the calculation can also be carried out without ν _GCM in accordance with the exemplary embodiments.

The above descriptions using the formulas have shown that it is possible to compensate for the voltage drop across the filter components and, if necessary, also across the line impedance. The discussion is prepared especially for the three-phase case, but can be applied analogously to the single-phase case.

In general, it can be stated that the above explanations in connection with the single-phase case are of course transferable to the three-phase case or vice versa.

Regarding the formulas, it should be noted that the position of L _D1 , R _D1 , L _D2 , R _D2 , L _G , R _G has already been explained in detail. Regarding i _LD1,L1 , i _LD1,l2 , i _{LD1, L3} , i _L1 , i _L2 , i _{L3 ,} it should be noted that these represent the corresponding currents in the phases 18a'(R), 18b'(R) and 18c'(R).

The variables ν _CM , ν _B6 and ν _{CM, B6} have already been introduced. The same applies to the variable ν _DC .

$$v_{H\mathrm{4,}N}=v_{CM,H4}$$

In single-phase operation, the phase L1 is connected to the first half-bridge and the neutral conductor N is connected to the second half-bridge. The first half-bridge L1 is controlled with the mains voltage v _L1 (in practice with the output voltage setpoint of the current regulator) and the common mode voltage ν _{CM, H4} (8). The second half-bridge N is controlled with the common mode voltage ν _{CM, H4} (9). $${\mathrm{<figure-callout\; id="4"\; label="v\; H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_H={\mathrm{<figure-callout\; id="1"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,\mathrm{<figure-callout\; id="4"\; label="H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">H</figure-callout>}4}$$

$${\mathrm{<figure-callout\; id="4"\; label="v\; H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_H=v_{CM,\mathrm{<figure-callout\; id="4"\; label="H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">H</figure-callout>}4}$$

$$v_{LD2CM}=R_{LD2}\cdot i_{LD\mathrm{2,}N}+L_{LD2}\frac{d}{dt}{i}_{LD\mathrm{2,}N}$$

$$v_{GCM}=R_G\cdot i_N+L_G\frac{d}{dt}{i}_N$$

$$v_{CM,H4}=\frac{\overline{V_{DC}}-v_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

For single-phase operation, the common mode voltages are calculated according to formulas (10) to (12). The common mode modulation voltage for the H4 bridge is summarized in formula (13). $$v_{LD1CM}={\mathrm{<figure-callout\; id="1"\; label="R\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">R</figure-callout>}}_{LD}\cdot {\mathrm{<figure-callout\; id="1"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}+L_{LD1}\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{1,}N}$$

$$v_{LD2CM}={\mathrm{<figure-callout\; id="2"\; label="R\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">R</figure-callout>}}_{LD}\cdot {\mathrm{<figure-callout\; id="2"\; label="i\; L\; D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">i</figure-callout>}}_{LD}+L_{LD2}\frac{d}{dt}{i}_{L\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">D</figure-callout>}\mathrm{2,}N}$$

$$v_{GCM}=R_G\cdot i_N+L_G\frac{d}{dt}{i}_N$$

$$v_{CM,\mathrm{<figure-callout\; id="4"\; label="H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">H</figure-callout>}4}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

$$v_{CM,H4}=-\frac{\overline{V_{DC}}-v_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

The capacitance C _CM can also be connected to the positive intermediate circuit connection. An additional DCDC converter can also be connected to the intermediate circuit (e.g. for a battery). Depending on the design (DC- or DC+ continuous), the capacitance C _CM of the battery is connected from DC- or from DC+ to earth potential. When compensating for the fluctuation in the intermediate circuit voltage, the fluctuation must then have a negative sign (formulas (14) and (15)). $$v_{CM,B6}=-\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

$$v_{CM,\mathrm{<figure-callout\; id="4"\; label="H"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">H</figure-callout>}4}=-\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

The voltage drop across the semiconductors and the voltage drop across the common mode chokes in the EMC filter can also be taken into account when compensating the common mode voltage, but was not taken into account in the representation and in the formulas due to its smaller influence.

berechnet wird. Diese Berechnungsmethode ermöglicht vorteilhafterweise, dass die aus der Schwankung der Zwischenkreisspannung resultierende Common Mode Spannung kompensiert werden kann. Entsprechend weiteren Ausführungsbeispielen ist diese Kompensation der Schwankung der Common Mode Spannung auch noch mit weiteren Berechnungsmethoden möglich. Eine Übersicht über vier verschiedene Berechnungsmethoden ist in 3 gezeigt.In the above embodiments, the half-bridges are controlled in such a way that the voltage is modulated based on the common mode voltage. In the above embodiments, it was assumed that the common mode voltage is based on a formula with the term $\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}$

This calculation method advantageously allows the common mode voltage resulting from the fluctuation of the intermediate circuit voltage to be compensated. According to further embodiments, this compensation of the fluctuation of the common mode voltage is also possible with other calculation methods. An overview of four different calculation methods is provided in 3 shown.

$$v_{CM}^{*}=v_{DC-PE}-\frac{\overline{V_{DC}}}{2}$$

$$v_{CM}^{*}=-V_{CX}+\frac{\overline{V_{DC}}}{2}-V_{C2}$$

$$v_{CM}=R\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$$

3 shows a table with the four calculation methods for the modulation voltage ν _CM , namely: $$v_{CM}=\frac{\overline{V_{DC}}-{\mathrm{<figure-callout\; id="2"\; label="v\; D\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_{DC}}{2}$$

$$v_{CM}^{*}=v_{DC-PE}-\frac{\overline{V_{DC}}}{2}$$

$$v_{CM}^{*}=-V_{CX}+\frac{\overline{V_{DC}}}{2}-{\mathrm{<figure-callout\; id="2"\; label="V\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">V</figure-callout>}}_C$$

$$v_{CM}=R\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$$

As already mentioned above, these calculation methods can be used individually or in combination. A preferred combination is 1 and 2 or 1 and 4, although of course more than two methods can be combined. In the explanation of the embodiments presented here, a combination, namely 1 + 4, is explained as an example. The advantages of the individual calculation methods are discussed below.

For point 1, please refer to the above explanations. As already mentioned, the common mode voltage resulting from the fluctuation in the intermediate circuit voltage can be compensated in this way. Calculation methods 2 and 3 also make it possible to compensate for fluctuations in the intermediate circuit voltage, whereby both advantageously also allow compensation for the voltage drops at the filter and network impedance. Calculation method 2 also takes into account displacement voltages and potential differences between the operational and system earthing.

Calculation method 4 allows compensation of the voltage drop across the filter and mains impedance.

Depending on the initial situation, one of the four variants can be selected according to the examples. Differences arise on the one hand in the type and extent of the compensation and on the other hand in the use of the measured variables. The measured variable for the For calculation method 1, the intermediate circuit voltage ν _DC or the partial voltages ν _DC = ν _C1 + ν _C2 can be used. For the second calculation method, the voltage measurement ν _CCM with e.g. ν _CCM = ν _DC-PE or ν _CCM = ν _MPE - ν _C2 can serve as the input variable. The third calculation method is based, for example, on a voltage measurement of ν _CX and ν _C2 . For the fourth calculation method, a measurement of the phase currents or the currents in the respective inductances is used.

It should be noted here that the permissible operating currents are determined depending on the device class.

The control method described here shows in simulations a strong reduction in leakage currents compared to conventional control.

Referring to 7a -c another embodiment is now explained which is particularly suitable for the TT system.

7a shows another electrical circuit, here an electrical charger connected to a TN-CS system. In 7b the same charger is connected to a TN-S system. As can be seen here, a separate conductor is used for PE and not the common PEN conductor. In 7c the connection of the same charger is used on a TT system. There is a separate earthing electrode on both the system side and the network side, which, unlike the TN-S and TN-CS systems, does not have a common potential through a separate connection. As a result, displacement voltages or potential differences between the operating and system earthing electrodes can occur.

Before we go into the solution according to this embodiment, we will briefly explain the charger and its components. It should be noted here that not all components are mandatory, but that optional components are also included.

The charger, e.g. from 7a , 7b or 7c comprises an EMC filter 1000 on the input side, which connects the respective power system (cf. voltage source V _G ) with the actual rectifier 1100. The rectifier (here a PVC rectifier with LCL sine filter (differential mode filter)) thus connects the AC voltage side of the network with the DC voltage side 1200. 1200 here designates the DC voltage intermediate circuit, which is arranged between the two potential taps 20a and 20b. The intermediate circuit 12 here comprises two series-connected capacitors with a center point M, over which the filters arranged on the input side (EMC filter and LCL sine filter) are arranged.

On the DC voltage side, an optional (non-isolated) DC-DC converter 1300 and an optional EMC filter 1400 can then follow. The reference symbol 1500 designates a DC source and/or DC sink, such as a battery.

According to the design examples, Y capacitors can optionally be used as common mode filter capacitors in the EMC filter 1400 in the charger (C _Y1 and C _Y2 ). These capacitors are connected to the ground potential on the DC voltage side. Y capacitors in the HV electrical system of a vehicle can have a higher capacitance depending on the design and are optional.

In this embodiment, different voltages can be measured, preferably voltages on the DC side, in order to regulate the common mode voltage.

$$

erfolgen. Dies ist eine Alternative für die Berechnung des Spannungsabfalls an der Induktivität L_D1, wobei keine Ableitung des Stroms nach der Zeit notwendig ist. Dieser Ansatz weist eine geringere Dynamik auf, da der Messwert einen Filter bzw. einen Regler aufweisen muss (TF in 8 (b)). Verlagerungsspannungen und Potenzialdifferenzen zwischen Betriebs- und Anlagenerder und weiteren Filterkomponenten z.B. L_D2 können mit dieser Methode nicht kompensiert werden. Hier wird dann bevorzugter Weise nur auf Gleichspannungsseite gemessen, so dass eine Kompensation durch direkte Messung der Spannung nach PE erfolgt. Hierfür kann zwischen einigen Ausführungsorten unterschieden werden.According to a first embodiment of current measurement, ν _C2 is measured on the DC side, i.e. between the center point M of the intermediate circuit 12 and one of the potential taps 20a and 20b. In many chargers, this measurement is carried out anyway, so it does not represent any additional effort. Alternatively or additionally, ν _CX can also be determined on the AC side. Using these two values, for example, a constant control at a constant value can be achieved. $v_{CM}^{*}=-v_{CX}+\frac{\overline{V_{DC}}}{2}-{\mathrm{<figure-callout\; id="2"\; label="v\; C"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_C$

$$

This is an alternative for calculating the voltage drop across the inductance L _D1 , where no derivative of the current with respect to time is necessary. This approach has a lower dynamic range, since the measured value must have a filter or a regulator (TF in 8 (b) ). Displacement voltages and potential differences between the operating and system earthing and other filter components, e.g. L _D2, cannot be compensated with this method. In this case, measurements are preferably only taken on the direct voltage side, so that compensation is achieved by directly measuring the voltage to PE. A distinction can be made between several design locations for this.

According to a first embodiment, a voltage measurement of ν _MPE and ν _C2 can be carried out. These two voltages can also be determined together as ν _DC-PE = ν _MPE - ν _C2 .

According to another variant, a direct voltage measurement of ν _DC-PE can also be carried out.

The voltage ν _DC-PE = ν _MPE - ν _C2 represents the common mode voltage ν _CCM , so that the common mode fluctuation of ν _CCM can be regulated to zero and the resulting leakage currents can be compensated or reduced. In the second type of measurement, a direct measurement of the common mode voltage ν _CCM = ν _DC-PE is carried out instead of two individual measurements.

According to an alternative variant, a measurement can also be carried out from DC+ to PE or from the battery+ to PE. Based on this, it is also possible to regulate the common mode voltage or common mode voltage fluctuation. In all three variants explained last, the measurement on the DC voltage side advantageously compensates for all elements, in particular the filter components, the intermediate circuit voltage, the network impedance, the displacement voltage, and potential differences between the operational and system earthing.

In summary, it can be said that there are various ways of measuring the voltage to PE (e.g. from DC+, M, DC- to PE). A combination would also be conceivable, or a combination with the measurement of the intermediate circuit voltage ν _C1 and ν _C2 . In general terms, this means that, according to the embodiments, a voltage measurement is carried out on the DC voltage side between the DC voltage side and PE in order to derive a value that allows a conclusion to be drawn about the common mode voltage. Based on the measured value, the common mode voltage is then calculated or the fluctuation in the common mode voltage is calculated so that it can then be compensated by adjusting the control of the converter circuit. With regard to the adaptation, it should be noted that both here and in all other embodiments, the adaptation is carried out in such a way that the common mode voltage or common mode voltage fluctuation calculated or calculated on the basis of measured values can be compensated for by, for example, adjusting the corresponding target value on the DC side accordingly (reducing or increasing by the fluctuation).

The following refers to 8a and 8b The calculation method is explained using an example block diagram. The pulse width modulation to be used to regulate the common mode voltage is discussed explicitly.

8a shows a control system with the three elements 16, 17 and 18. Element 1600 represents the control voltage for the rectifier (e.g. generated by the current controller) and corresponds, for example, to the principle of EN 10 2017 216 468 A1 (Modulation N with 0V and L with the phase voltage) or the control known from the US 11,228,238 B2 (see. US 11,228,238 B2 , 2 , Modulation 120+130 by 110+140+150 so that again the curves as in EN 10 2017 216 468 A1 is formed -> i.e. N=0V L=full phase voltage). Here, the half-bridges in single-phase operation set the voltage 0 V or duty cycle 0.5 for the neutral conductor and the half-bridges for the phase set the full voltage. In three-phase operation, all half-bridges set the full voltage. Based on the two control voltages, the pulse width modulator 1700 can then generate the modulation level and then carry out the pulse width modulation. It should be noted that this can be implemented differently depending on the circuit topology. Block 1800 illustrates the application of the common mode voltage for the control process. The voltage ν _CM is added to all voltages (neutral conductor and phases). The value compensated for by the common mode voltage ν _CM is then transferred to the pulse width modulation, taking into account the intermediate circuit voltage ν _DC .

8b also starts from blocks 1600, 1700, but is extended by block 1900, in which the common mode voltage is regulated according to the above embodiments.

In the 1900 unit, ν* _CM serves as the input signal for the transfer function TF, which outputs the common mode voltage ν _CM . The transfer function TF can be implemented, for example, in the form of a filter or a controller.

According to the embodiments, the modulation voltage at the phase connections is calculated from the mains voltage or mains voltage measurement v _L1 , v _L2 , v _L3 and the common mode voltage ν _CM as follows $$\begin{array}{l}{v}_{B\mathrm{6,}\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">L</figure-callout>}1}={\mathrm{<figure-callout\; id="1"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0099.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\\ v_{B\mathrm{6,}\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">L</figure-callout>}2}={\mathrm{<figure-callout\; id="2"\; label="v\; L"\; filenames="DE102022211478A1\_0089.png,DE102022211478A1\_0091.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\\ v_{B\mathrm{6,}\mathrm{<figure-callout\; id="3"\; label="L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0100.png"\; state="\{\{state\}\}">L</figure-callout>}3}={\mathrm{<figure-callout\; id="3"\; label="v\; L"\; filenames="DE102022211478A1\_0091.png,DE102022211478A1\_0100.png"\; state="\{\{state\}\}">v</figure-callout>}}_L+v_{CM,B6}\end{array}$$

This connection, which can be seen for example in 8a shown, for example, allows the combination of methods 1+4. The following mathematical relationship shows the calculation of the modulation voltage in general. $$v_{m}bzw.v_{B6}=v_{AC}+v_{CM}$$

This general relationship is applicable, for example, to method 1+2 or 1+3 (see overview 8a and 8b) .

In detail: As shown by block 1800, this path can take into account both method 1 and method 4 as well as the combination of methods 1 and 4 as a simple sum of the formulas associated with methods 1 and 4. The sum of the common mode voltage according to methods 1 and 4 is then added to the voltage ν _AC via the summation point of block 16.

In an analogous way, this is 8b possible, which is also made clear here by the arrow 1800, which leads to the sum point of block 1600. In addition, 8b the consideration of the calculations according to method 1 and/or 2. For this purpose, the transfer function TF in block 1900 is used.

In summary, it can be stated that the common mode voltage according to methods 1 and/or 4 can be taken into account by adding the common mode voltage to ν _AC , while alternatively or additively the common mode voltage according to methods 2 and 3 can also be added to the signal ν _AC taking into account a transfer function TF.

With regard to the previous embodiments, the objectives and in particular the efficiency will be discussed below.

In these embodiments, the aim is to provide the voltage ν _CCM with as little fluctuation as possible. This means that a reduction in the operating current by C _CM is desired. In the t = 0 to 0.1 is shown without control procedure and t = 0.1 to 0.2 with activated control procedure.

9a illustrates the behavior when compensating for the influence of the fluctuation of the intermediate circuit voltage ν _DC . For this, the voltage of the upper intermediate circuit half ν _C1 was kept constant and a fluctuation was assumed for the lower intermediate circuit half ν _C2 . The fluctuation in the voltage ν _C2 leads to a fluctuation in the voltage ν _CCM across the capacitance C _CM and thus to the leakage current i _CCM . By applying the voltage ν _CM according to method 1, the fluctuation in ν _CCM and thus the leakage current i _CCM can be compensated.

In 9b The control is illustrated based on a ν _DC-PE = ν _CCM measurement. A voltage drop at the filter components ν _ZN (see 5a) , a displacement voltage or voltage difference between the operating and system earthing ν _ZPE and a fluctuation in the intermediate circuit voltage ν _DC are assumed. The superposition of these components leads to the shown common mode voltage ν _CCM over capacitance C _CM and thus to the leakage current i _CCM . Compensation according to method 2 can greatly reduce the leakage current. The level of the remaining leakage current depends on the filtering or the controller used (TF 8 b) away.

9c illustrates a compensation via the voltage measurement ν _CX in the neutral conductor path and ν _C2 according to method 3 using a controller. Here, in particular, the voltage drop at L _D1 in the neutral conductor ν _ZN (see 5 a) and compensates for fluctuations in the intermediate circuit voltage. The com compensation according to method 3 can greatly reduce the leakage current. The level of the remaining leakage current depends on the filtering or the regulator used (TF 8 b) away.

9d shows a compensation of the voltage drop ν _ZN across the filter components (eg L _D1 ). Compensation according to method 4 can greatly reduce the leakage current. The level of the remaining leakage current depends on the filtering or the regulator used (TF 8 b) away.

All elements in the path in which the sum of the voltage drops is formed can be taken into account. Examples of factors that influence this are the inductances L _D1 and L _D2 , their ohmic components, the voltage drop of the semiconductor switches, the network impedance (this value is usually unknown) and connecting cables. For single-phase operation, for example, LD1, LD2 and the network impedance in the neutral conductor are taken into account by the last three terms in formula 13. For the multi-phase application, the elements of the three phases are taken into account by the last three terms in formula 7. In general, the voltage at the elements can be expressed using the following formula. $$v_L=R_L\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$$

It should be noted that the necessary derivation of the current with time is usually difficult in practical implementation.

With regard to the above embodiments, it should be noted that instead of the battery, there may of course also be another DC voltage source or DC voltage sink, e.g. a fuel cell or an electrolysis.

In the above-described examples, the focus was on certain systems, such as the TN-CS system. In other systems, such as the TN-S system or the TT system, the influences on the common mode voltage are different. For example, displacement voltages and potential differences occur between the operational and system earthing, e.g. in the TT system (see. 7c ). Advantageously, the approaches described above and in particular the approach from 3 , e.g. Method 2 regulates these displacement voltage potential differences as best as possible.

Although some aspects have been described in the context of a device, it is to be understood that these aspects also represent a description of the corresponding method, so that a block or component of a device can also be understood as a corresponding method step or as a feature of a method step. Analogously, aspects described in the context of or as a method step also represent a description of a corresponding block or detail or feature of a corresponding device. Some or all of the method steps can be implemented by a hardware apparatus (or using a hardware apparatus), such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or more of the key method steps can be performed by such an apparatus.

Depending on particular implementation requirements, embodiments of the invention may be implemented in hardware or in software. The implementation may be performed using a digital storage medium, for example a floppy disk, a DVD, a Blu-ray Disc, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or other magnetic or optical storage on which electronically readable control signals are stored that can or do interact with a programmable computer system in such a way that the respective method is carried out. Therefore, the digital storage medium may be computer readable.

Some embodiments according to the invention thus comprise a data carrier having electronically readable control signals capable of interacting with a programmable computer system such that one of the methods described herein is carried out.

In general, embodiments of the present invention may be implemented as a computer program product having a program code, wherein the program code is operable to perform one of the methods when the computer program product is run on a computer.

The program code can, for example, also be stored on a machine-readable medium.

Other embodiments include the computer program for carrying out one of the methods described herein, wherein the computer program is stored on a machine-readable medium. In other words, an embodiment of the method according to the invention is thus a computer program that has a program code for carrying out one of the methods described herein when the computer program runs on a computer.

A further embodiment of the methods according to the invention is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for carrying out one of the methods described herein is recorded.

A further embodiment of the method according to the invention is thus a data stream or a sequence of signals which represents the computer program for carrying out one of the methods described herein. The data stream or the sequence of signals can be configured, for example, to be transferred via a data communication connection, for example via the Internet.

A further embodiment comprises a processing device, for example a computer or a programmable logic device, which is configured or adapted to carry out one of the methods described herein.

A further embodiment comprises a computer on which the computer program for carrying out one of the methods described herein is installed.

A further embodiment according to the invention comprises a device or a system which is designed to transmit a computer program for carrying out at least one of the methods described herein to a recipient. The transmission can be carried out electronically or optically, for example. The recipient can be, for example, a computer, a mobile device, a storage device or a similar device. The device or system can, for example, comprise a file server for transmitting the computer program to the recipient.

In some embodiments, a programmable logic device (e.g., a field programmable gate array, an FPGA) may be used to perform some or all of the functionality of the methods described herein. In some embodiments, a field programmable gate array may interact with a microprocessor to perform any of the methods described herein. In general, in some embodiments, the methods are performed by any hardware device. This may be general-purpose hardware such as a computer processor (CPU) or hardware specific to the method such as an ASIC.

The above-described embodiments are merely illustrative of the principles of the present invention. It is understood that modifications and variations of the arrangements and details described herein will occur to others skilled in the art. Therefore, it is intended that the invention be limited only by the scope of the following claims and not by the specific details presented in the description and explanation of the embodiments herein.

literature

1. [1] Common Mode Analysis of Non-Isolated Three-Phase EV-Charger for BiDirectional Vehicle-to-Grid Operation, B. Strothmann, PCIM Europe2019, 7-9 May 2019, Nuremberg, Germany
2. [2] Common-Mode-Free Bidirectional Three-Phase PFC-Rectifier for Non-Isolated EV Charger, B. Strothmann, 2021 IEEE Applied Power Electronics Conference and Exposition
3. [3] Single-Phase Operation of Common-Mode-Free Bidirectional Three-Phase PFC-Rectifier for Non-Isolated EV Chargerwith Minimized DC-Link, B. Strothmann, PCIM Europe digital days 2021, 3 - 7 May 2021
4. [4] Elimination of Common-Mode Voltage in Three-Phase Sinusoidal Power Converters, Alexander L. Julian, IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 5, SEPTEMBER 1999

Reference symbols

10

circuit

12

Power converter circuit

20a, 20b

Potential tap

18a, 18b, 18a', 18b', 18c'

Phase connections

25

steering

14

elements

22

Intermediate circuit

24

Capacity arrangement

QUOTES INCLUDED IN THE DESCRIPTION

This list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions.

Cited patent literature

• DE 102017216468 A1 [0102]
• US 11228238 B2 [0102]

Cited non-patent literature

• Common Mode Analysis of Non-Isolated Three-Phase EV-Charger for BiDirectional Vehicle-to-Grid Operation, B. Strothmann, PCIM Europe2019, 7-9 May 2019, Nuremberg, Germany [0133]
• Common-Mode-Free Bidirectional Three-Phase PFC-Rectifier for Non-Isolated EV Charger, B. Strothmann, 2021 IEEE Applied Power Electronics Conference and Exposition [0133]
• Single-Phase Operation of Common-Mode-Free Bidirectional Three-Phase PFC-Rectifier for Non-Isolated EV Chargerwith Minimized DC-Link, B. Strothmann, PCIM Europe digital days 2021, 3 - 7 May 2021 [0133]
• Elimination of Common-Mode Voltage in Three-Phase Sinusoidal Power Converters, Alexander L. Julian, IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 5, SEPTEMBER 1999 [0133]

Claims (24)

Circuit (10), with the following features: a converter circuit (12) which has a DC voltage connection with two potential taps (20a, 20b) and one or more phase connections (18a, 18b, 18a', 18b', 18c'); and a controller (25), wherein the controller (25) is designed to control switchable elements (14) of the converter circuit (12) such that a voltage at one of the two potential taps (20a, 20b) and/or at one of the one or more phase connections (18a, 18b, 18a', 18b', 18c') is modulated based on a common mode voltage; wherein the common mode voltage ν _CM is based on the formula $$v_{CM}=\frac{\overline{V_{DC}}-v_{DC}}{2}$$

or where the common mode voltage ν _CM is calculated based on a formula that contains the term $\frac{\overline{V_{DC}}-v_{DC}}{2}$

where ν _DC represents the voltage between two potential taps (20a, 20b) of the DC voltage connection; and/or where the common mode voltage ν* _CM is calculated based on the formula $$v_{CM}^{*}=v_{DC-PE}+\frac{\overline{V_{DC}}}{2}$$

is calculated, where ν _DC represents the voltage between two potential taps (20a, 20b) of the DC voltage connection; and/or where the common mode voltage $v_{CM}^{*}$

based on the formula $$v_{CM}^{*}=-v_{CX}+\frac{\overline{V_{DC}}}{2}-v_{C2}$$

is calculated, where ν _DC represents the voltage between two potential taps (20a, 20b) of the DC voltage connection; and/or where the common mode voltage ν _CM is calculated based on the formula $$v_{CM}=R\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$$

is calculated. Circuit (10) according to Claim 1 , wherein currents in the one or more phases (18a', 18b', 18c') are symmetrical and/or wherein the converter circuit (12) is designed for three-phase operation. Circuit (10) according to Claim 1 , wherein currents in the one or more phase connections (18a, 18b) are asymmetrical and/or wherein the converter circuit (12) is designed for single-phase operation. Circuit (10) according to Claim 2 or 3 , where the common mode voltage ν _{CM, B6} is based on the formula $$v_{CM,B6}=\frac{\overline{V_{DC}}-v_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

with $$\begin{array}{l}{v}_{LD1CM}=\frac{1}{3}(R_{LD1}\cdot \left(i_{LD\mathrm{1,}L1}+i_{LD\mathrm{1,}L2}+i_{LD\mathrm{1,}L3}\right)+L_{LD1}\\ \cdot \left(\frac{d}{dt}{i}_{LD\mathrm{1,}L1}+\frac{d}{dt}{i}_{LD\mathrm{1,}L2}+\frac{d}{dt}{i}_{LD\mathrm{1,}L3}\right))\end{array}$$

$$\begin{array}{l}{v}_{LD2CM}=\frac{1}{3}(R_{LD2}\cdot \left(i_{LD\mathrm{2,}L1}+i_{LD\mathrm{2,}L2}+i_{LD\mathrm{2,}L3}\right)+L_{LD2}\\ \cdot \left(\frac{d}{dt}{i}_{LD\mathrm{2,}L1}+\frac{d}{dt}{i}_{LD\mathrm{2,}L2}+\frac{d}{dt}{i}_{LD\mathrm{2,}L3}\right))\end{array}$$

$$v_{GCM}=\frac{1}{3}\left(R_G\cdot \left(i_{L1}+i_{L2}+i_{L3}\right)+L_G\cdot \left(\frac{d}{dt}{i}_{L1}+\frac{d}{dt}{i}_{L2}+\frac{d}{dt}{i}_{L3}\right)\right)$$

is calculated. Circuit (10) according to one of the preceding claims, wherein the common mode voltage is based on the combination of the formulas $$v_{CM}=\frac{\overline{V_{DC}}-v_{DC}}{2}\text{and}{v}_{CM}^{*}=v_{DC-PE}+\frac{\overline{V_{DC}}}{2}$$

is calculated, where $v_{CM}^{*}$

can be combined with ν _CM using a transfer function to obtain the common mode voltage. Circuit (10) according to Claim 2 , 3 , 4 or 5 , wherein the ratio between a voltage at the phase terminals (18a, 18b, 18a', 18b', 18c') and a common mode voltage is given by the formula $$v_M=v_{AC}+v_{CM}$$

is determined for the symmetrical or asymmetrical case. Circuit (10) according to Claim 2 or 3 , where the common mode voltage is given by the formula $$v_{CM,H4}=\frac{\overline{V_{DC}}-v_{DC}}{2}+v_{LD1CM}+v_{LD2CM}+v_{GCM}$$

with $$\begin{array}{c}{v}_{LD1CM}=R_{LD1}\cdot i_{LD\mathrm{1,}N}+L_{LD1}\frac{d}{dt}{i}_{LD\mathrm{1,}N}\\ v_{LD2CM}=R_{LD2}\cdot i_{LD\mathrm{2,}N}+L_{LD2}\frac{d}{dt}{i}_{LD\mathrm{2,}N}\\ v_{GCM}=R_G\cdot i_N+L_G\frac{d}{dt}{i}_N\end{array}$$

is calculated. Circuit (10) according to Claim 3 or 7 , where a relationship between a voltage at one of the phase inputs and the common mode voltage is given by the formula $$\begin{array}{c}{v}_{H\mathrm{4,}L1}=v_{L1}+v_{CM,H4}\\ v_{H\mathrm{4,}N}=v_{CM,H4}\end{array}$$

is defined for the single-phase case. Circuit (10) according to one of the preceding claims, wherein it comprises an intermediate circuit (22) and/or a symmetrical intermediate circuit (22), wherein the intermediate circuit (22) or the symmetrical intermediate circuit (22) is arranged between the two potential taps (20a, 20b) of the DC voltage connection. Circuit (10) according to Claim 9 , wherein a center point of the intermediate circuit (22) is connected to one phase via a capacitor or to several phases via a capacitor arrangement (24). Power converter circuit (12) according to one of the preceding claims, wherein in single-phase operation ν _CX = ν _CXN is defined and in three-phase operation ν _CX = ν _CXL1 + ν _CXL2 + ν _CXL3 is defined; and/or wherein in single-phase operation i = i _N is defined and in three-phase operation i = i _L1 + i _L2 + i _L3 is defined. Power converter circuit (12) according to one of the preceding claims, wherein the power converter circuit (12) comprises a rectifier, inverter or AC-DC converter. Circuit (10) according to one of the preceding claims, which has a measuring unit which is designed to determine ν _DC = ν _C1 + ν _C2 as an input variable for the calculation and/or to determine ν _CCM with ν _CCM = ν _DC-PE = ν _MPE - ν _C2 as an input variable for the calculation and/or to determine ν _CX and ν _C2 as an input variable for the calculation Rectifier or non-isolated rectifier or battery charger comprising a circuit (10) according to any one of the preceding claims. Rectifier or non-isolated rectifier or battery charger in accordance with Claim 14 for operation on a TN-C, TN-CS or TN-S system. Method for operating a circuit (10) according to one of the preceding claims, wherein the method comprises a step of modulating a voltage at one of the two potential taps (20a, 20b) and/or at one of the phase connections (18a, 18b, 18a', 18b', 18c') based on a common mode voltage, wherein the common mode voltage ν _CM,B6 is based on the formula $$v_{CM}=\frac{\overline{V_{DC}}-v_{DC}}{2}$$

or where the common mode voltage ν _CM is calculated based on a formula that contains the term $\frac{\overline{V_{DC}}-v_{DC}}{2}$

is calculated, where ν _DC represents the voltage between two potential taps (20a, 20b) of the DC voltage connection; and/or where the common mode voltage $v_{CM}^{*}$

based on the formula $$v_{CM}^{*}=v_{DC-PE}+\frac{\overline{V_{DC}}}{2}$$

is calculated, where ν _DC represents the voltage between two potential taps (20a, 20b) of the DC voltage connection; and/or where the common mode voltage $v_{CM}^{*}$

based on the formula $$v_{CM}^{*}=-v_{CX}+\frac{\overline{V_{DC}}}{2}-v_{C2}$$

is calculated, where ν _DC represents the voltage between two potential taps (20a, 20b) of the DC voltage connection; and/or where the common mode voltage ν _CM is calculated based on the formula $$v_{CM}=R\cdot i\left(t\right)+L\cdot \frac{di\left(t\right)}{dt}$$

is calculated. Computer program for carrying out a method according to Claim 16 if the method is based on a converter circuit (12) according to one of the Claims 1 until 13 expires. Circuit (10), with the following features: a converter circuit (12) which has a DC voltage connection with two potential taps (20a, 20b) and one or more phase connections (18a, 18b, 18a', 18b', 18c'); and a controller (25), wherein the controller (25) is designed to switchable elements (14) of the converter circuit (12) to control such that a voltage at one of the two potential taps (20a, 20b) and/or at one of the phase connections (18a, 18b, 18a', 18b', 18c') is modulated based on a common mode voltage; measuring unit designed to determine a voltage on the DC side with respect to earth; wherein the common mode voltage is determined using the voltage measured by the measuring unit. Circuit according to Claim 18 , wherein the voltage is measured between a midpoint of an intermediate circuit arranged between the two potential taps (20a and 20b) and one of the potential taps; or wherein the voltage is measured between a midpoint of an intermediate circuit arranged between the two potential taps and one of the potential taps, wherein an additional voltage on the AC side is measured between one of the phases and the midpoint of the intermediate circuit or wherein the additional voltage is measured between one of the phases and earth. Circuit according to Claim 19 , where the voltage is measured between one of the potential taps and earth or where the voltage is measured between the negative or the positive potential tap and earth. Rectifier or non-isolated rectifier or battery charger with a circuit (10) according to Claim 18 , 19 or 20 . Rectifier or non-isolated rectifier or battery charger in accordance with Claim 23 for operation on a TT system. Method for operating a circuit (10) according to Claim 20 , 21 or 22 , wherein the method comprises a step of modulating a voltage at one of the two potential taps (20a, 20b) and/or at one of the phase terminals (18a, 18b, 18a', 18b', 18c') based on a common mode voltage, wherein the common mode voltage is determined using the voltage measured by the measuring unit on the DC side with respect to earth. Computer program for carrying out a method according to Claim 23 , if the method is carried out on a circuit (10) according to Claim 18 expires.

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