DE102021132516A1 - METHODS, DEVICES AND SYSTEMS FOR INDUCTIVE SCANNING - Google Patents

Abstract

A method may include: in a first phase of a sensing operation, controlling at least a first switch to energize a sensor inductance; in a second phase of the sensing operation subsequent to the first phase, controlling at least a second switch to couple the sensor inductance to a first modulator capacitance to induce a first flyback current from the sensor inductance, the first flyback current producing a first modulator voltage across the first modulator capacitance generated; and in response to the first modulator voltage, controlling at least a third switch to generate a transient current that flows in the opposite direction to the flyback current at the first modulator node. The first and second phases can be repeated to generate a first modulator voltage across the first modulator capacitance. The modulator voltage can be converted to a digital value that represents the sensor inductance. Associated devices and systems are also disclosed.

Description

TECHNICAL AREA

The present disclosure relates generally to proximity sensing systems, and more particularly to inductive sensing systems and methods.

BACKGROUND

Inductive sensors are used in a variety of applications. Because inductive sensors rely on electromagnetic induction, they may be preferred for use in more demanding environments, including industrial applications.

25 12 is a schematic diagram of a conventional inductive sensing system 2551. The system 2551 may include a balanced Maxwell-Wien bridge having fixed resistors R1 and R3, a reference capacitance C2 in parallel with reference resistor R2, and a sensor inductor LX in series with a sense resistor Rlx. The A and B nodes of the Maxwell-Wien bridge can be connected to the inputs of a differential amplifier. The reference capacitance C2 and reference resistance R2 are typically sets of resistors and capacitors that can be programmed to specific values using digital codes. The Maxwell-Wien bridge can be powered by an AC generator (Gen), typically a sine wave. An output of a differential amplifier can be applied to a zero voltage detector and phase detector from which a count can be generated.

$$R{l}_x=\frac{R_3}{R_2}\cdot R_1$$

$$\frac{L_x}{R_{lx}}=R_2\cdot C_2$$

A sampling process can be based on trying to keep the Maxwell-Wien bridge in a balanced state. In a balanced condition, a voltage between nodes A and B is zero, and the following formulas hold: $$L_x=R_1\cdot R_3\cdot {\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102021132516A1\_0028.png,DE102021132516A1\_0033.png"\; state="\{\{state\}\}">C</figure-callout>}}_2$$

$$R{l}_x=\frac{R_3}{R_2}\cdot R_1$$

$$\frac{L_x}{R_{lx}}=R_2\cdot {\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102021132516A1\_0028.png,DE102021132516A1\_0033.png"\; state="\{\{state\}\}">C</figure-callout>}}_2$$

Sensing with a Maxwell-Wien bridge depends on knowing the resistance and capacitance values. Furthermore, measurement accuracy and stability depend on the quality of the capacitance and resistance sets.

Maxwell-Wien bridge sensing is commonly used in conventional inductive sensing devices.

26 12 is a schematic diagram of another inductive sensing system 2651. The system 2651 can create an oscillator with a sensed inductance and use a resulting frequency Fout to derive a value for the inductance. The oscillator is formed with the sensor inductance L1, the capacitances C1 and C2 and a current-limiting resistor R1. Such components are formed “off-chip”, with the driver, counter, timer and clock generator being part of an integrated circuit (IC). Sensor inductance may include coil resistance RI and parasitic capacitance Ci. A counter can count a number of Fout signal clock pulses over a period Nsample. The inductance-to-code transfer function for an ideal 2651 system can be given as: $$ROH\mathrm{e.g}\ddot{a}Hl\mathrm{and}nGen=\frac{1}{2\cdot \pi }\cdot \sqrt{\frac{2}{C}}\cdot \frac{N_{sample}}{f_{clk}}\cdot \frac{1}{\sqrt{{\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102021132516A1\_0035.png"\; state="\{\{state\}\}">L</figure-callout>}}_1}}$$

As shown, an output code raw counts is inversely proportional to a square root of inductance L1, capacitances C1, C2 and frequency Fclk.

A disadvantage of the 2651 system can be the limited sampling resolution since the sampling depends on Fclk. In addition, Fout is constrained by the printed circuit board (PCB) inductor's natural resonant frequency and FIMO values. The conversion sensitivity is lower than the sensor sensitivity due to the square root dependence of the transfer function. As shown below, changes in fout frequency are proportionally less than changes in sensor inductance: $$\delta {ƒ}_{Osc}=1-\sqrt{\frac{1}{1-\frac{\Delta L_s}{L_s}}}if\frac{\Delta L_s}{L_s}=0.1\left(10\%\right)\delta {ƒ}_{Osc}=-5.4\%$$

In a 2651 system, the initial Fout tolerance can be high due to the tolerances of L1, C1, and C2. For example, PCB inductor tolerance is typically no more than +-15% and typical capacitor tolerance is +-10%. In addition, Fout depends on the sensor capacitance, especially at high resolution. In addition, the impedance of the driver can affect the fout frequency. The need to address these different characteristics can complicate the implementation of multi-sensor sensing. Because of the various tank oscillator components required per sensor, multi-sensor sampling systems can have a high component count. As a result, an approach such as that of the 2651 system can be inflexible and unsatisfactory for some applications.

It would be desirable to find a way that implements inductance sensing with an integrated circuit device that does not suffer from the disadvantages of other approaches such as those mentioned above.

character list

• 1A 12 is a block diagram of an inductive scanning device according to an embodiment.
• 1B 12 is a schematic diagram of a single-ended inductive sensing apparatus according to an embodiment.
• 2 1 is a schematic diagram of a current path of an inductive sensor that may be included in embodiments.
• 3 12 is a schematic diagram of a three-point sensor connection according to an embodiment.
• 4A until 4D 12 illustrates a series of diagrams showing different phases of an inductance sensing operation according to one embodiment.
• 5 12 is a timing diagram showing a single-ended inductance sensing operation according to an embodiment.
• 6 12 is a schematic diagram of a single-ended inductive pickup device according to another embodiment.
• 7A until 7D 12 illustrates a series of diagrams showing different phases of an inductance sensing operation according to another embodiment.
• 8th 12 is a schematic diagram of a single-ended inductive pickup device utilizing a compensation current according to an embodiment.
• 9 12 is a schematic diagram of a single-ended inductive pickup device utilizing a compensation current according to another embodiment.
• 10A 12 is a schematic diagram of a pseudo-differential inductive scanning device according to an embodiment.
• 10B 12 is a schematic diagram of a pseudo-differential inductive scanning device according to another embodiment.
• 11A until 11H 12 illustrates a series of diagrams showing different phases of an inductance sensing operation according to another embodiment.
• 12 12 is a timing diagram showing a pseudo-differential inductance sensing operation according to another embodiment.
• 13 12 is a schematic diagram of a pseudo-differential inductive scanning device according to an embodiment.
• 14A until 14D 12 illustrates a series of diagrams showing different phases of a pseudo-differential inductance sensing operation according to another embodiment.
• 15 12 is a timing diagram showing a pseudo-differential inductance sensing operation according to an embodiment.
• 16A 12 is a schematic diagram of a pseudo-differential inductive scanning device according to another embodiment.
• 16B 12 is a schematic diagram of a pseudo-differential inductive scanning device according to another embodiment.
• 17A until 17H 12 illustrates a series of diagrams showing different phases of a pseudo-differential inductance sensing operation according to another embodiment.
• 18 12 is a schematic diagram of a pseudo-differential inductive scanning device using a compensation current according to an embodiment.
• 19 12 is a block diagram of a system according to one embodiment.
• 20 12 is a block diagram of a system according to another embodiment.
• 21 12 is a flow chart of an inductance sensing method according to an embodiment.
• 22 12 is a flow chart of an inductance sensing method according to another embodiment.
• 23 12 is a flow chart of an inductance sensing method according to another embodiment.
• 24 12 is a flow chart of an inductance sensing method according to another embodiment.
• 25 12 is a block diagram of a conventional inductance sensor.
• 26 12 is a block diagram of another conventional inductance sensor.

DETAILED DESCRIPTION

Embodiments may include inductive sensing methods, apparatus, and systems based on inducing a fly-back current from the sensed inductor. Generating a flyback current generally involves two phases. In a first phase, the inductance is coupled to a voltage source to accumulate energy. In a second phase, the inductance is decoupled from the voltage source and coupled to a load. The energy accumulated in the first phase creates an electromotive force (EMF) that generates a flyback current at the load. The accumulated energy is directly proportional to the inductance.

According to embodiments, the inductive sensing may be single-ended, generating a one-way flyback current that generates a voltage that may be sigma-delta modulated into a digital value.

According to embodiments, the inductive sensing may be pseudo-differential, generating a first return current of one direction and then a second return current of another direction. The first and second flyback currents can produce a differential voltage that can be sigma-delta modulated into a digital value.

According to embodiments, the pseudo-differential sampling may include four phases. A first phase can excite a sensed inductor. A second phase can generate a first flyback current at a first modulator node. A third phase can excite the sensed inductance a second time. A fourth phase may generate a second retrace current at a second modulator node that has a direction of flow opposite to that of the first retrace current.

According to embodiments, a flyback current at a modulator node may be balanced by a balancing current to optimize sensing response. A compensating current can modulated by the voltage at the modulator node (e.g. via a feedback path). In some embodiments, a transient current may be generated by a switched capacitor circuit. Such a switched capacitor circuit may include a programmable capacitance.

According to embodiments, a flyback current at a modulator node may be controlled by a reference current flowing in the opposite direction. In some embodiments, a reference current may be generated by a switched capacitor circuit. Such a switched capacitor circuit may include a programmable capacitance.

In the various embodiments described herein, like elements are denoted by the same reference numerals, with the first digit(s) corresponding to the figure number.

1A 10 is a block diagram of an inductive scanning device 100A according to an embodiment. An apparatus 100A may include an analog front end (AFE) 121A and a digital (e.g., encoding) portion 123A. The AFE 121A may include a flyback section 102A and a sigma-delta modulator 105A and may be coupled to one or more inductive sensors (one shown as 116A). An inductive sensor 116A may have a sensing inductance Ls. In some embodiments, inductive sensor 116A may be coupled to device 100A through external connectors 107 . A retrace section 102A may couple the sense inductance Ls to an excitation voltage and then subsequently couple the sense inductance Ls to a modulator node 106A to generate a retrace current (Ireturn). All or a portion of the sense current Isen may generate a voltage (Vmod) at the modulator node 106A. The sigma-delta modulator 105A can generate a bitstream 112A from Vmod. Such a bit stream can correspond to a sampled inductor Ls.

A bitstream 112A may be converted to a digital value (code 113) representing an inductance by digital portion 123A. In the embodiment shown, the digital portion 123A may include a digital filter/decimator 109 that may filter out noise and downsample the modulator results to generate code values 113 . The code values 113 can be output and/or stored in a buffer 117 or the like.

1B 10 is a schematic diagram of an inductive scanning device 100B according to another embodiment. A device 100B may include an AFE 121B and an encoding section 123B. The AFE 121B may include a flyback section 102B, a sigma-delta modulator 105B, and a compensation section 104 . The encoding section 123B may include a flip-flop (FF) 110, feedback logic 114, and a digital sequencer 115. A flyback section 102B can energize a sensor inductance Ls that switches voltages across Ls to induce a flyback current Isen. The return current Isen can vary with the sensor inductance Ls. A flyback section 102B may include analog switches SW0, SW1, SW2, SW3, and SW4 that may be coupled to an inductive sensor 116B (also called sensor cell 116B). In some embodiments, such connections can be made via external connections (e.g., Tx, Rx) of the device 100B. Inductive sensor 116B may include sensing inductance Ls and inductor resistance Rs. The switch SW0 can be controlled by a signal Ph0 to couple a first sensor node (Tx) to a high voltage supply node VDDA. Switch SW1 can be controlled by signals Ph0/Ph3 to couple a second sensor node (Rx) to a low voltage supply node (ground). Switch SW2 can be controlled by signal Ph2 to couple Rx to a modulator node 106 . Switch SW3 can be controlled by signal Ph1 to couple Rx to VDDA. Switch SW4 can be controlled by signals Ph1/Ph2/Ph3 to couple Tx to ground.

A balancing section 104 may be a switched capacitor (SC) circuit that can charge a capacitance (Cref) across a node (Ca) and then switch the voltage at the node to induce a balancing current (Ibal). The compensation section 104 may include analog switches SW5, SW6, SW7, and SW8. A balancing section 104 may include (or be coupled to) a reference cell 118, which may include a variable capacitance Cref. Reference cell 118 may include nodes Ca and Cb. A capacitance value of Cref can be specified with the value Ccode, which in some embodiments can be a digital value. SW5 can be controlled by a signal Ph1_mod to couple Ca to a high voltage supply node VDDA. SW6 can be controlled by a signal Ph1_mod_fb to couple Cb to ground. SW7 can be controlled by a signal Ph0_mod_fb to couple Cb to modulator node 106 . SW8 can be controlled by signal Ph0_mod to couple Ca to ground.

The sigma-delta modulator 105B may include the modulator capacitance Cmod, the switch SW9, the comparator 108 and the flip-flop FF 110. SW9 can be controlled to couple modulator node 106 to ground. Cmod can be coupled between modulator node 106 and ground and can be charged and discharged to generate a modulator voltage Vmod. Comparator 108 may have a first (non-inverting) input coupled to modulator node 106 and a second (inverting) input coupled to ground.

An output of comparator 108 Vout may be coupled to a "D" input of FF 110 . FF 110 can be activated by a clock signal Fmod. An output (Q) of FF 110 can thus provide a sigma-delta modulated bitstream 112B with a duty cycle that varies with Vmod. Vmod can vary according to Isen, which in turn can vary according to Ls. In this way, the bitstream 112B can represent Ls.

Digital sequencer 115 may generate signals Ph0, Ph1, Ph2, Ph3, and combinations thereof (e.g., Ph1/Ph2/Ph3 and Ph0/Ph3). In addition, the digital sequencer 115 can generate the signals Ph0_mod and Ph1_mod. In the embodiment shown, such signals may be synchronous with Fmod. The feedback logic 114 may generate non-overlapping Ph0_mod_fb and Ph1_mod signals in response to the bitstream 112B and the Ph0_mod and Ph1_mod signals, respectively. In the embodiment shown, Ph0_mod_fb and Ph1_mod_fb may be synchronous with Fmod, in other embodiments these signals may have different timing.

While the embodiments herein show sensor inductances that can be excited with particular supply voltages (e.g., VDDA, VDDA/2), these particular supply voltages are not intended to be limiting. Embodiments may excite a sensor inductor with any suitable supply voltage, including voltages that have been stepped down from a power supply voltage and/or voltages that have been increased beyond a power supply voltage (e.g., Vbe).

In order to better understand the features and advantages of the disclosed embodiments, the elements of the inductive sensing will be described.

A typical printed circuit board (PCB) inductor may have an inductance of tens of microhenries and a resistance of tens of ohms. A time constant of an inductor is given as follows: $$\tau =\frac{L_s}{{\mathrm{right}}_s}$$

In equivalent circuits, the rs value may include the sensor inductance resistance (Rs) and the analog switch resistances ( _Rsw ). Typically the analog switch resistance can be equal to or higher than Rs.

Ein Sensorsättigungsstrom Isat, kann wie folgt angegeben werden: $$Isat=\frac{V_{DDA}}{{\displaystyle \sum R_i}}wobei{\displaystyle \sum R_i=R_s+R_{sw}+R_{ex}}$$

Gemäß Ausführungsformen kann Rex verwendet werden, um einen Sensorsättigungsstrom zu reduzieren. Eine Erhöhung des Gesamtstromschleifenwiderstands in dem Abtastpfad ist jedoch unerwünscht. Wenn die Sensorinduktivität (Ls) niedrig und der Schleifenwiderstand (Rs+Rsw+Rex) hoch ist, kann die Zeitkonstante niedriger werden als eine Systemtaktfrequenz. Dies kann einen Wandlerbetriebszeitraum begrenzen. 2 12 is a schematic diagram equivalent to the current path 217 of the inductive sensor. Current path 217 may include sensor inductance (Ls), inductor resistance (Rs), and additional external resistance (Rex). As a result, a time constant for the inductive sensor can be given as: $$\tau =\frac{L_s}{R_s+R_{ex}+R_{sw}}$$

A sensor saturation current Isat can be specified as follows: $$Isat=\frac{V_{DDA}}{{\displaystyle \sum R_i}}wObei{\displaystyle \sum R_i=R_s+R_{sw}+R_{ex}}$$

According to embodiments, Rex can be used to reduce sensor saturation current. However, increasing the total current loop resistance in the scan path is undesirable. When the sensor inductance (Ls) is low and the loop resistance (Rs+Rsw+Rex) is high, the time constant can become lower than a system clock frequency. This can limit a converter operating period.

According to embodiments, a three-point sensor connection may be used to advantageously include Rex in inductor excitation operations, thereby reducing Isat while excluding Rex from sensing operations, and thereby providing an advantageously lower time constant for the sensed inductor.

3 319 is a schematic diagram of a three-point sensor connection 319 according to an embodiment. 3 FIG. 3 shows an inductive sensor 316 and a sensing device 300, which may be an integrated circuit (IC) in some embodiments. The inductive sensor 316 may have a first terminal (A) coupled to a first port 307 - 0 of the device 300 . A second terminal (B) may be coupled to a second port 307-1 and to a third port 307-2. The connection to the third connection 307-2 may include the resistance Rex, whereby this connection can become a path with a higher resistance than the path to the second connection 302-1.

Device 300 may include an analog scan path switch SW2 (which may introduce a resistor Rsw) and an analog excitation path switch SW1. Typically, a pull-up or pull-down switch (i.e., SW1) may have a lower resistance than an analog MUX switch (i.e., SW2). In an excitation operation, SW1 can be activated and SW2 deactivated, with sensor terminal B being coupled to ground (sensor terminal A can be coupled to an excitation voltage). As a result, Rex can affect a resulting Isat value. In contrast, in a scanning operation in which a flyback current is induced, SW1 can be deactivated and SW2 can be activated. As a result, flyback current (flowing through SW2) is not subject to the Rex, providing lower current loop resistance and hence an advantageously smaller time constant τ.

4A until 4D 12 depict a series of diagrams depicting sampling phases for inductive sampling according to embodiments including those in FIG 1B shown, show. According to embodiments, inductive sensing may include a number of phases, which may include switching configurations to clamp inductive sensors to generate a flyback current to vary a voltage across a modulator capacitance. 4A until 4D Figure 12 shows a return section 402 which may have connections to terminals (A and B) of inductive sensor 416. The inductive sensor 416 can have an inductance Ls and a resistance Rs.

4A shows a first phase (Ph0), which can be an excitation phase. In Ph0, operation of one or more switches (e.g., SW0 and SW1) may couple terminal A to an excitation voltage, which in the embodiment shown may be a high power supply node VDDA. At the same time, terminal B may be coupled to a low-power supply node (ground). A voltage (Vsen) across the sensor 416 can excite the inductor Ls.

4B shows a second phase (Ph1), which can be an optional energy recovery phase. In Ph1, through the operation of switches (e.g., SW3 and SW4), terminal A may be coupled to a lower power supply node, while terminal B may be coupled to a higher voltage node (VDDA in this case). Ph1 can be used to reduce a subsequent flyback current from Ls if required. If Ph1 is omitted, a sampling operation can transition from a first phase (Ph0) to a third phase (Ph2).

4C shows a third phase (Ph2), which may be a charge accumulation phase. In Ph2, through the operation of switches (e.g., SW2 and SW4), the B terminal can be coupled to a modulator capacitance (Cmod) and the B terminal can be coupled to a potential that can induce a flyback current from Ls that is present in the embodiment shown is a low power supply node. Charge can accumulate on Cmod due to flyback current (Isen). A resulting voltage on Cmod can be modulated to determine Ls. A duration of Ph2 can control a signal-to-noise ratio (SNR) of the sampling.

4D shows a fourth phase (Ph3), which can be an optional idle phase. In Ph3, terminals A and B can both be coupled to a low-power supply node through the operation of switches (e.g., SW1 and SW4). Ph3 can discharge remaining energy in Ls. Accordingly, Ph3 can be used to control the sampling frequency and affect the power consumption and a balance condition of a modulator node (ie, Cmod). After Ph3, a scan operation can return to Ph0 to repeat the sequence. If Ph3 is omitted, a scan operation can go from Ph2 to Ph0 to repeat the sequence.

The different sampling phases can produce a voltage on Cmod that can be sigma-delta modulated to produce a bitstream that can be sampled to obtain the sampled inductance values.

Regarding 5 is a time chart for the operations of the in 1B device 100B shown. The timing diagram shows: the modulation clock Fmod; the different sampling phases Ph0, Ph1, Ph2 and Ph3; a resulting bit stream (Bitstream); feedback signals Ph0_mod_fb, Ph1_mod_fb; an inductor voltage VLs; an inductor current ILs; a resulting sampled current Isen; a modulation voltage Vmod; and a balancing current Ibal.

At time t0, Ph0 can begin. SW0 and SW1 are allowed to close, placing VDDA across a sensor inductor (Ls), energizing Ls.

At time t1, Ph0 may end and Ph1 begin. SW0 and SW1 are allowed to open while SW3 couples node r/x to VDDA and SW4 couples node Rx to ground. A voltage across Ls can switch and Ls can start to be de-energized.

At time t2, Ph1 can end and Ph2 can begin. SW3 can open and SW2 can couple node Rx to modulator node 106 . As a result, a flyback current can be generated through Ls. The retrace sense current may flow to the modulator node 106 through the operation of SW2 to generate a modulator voltage Vmod. In the embodiment shown, Isen may be a source current for modulator node 106 .

At time t3, which occurs during Ph2, an output of comparator 108 Vout may be driven high due to Vmod. This can cause FF 110 to drive output Q (i.e., bitstream 112B) high. A high bit stream 112B may be received by feedback logic 114 . The feedback logic 114 may then generate the Ph0_mod_fb pulse followed by the Ph1_mod_fb pulse. The pulse Ph0_mod_fb can result in a transient current Ibal due to the switched capacitor operation of Cref. As shown, Ibal may be a sink current from modulator node 106 that may reduce Vmod. Cref can then be charged by operating switches SW5 and SW6. Provided bitstream 112B remains high, current Ibal can continue to be generated.

At time t4, Ph2 may end and Ph3 begin. SW2 is allowed to open, stopping modulator node 106 from being charged by flyback current Isen. Operation of SW4 and SW1 allows both nodes Tx and Rx of inductive sensor 116B to be coupled to ground. In the embodiment shown, Vmod continues to drive the bitstream high, so Ph0_mod_fb and Ph1_mod_fb can continue and generate an Ibal current that continues to drive Vmod toward zero volts.

At time t5 a subsequent Ph0 can begin and the detection process can repeat.

Waveforms 531 show how signals Ph0_mod_fb and Ph1_mod_fb can be generated in relation to signals Ph0_mod and Ph1_mod. Such waveforms are provided by way of example and are not to be construed as limiting. Also, as noted herein, although 5 shows the pulses Ph0_mod_fb and Ph1_mod_fb synchronous with Fmod, this timing should not be understood as limiting.

wobei Tph2 die Dauer eines Ladungsakkumulationszeitraums Ph2 ist. In der obigen Formel wird von Folgendem ausgegangen: ein Gesamtsensorwiderstand verändert sich in den Sensorerregungsphasen nicht; eine Ph1-Phase ist nicht enthalten; ein Kapazitätswert Cmod ist hoch genug, sodass der Spannungsabfall während des Ladungsübertragungszeitraums (z. B. Ph2) vernachlässigbar ist; und eine Sensorkapazität (z. B. Ci in 26) hat keinen Einfluss auf das Abtasten.In inductance sensing operations according to embodiments, a total charge accumulated by a modulator capacitance (Cmod) can be calculated using the following formula: $$Q_{pH2}=\frac{V_{DDA}}{{\displaystyle \sum R_I{}^2}}\cdot L_S\cdot \left(1-e^{-T_{pH2}\cdot \frac{{\displaystyle \sum R_i}}{L_S}}\right),$$

where Tph2 is the duration of a charge accumulation period Ph2. In the above formula, it is assumed that: a total sensor resistance does not change in the sensor excitation phases; a Ph1 phase is not included; a capacitance value Cmod is high enough that the voltage drop during the charge transfer period (e.g. Ph2) is negligible; and a sensor capacitance (e.g. Ci in 26 ) does not affect sampling.

Q_{ph2_.max} kann die maximale Ladung sein, die in einem Sensorerregungszyklus (z. B. Ph2) produziert werden kann. Nb_min kann die erforderliche Minimummenge an Fmod-Zyklen sein, um einen Ausgleich zu erreichen. Der Wert Nb_min kann somit eine maximale Sensorerregungsfrequenz F_{s_max} definieren. Diese Frequenz wird nach der folgenden Formel berechnet: $$F_{s\_max}=\frac{F_{mod}}{N_{b\_min}}$$

In einem Ph3-Zeitraum können beide Klemmen der Sensorinduktivität nach dem Ph2-Zeitraum an Masse gekoppelt werden. Wenn die Ausgleichszeitraumdauer länger ist als die Sensorerregungsphasendauer: $$\frac{1}{F_s}>T_{ph0}+T_{ph1}+T_{ph2}+T_{ph3}$$

Die Induktivitäts-zu-Code-Übertragungsfunktion kann wie folgt sein: $$DC=\frac{1}{{\displaystyle \sum R_i{}^2\cdot C_{ref}\cdot N_b}}\cdot L_s\cdot \left(1-e^{-T_{ph2}\cdot \frac{{\displaystyle \sum R_i}}{L_S}}\right)$$

In embodiments like that of 1B and 5 For example, a transient process (e.g., transient current generation) can be designed to return a Vmod voltage to zero after it is generated by a sensor inductive flyback current. A balancing process may take place during a period of charge accumulation (ie sampling). An accumulated charge on Cmod can be balanced by a switched capacitor current Ibal. A balanced constraint can be specified as follows: $${\text{Q}}_{\text{ph2\_max}}<{\text{V}}_{\text{DDA}}\cdot {\text{C}}_{\text{ref}}\cdot {\text{N}}_{\text{b\_min}}$$

Q _{ph2_.max} can be the maximum charge that can be produced in one sensor excitation cycle (e.g. Ph2). Nb_min may be the minimum amount of Fmod cycles required to achieve balance. The value Nb_min can thus define a maximum sensor excitation frequency F _{s_max} . This frequency is calculated using the following formula: $$f_{s\_max}=\frac{f_{mO\mathrm{i.e}}}{N_{b\_min}}$$

In a Ph3 period, both terminals of the sensor inductor can be coupled to ground after the Ph2 period. If the equalization period duration is longer than the sensor excitation phase duration: $$\frac{1}{f_s}>{\mathrm{<figure-callout\; id="0"\; label="T\; p\; H"\; filenames="DE102021132516A1\_0023.png,DE102021132516A1\_0031.png"\; state="\{\{state\}\}">T</figure-callout>}}_{pH}+{\mathrm{<figure-callout\; id="1"\; label="T\; p\; H"\; filenames="DE102021132516A1\_0035.png"\; state="\{\{state\}\}">T</figure-callout>}}_{pH}+{\mathrm{<figure-callout\; id="2"\; label="T\; p\; H"\; filenames="DE102021132516A1\_0028.png,DE102021132516A1\_0033.png"\; state="\{\{state\}\}">T</figure-callout>}}_{pH}+{\mathrm{<figure-callout\; id="3"\; label="T\; p\; H"\; filenames="DE102021132516A1\_0026.png"\; state="\{\{state\}\}">T</figure-callout>}}_{pH}$$

The inductance-to-code transfer function can be: $$DC=\frac{1}{{\displaystyle \sum {\mathrm{<figure-callout\; id="2"\; label="R\; i"\; filenames="DE102021132516A1\_0028.png,DE102021132516A1\_0033.png"\; state="\{\{state\}\}">R</figure-callout>}}_i{}^2\cdot C_{\mathrm{right}ef}\cdot N_b}}\cdot L_s\cdot \left(1-e^{-{\mathrm{<figure-callout\; id="2"\; label="T\; p\; H"\; filenames="DE102021132516A1\_0028.png,DE102021132516A1\_0033.png"\; state="\{\{state\}\}">T</figure-callout>}}_{pH}\cdot \frac{{\displaystyle \sum R_i}}{L_S}}\right)$$

It is noted that the above function demonstrates various advantages of a flyback sampling approach according to embodiments: conversion results, a digital code (DC) is proportional to the sensor inductance (Ls); Conversion results are time dependent on a sampling period (Tph2). It is also noted that a sensor resistance (Rs included in Ri) and Cref do not depend on a power supply voltage VDDA.

While the above conversion appears to be non-linear with respect to Ls, this non-linearity does not significantly affect a typical sampling operation. In many applications, the measured inductance fluctuations lie within a relatively narrow range. For example, many inductance sensing operations detect inductance variations of less than 20% (e.g., +-10%). In this range of inductance variation, the non-linearity has almost no effect. For example, if a Ph2 period is about three times the time constant, the approximation formula becomes: $$DC=\frac{1}{{\displaystyle \sum {\mathrm{<figure-callout\; id="2"\; label="R\; i"\; filenames="DE102021132516A1\_0028.png,DE102021132516A1\_0033.png"\; state="\{\{state\}\}">R</figure-callout>}}_i{}^2\cdot C_{\mathrm{right}ef}\cdot N_b}}\cdot L_s{\text{if <figure-callout id="2" label="t p H" filenames="DE102021132516A1\_0028.png,DE102021132516A1\_0033.png" state="{{state}}">t</figure-callout>}}_{pH}\approx 3\cdot \frac{L_s}{{\displaystyle \sum R_i}}$$

This transfer function is linear with respect to the inductance Ls. In this way, inductive flyback sensing devices according to embodiments can generate code values that vary linearly with changes in inductance. This is in sharp contrast to conventional approaches.

While embodiments may attempt to modulate an inductance-related voltage (Vmod) around a zero volt level, other embodiments may produce modulation voltages around other voltage levels. 6 shows such an embodiment.

6 FIG. 6 shows an inductance sensing device 600 according to another embodiment. The inductance sensing device 600 may include elements such as those shown in 1B that can work in a similar way.

The embodiment of 6 differs from 1B in that the modulator node 606 can be driven back to VDDA after a Vmod voltage lower than VDDA generated by a flyback current, and that a flyback section 106 can draw (ie, sink) a flyback sample current (Isen) from the modulator node, that SW9 can couple the modulator node 606 to VDDA, and that a non-inverting input of comparator 608 can be coupled to VDDA. Accordingly, a balancing section 604 may generate a balancing current (Ibal) that is a current source for the modulator node 606 .

7A until 7D FIG. 12 is a series of diagrams depicting sampling phases for inductive sampling according to other embodiments, including those in FIG 6 shown, show.

7A shows an excitation phase Ph0. Through the operation of one or more switches (e.g., SW3 and SW4), terminal B can be coupled to an excitation voltage VDDA. At the same time, terminal A can be coupled to ground.

7B shows an optional energy recovery phase (Ph1). Through the operation of switches (e.g., SW0 and SW1), terminal A can be coupled to VDDA while terminal B can be coupled to ground.

7C shows a charge accumulation phase Ph2. Through the operation of switches (e.g., SW0 and SW2), the B terminal can be coupled to generate a flyback current across the modulator capacitance (Cmod). Due to the flyback current (Isen), the charge can be discharged at Cmod. A resulting voltage on Cmod can be modulated to determine Ls.

7D shows an optional idle phase Ph3. By operating switches (e.g. SW0 and SW3), terminals A and B can be coupled to VDD.

wobei DC (Duty Cycle) ein durchschnittliches Tastverhältnis eines Bitstreamsignals ist.The embodiments of 1B and 6 may generate a switched capacitor balancing current (Ibal) through the operation of a balancing section (e.g., 104, 604). A compensation section may include four analog switches and an adjustable capacitance Cref. A capacitance Cref can be set with a digital code Ccode. Switches that couple nodes Ca and Cb to the power supply node (e.g., SW5, SW6, SW8) can be open-drain pull-up/pull-down drivers. A switch that couples node Cb to a modulator node (e.g., 106, 606) may be an analog switch with low switching injection current. Two-phase non-overlapping signals (Ph0_mod_fb, Ph1_mod_fb) can control Ibal. In some embodiments, an Fmod modulator clock frequency can determine this sequence. Furthermore, the sequence is modulated by a converter output bitstream signal (e.g. 112B, 612). An average current produced by a balanced subsection (e.g. 106, 606) can be given as: $$I_{bal}=\pm C_{\mathrm{right}ef}\cdot V_{\mathrm{i.e}\mathrm{i.e}a}\cdot {ƒ}_{mO\mathrm{i.e}}\cdot DC,$$

where DC (duty cycle) is an average duty cycle of a bitstream signal.

The formula above assumes that a modulator capacitance (Cmod) is sufficiently high that the voltage drop during charge transfer is negligible. When a modulator voltage (Vmod) is at a comparator threshold voltage (e.g. ground in 1B or VDDA in 6 ), the inductance conversion device 100B/600 can be considered to be in a balanced operating point.

For some sensor ranges and sensitivities, a transient current (Ibal) generated in response to a modulator output (bitstream) can provide a desired response. However, for some sensor ranges and/or sensitivities, it may be desirable to generate additional current to balance the return current (Isen) at the modulator node. 8th and 9 are schematic representations of such embodiments.

8th FIG. 8 shows an inductance sensing device 800 according to another embodiment. The scanning device 800 can include elements such as those in 1B that can work in a similar way. This includes a compensation section 804 having a reference capacitance Cref that can be set by a value Ccode. The embodiment of 8th differs from 1B in that an additional compensation section 817 can be included that can generate a compensation current Icomp that can be used to maintain a balanced state at the modulator node 806 .

A compensation section 817 may have the same general form as a compensation section 804 and may include analog switches SW12-SW15. A compensation section 817 may include (or be coupled to) a variable capacitance Ccomp at nodes Cc and Cd. A value of Ccomp can be specified with the value of Ccoder (where Ccoder is different from Ccode used at the compensation section 804). SW12 can be controlled by a Ph1_mod signal to couple Cc to VDDA. SW13 can be controlled by a signal Ph0_mod to couple Cc to ground. SW14 can be controlled by a Ph1_mod signal to couple Cd to ground and SW15 can be controlled by a Ph0_mode signal to couple Cd to modulator node 806 .

A compensation section 817 may operate in the same manner as a compensation section (e.g., 104, 604). The generation of the stream is not modulated by the bitstream 812, however. The average current that gives a balanced scheme is calculated by the following formula: $$I_{cOmp}=\pm C_{cOmp}\cdot V_{\mathrm{i.e}\mathrm{i.e}a}\cdot {ƒ}_{mO\mathrm{i.e}}$$

It should be understood that while the embodiment uses the Fmod clock frequency (shown as f _mod ) for the generation of Icomp, such an arrangement is not limiting. Any suitable switched capacitor timing can be used based on the capacitance Icomp, the desired Icomp, and the desired transient behavior.

9 FIG. 9 shows a scanning device 900 according to another embodiment. The scanning device 900 can include elements such as those in 6 include, which can work in a similar way. The embodiment 9 differs from 6 in that it may include a compensation section 917 that generates a compensation current Icomp. Compensation circuit 914 can operate in the same general manner as 8th , the generated switched capacitor reference current Icomp can feed the modulator node 906 to counteract the sink current Isen.

Embodiments such as those in 1B , 6 , 8th and 9 , have a single-ended configuration, generating a modulator voltage Vmod, which may differ from the static reference voltage (e.g., VDDA, ground). However, other embodiments may include pseudo-differential sampling. A pseudo-differential inductance-to-code converter according to some embodiments can be designed as a combination of two single-ended configurations as described above. Pseudo-differential inductance sensing can include eight phases of operation, Ph0 through Ph7. Ph0 and Ph4 can be inductor energy accumulation periods. Ph1 and Ph5 can be optional inductor energy recovery periods. Ph2 and Ph6 can be modulator node charge accumulation periods. Ph3 and Ph7 can be optional idle periods.

10A 10 is a schematic diagram of an inductive sensing device 1000A utilizing pseudo-differential sensing according to an embodiment. A device 1000A may include sections such as those in 1B , including a return section 1002, an equalization section 1004A, a modulator section 1005, a digital sequencer 1015, and feedback logic 1014.

A return section 1002 may differ from that in 1B in that it may include switches SW2A and SW2B that may couple the Rx pin of sensor cell 1016 to modulator nodes 1006A and 1006B, respectively. Furthermore, a retrace section 1002 may operate according to an eight-phase inductive sampling operation as mentioned above. The switch SW0 can be controlled by a signal Ph0/Ph5/Ph6/Ph7 to couple the first sensor node Tx to VDDA. Switch SW1 can be controlled by signals Ph0/Ph3/Ph5 to couple sensor node Rx to ground. Switch SW3 can be controlled by signals Ph1/Ph4/Ph7 to couple Rx to VDDA. Switch SW4 can be controlled by signals Ph1/Ph2/Ph3/Ph4 to couple Tx to ground. SW2A can be controlled by signal Ph2 to couple Rx to modulator node 1006A. SW2B can be controlled by signal Ph6 to couple Rx to modulator node 1006B.

A balance section 1004A may differ from that in 1B differ in that it may include analog switches SW5, SW7A, SW7B and SW8. SW5 can be controlled by a signal Ph1_mod to couple Ca to VDDA. SW8 can be controlled by a signal Ph0_mod to couple Ca to ground. SW7A can be controlled by a signal Ph0_mod_fb to couple Cb to modulator node 1006A. SW7B can be controlled by a signal Ph1_mod_fb to connect Cb to the to couple modulator node 1006B. A balancing section 1004A may generate a first balancing current Ibal_sn, which sinks current from the modulator node 1006A in Ph2 of a sampling operation, and may generate a second balancing current Ibal_sc, which sources current to the modulator node 1006B in Ph6 of a sampling operation. As in the above embodiments, such balance currents (lbal_sn, Ibal_sc) are dependent on the modulator 1012 output bitstream.

A modulator section 1005 may differ from that in 1B differ in that a first modulator node 1006A can be coupled to a non-inverting input of the comparator 1008 while a second modulator node 1006B can be coupled to an inverting input of the comparator 1008. The modulator node 1006A may have a first modulator capacitance CmodA. The modulator node 1006B may have a second modulator capacitance CmodB.

The digital sequencer 1015 can generate the various signals for controlling the device 1000 according to the eight-phase sampling sequence. Feedback logic 1014 may generate feedback signals Ph0_mod_fb and Ph1_mod_fb as described herein and equivalents.

In operation, the pseudo differential inductive sampling device 1000 may attempt to maintain a common mode voltage at inputs of the comparator 1008 at VDDA/2. Accordingly, embodiments may include initialization and/or equalization circuitry that precharges inputs of comparator 1008 to VDDA/2. Compensation section 1004 may be designed to maintain a differential voltage between modulator inputs VmodA and VmodB at zero volts.

10B 10 is a schematic diagram of an inductive sensing device 1000B utilizing pseudo-differential sensing according to another embodiment. A device 1000B may include elements such as those in 10A and such same elements can operate in the same general manner.

10B can differ from 10A differ in that a balancing section 1004B may utilize digital-to-analog current converters (iDACs) 1027sc and 1027sn to generate balancing currents. The 1027sc/sn iDACs are programmable to provide streams based on the DAC codes Icod_sc and Icode_sn, respectively. In the embodiment shown, iDAC 1027sn may be coupled to modulator node 1006A by operation of timing signal Ph0_mod_fb through SW7A to derive balancing current Ibal_sn from modulator node 1006A.

Operation of timing signal Ph1_mod_fb allows iDAC 1027sc to be coupled to modulator node 1006B through SW7B to inject balancing current Ibal_sc to modulator node 1006B.

It should be understood that in all of the embodiments disclosed herein, iDACs can be used to generate transient currents and/or reference currents instead of switched capacitor circuits.

11A until 11H represent a series of diagrams depicting sampling phases for inductive sampling according to a pseudo-differential embodiment, including the in 10A and 10B shown, show.

11A shows a first phase (Ph0), which may be a first excitation phase. In Ph0, operation of one or more switches (e.g., SW0, SW1) can couple terminal A to VDDA. At the same time, terminal B can be coupled to ground.

11B shows a second phase (Ph1), which can be an optional energy recovery phase. In Ph1, through the operation of switches (e.g., SW3 and SW4), terminal A can be coupled to ground while terminal B can be coupled to VDDA.

11C shows a third phase (Ph2), which may be a first charge accumulation phase. In Ph2, through the operation of switches (e.g., SW2A, SW4), the B terminal can be coupled to a first modulator capacitance (CmodA) and the A terminal can be coupled to ground to induce a flyback current from Ls. Charge can accumulate on CmodA due to flyback current (Isen_sc).

11D shows a fourth phase (Ph3), which can be an optional idle phase. In Ph3, operation of switches (e.g. SW1 and SW4) allows terminals A and B to be coupled to ground.

11E shows a fifth phase (Ph4), which may be a second phase of excitation. In Ph4, operation of one or more switches (e.g., SW3, SW4) can couple terminal B to VDDA and couple terminal A to ground to energize Ls.

11F shows a sixth phase (Ph5), which can be an optional energy recovery phase. In Ph5, through the operation of switches (e.g., SW0, SW1), terminal A can be coupled to VDDA while terminal B can be coupled to ground.

11G shows a seventh phase (Ph6), which may be a second charge accumulation phase. In Ph6, through the operation of switches (e.g., SW0, SW2B), the B terminal can be coupled to a second modulator capacitance (CmodB) and the A terminal can be coupled to VDDA to induce a flyback current from Ls. Current can be drawn from CmodB due to flyback current (Isen_sn).

11H shows an eighth phase (Ph7), which can be an optional idle phase. In Ph7, by operating switches (e.g. SW0, SW3), terminals A and B can be coupled to VDDA.

Regarding 12 12 is a timing chart for operations of devices like those in FIG 10A/B shown. The timing diagram shows: the different sampling phases Ph0, Ph2, Ph3, Ph4, Ph6, Ph7; an inductor voltage VLs; an inductor current ILs; a resulting first flyback current Isen_sc at a first modulator node; a resulting second flyback current Isen_sn at a second modulator node; a differential voltage across the first and second modulator nodes; and a resulting bitstream. It is noted that 12 shows operations that do not include optional energy recovery phases Ph1 and Ph5.

The different phases can be understood from the 11A until 11H .

In an embodiment like that in 10A/B For example, the accumulated charge on the modulator capacitances CmodA and CmodB can be balanced by the charge generated with the fly capacitor Cref in a balancing section (e.g., 1004A/B).

Q_{ph2_max} ist die maximale Ladung, die im Abtastzyklus Ph2 erzeugt werden kann. Q_{Ph6_max} ist die maximale Ladung, die im Abtastzyklus Ph6 erzeugt werden kann. N_{b_min} kann die erforderliche Minimummenge an Fmod-Zyklen sein, um einen Ausgleich zu erreichen. Ein Unterschied zwischen einer einendigen und einer pseudodifferentiellen Konfiguration lässt sich anhand der Werte für Qph2 und Qph6 nachvollziehen. Der Isen-Strom wechselt während dieser Phasen das Vorzeichen, weil ein durch einen Ausgleichsstrom (Ibal) verursachter Einstellbetrieb einen Modulationsknoten von VDDA/2 weg treibt. Insbesondere kann in Ph2 ein Einstellprozess dazu neigen, eine VmodA-Spannung hin zur Masse zu ziehen. In Ph6 kann ein Einstellprozess dazu neigen, VmodB hin zu VDDA zu treiben. Das bedeutet, dass sich Qph2 und Qph6 während der Ph2- und Ph6-Zeiträume abwechseln können. Diese Eigenschaft kann die Dauer der Ph2- und Ph6-Zeiträume einschränken, wie sich aus der Induktivität-zu-Code-Übertragungsfunktion ergibt, die wie folgt angegeben werden kann: $$D_x=\frac{3}{2\cdot R_s{}^2\cdot C_{ref}\cdot N_{b\_min}}\cdot \left(1-e^{-\frac{R_S}{L_S}\cdot T_{ph2}}\right)\cdot L_S-\frac{T_{ph2}}{2\cdot R_S\cdot C_{ref}\cdot N_{b\_min}}.$$

The equilibrium condition can be stated as follows: $${\text{Q}}_{\text{ph2\_max}}+{\text{Q}}_{\text{ph6\_max}}<2\cdot {\text{V}}_{\text{DDA}}\cdot {\text{C}}_{\text{ref}}\cdot {\text{N}}_{\text{b\_min}}$$

Q _{ph2_max} is the maximum charge that can be generated in sampling cycle Ph2. Q _{Ph6_max} is the maximum charge that can be generated in sampling cycle Ph6. N _{b_min} may be the required minimum amount of Fmod cycles to achieve balance. A difference between a single-ended and a pseudo-differential configuration can be understood from the values for Qph2 and Qph6. The Isen current changes sign during these phases because a settling operation caused by a transient current (Ibal) drives a modulation node away from VDDA/2. In particular, in Ph2, an adjustment process may tend to pull a VmodA voltage toward ground. In Ph6, an adjustment process may tend to drive VmodB towards VDDA. This means that Qph2 and Qph6 can alternate during the Ph2 and Ph6 periods. This property can limit the duration of the Ph2 and Ph6 periods as follows from the inductance-to-code transfer function, which can be given as: $$D_x=\frac{3}{2\cdot R_s{}^2\cdot C_{\mathrm{right}ef}\cdot N_{b\_min}}\cdot \left(1-e^{-\frac{R_S}{L_S}\cdot T_{pH2}}\right)\cdot L_S-\frac{{\mathrm{<figure-callout\; id="2"\; label="T\; p\; H"\; filenames="DE102021132516A1\_0028.png,DE102021132516A1\_0033.png"\; state="\{\{state\}\}">T</figure-callout>}}_{pH}}{2\cdot R_S\cdot C_{\mathrm{right}ef}\cdot N_{b\_min}}.$$

13 13 is a schematic diagram of an inductive scanning device 1300 according to another embodiment. A sampling device 1300 can employ differential sampling without the phase duration limitations mentioned above by using a capacitive divider 1320 . The scanner 1300 may include elements such as those in 10A and such same elements can operate in the same general manner.

A scanner 1300 may differ from that in 10A differ in that a flyback section 1302 may include a capacitance divider 1320 in place of switches SW0 and SW4. The capacitance divider 1320 may include a dividing capacitance Cd1 and a dividing resistor Rd1 arranged in series between VDDA and node Tx, and a dividing capacitance Cd2 and a dividing resistor Rd2 arranged in series between node Tx and ground.

14A until 14D represent a series of diagrams depicting sampling phases for inductive sampling according to a pseudo-differential embodiment, including the in 13 shown, show. By operating a voltage divider, a sensor node terminal A can be maintained at a voltage between VDDA and ground, in this case VDDA/2.

14A shows a first phase (Ph0), which may be a first excitation phase. In Ph0, operation of one or more switches (e.g., SW1) allows terminal B to be coupled to ground while terminal A is coupled to VDDA/2 to excite sensor inductor Ls.

14B shows a second phase (Ph1), which may be a first charge accumulation phase. In Ph1, the operation of switches (e.g., SW2A) allows the B terminal to be coupled to a first modulator capacitance (CmodA) while the A terminal remains at VDDA/2. This can induce a first flyback current with Ls. Charge can accumulate on CmodA due to flyback current (Isen_sc).

14C shows a third phase (Ph2), which may be a second excitation phase. In Ph0, operation of one or more switches (e.g., SW3) allows terminal B to be coupled to VDDA while terminal A remains at VDDA/2. This can excite the sensor inductance Ls.

14D shows a fourth phase (Ph3), which may be a second charge accumulation phase. In Ph3, the operation of switches (e.g., SW2B) allows the B terminal to be coupled to a second modulator capacitance (CmodB), while the A terminal remains at VDDA/2. This can induce a second flyback current with Ls opposite to that of Ph1. Charge can be drawn from CmodB due to the flyback current.

In some embodiments, an energy recovery period may be inserted between phases Ph0 and Ph1 and/or between phases Ph2 and Ph3.

Regarding 15 is a timing diagram for the operation of a device like that in 13 shown. The timing diagram shows: the different sampling phases Ph0-Ph3; an inductor voltage VLs; an inductor current ILs; a resulting first sampled current Isen_sc; a resulting second sampled current Isen_sn; a differential voltage across the modulation node; and a resulting bitstream.

The different phases are from the 14A until 14D apparent.

16A 16 is a schematic diagram of an inductive scanning device 1600A according to another embodiment. A sensing device 1600A may couple a sensor inductance across differential modulator nodes. The scanner 1600A may include elements such as those in 13 include, and such same elements can work in the same way.

A sensor device 1600A can differ from the 13 differ in that a flyback section 1602A may further include analog switches SW0, SW4, and may include SW2 and SW16 instead of SW2A and SW2B. SW0 can be controlled by signals Ph0/Ph5/Ph7 to couple node Tx to VDDA. SW4 can be controlled by signals Ph1/Ph3/Ph4 to couple node Tx to ground. SW2 can be controlled by signals Ph2/Ph6 to couple node Rx to modulator node 1606A. SW16 can be controlled by signals Ph2/Ph6 to couple Tx to modulator node 1606B. In one phase (ie, Ph2) of a sampling operation, an inductive sensor 1616 may be coupled across modulator nodes 1606A/B to induce a flyback current in one direction. In another phase (ie, Ph6) of a sensing operation, inductive sensor 1616 may couple across modulator nodes 1606A/B and induce a flyback current in the opposite direction.

16B 16 is a schematic diagram of an inductive scanning device 1600B according to another embodiment. A scanner 1600B can, in various configurations, include a sen couple inductance via differential modulator nodes. The scanner 1600B may include elements such as those in 16A and such same elements can operate in the same general manner.

A scanner 1600B may differ from the one shown in 16A differ in that a flyback section 1602B may include analog switches SW2A/B instead of SW2 and switches 16A/B instead of SW16. SW2A can be controlled by signal Ph2 to couple node Rx to modulator node 1606A. SW2B can be controlled by signal Ph6 to couple node Rx to modulator node 1606B. SW16A can be controlled by signal Ph6 to couple node Tx to modulator node 1606A. SW16B can be controlled by signal Ph2 to couple node Tx to modulator node 1606B. In a phase (ie, Ph2) of a sensing operation, an inductive sensor 1616 may be coupled in a first configuration across the modulator nodes 1606A/B such that a flyback current flows in a direction relative to the first and second modulator nodes 1606A/B. In another phase (ie, Ph6) of a sensing operation, an inductive sensor 1616 may be coupled in a second configuration across the modulator nodes 1606A/B such that a flyback current flows in an opposite direction with respect to the first and second modulator nodes 1606A/B.

17A until 17H FIG. 12 is a series of diagrams showing sampling phases for an inductive sampling operation according to an embodiment like that of FIG 16A demonstrate.

17A shows a first phase (Ph0), which may be a first excitation phase. In Ph0, through operation of one or more switches (e.g., SW0, SW1), terminal A can be coupled to VDDA and terminal B can be coupled to ground to energize Ls.

17B shows a second phase (Ph1), which can be an optional energy recovery phase. In Ph1, through the operation of switches (e.g., SW3, SW4), terminal A can be coupled to ground while terminal B can be coupled to VDDA.

17C shows a third phase (Ph2), which may be a first charge accumulation phase. In Ph2, through operation of switches (e.g., SW2, SW16), terminal B can be coupled to a first modulator capacitance (CmodA) and terminal A can be coupled to a second modulator capacitance (CmodB). This can induce a flyback current from Ls. Due to reverse current (Isen_sc), charge can accumulate on CmodA and discharge from CmodB.

17D shows a fourth phase (Ph3) which may be an optional idle time. In Ph2, operation of switches (e.g. SW1, SW4) allows terminals A and B to be coupled to ground.

17E shows a fifth phase (Ph4), which may be a second phase of excitation. In Ph4, operation of one or more switches (e.g., SW3, SW4) allows terminal A to be coupled to ground while terminal B may be coupled to VDD.

17F shows a sixth phase (Ph5), which can be an optional energy recovery phase. In Ph5, through the operation of switches (e.g., SW0, SW1), terminal A can be coupled to VDD while terminal B can be coupled to ground.

17G shows a seventh phase (Ph6), which may be a second charge accumulation phase. In Ph6, through operation of switches (e.g., SW2, SW16), terminal B can be coupled to a first modulator capacitance (CmodA) and terminal A can be coupled to a second modulator capacitance (CmodB). This can induce a reverse current from Ls to reverse that from Ph2. Due to the reverse current (Isen_sn), charge can accumulate on CmodB and discharge from CmodA.

17H shows an eighth phase (Ph7), which may be an optional idle time. In Ph7, by operating switches (e.g. SW0, SW3), terminals A and B can be coupled to VDDA.

A balanced condition can be achieved when a maximum transient current is higher than a maximum sense current.

17I until 17O FIG. 12 is a series of diagrams showing sampling phases for an inductive sampling operation according to an embodiment like that of FIG 16B demonstrate.

17I shows a first phase (Ph0), which may be a first excitation phase. In Ph0, through operation of one or more switches (e.g., SW0, SW1), terminal A can be coupled to VDDA and terminal B can be coupled to ground to energize Ls.

17y shows a second phase (Ph1), which can be an optional energy recovery phase. In Ph1, through the operation of switches (e.g., SW3, SW4), terminal A can be coupled to ground while terminal B can be coupled to VDDA.

17K shows a third phase (Ph2), which may be a first charge accumulation phase. In Ph2, through operation of switches (e.g., SW2A, SW16B), terminal B can be coupled to a first modulator capacitance (CmodA) and terminal A can be coupled to a second modulator capacitance (CmodB). This can induce a flyback current from Ls. Due to reverse current (Isen_sc), charge can accumulate on CmodA and discharge from CmodB.

17L shows a fourth phase (Ph3) which may be an optional idle time. In Ph2, operation of switches (e.g. SW1, SW4) allows terminals A and B to be coupled to ground.

17M shows a fifth phase (Ph4), which may be a second phase of excitation. In the embodiment shown, Ph4 may be identical to Ph0.

17N shows a sixth phase (Ph5), which can be an optional energy recovery phase. In the embodiment shown, Ph5 may be identical to Ph1.

17O shows a seventh phase (Ph6), which may be a second charge accumulation phase. In Ph6, through operation of switches (e.g., SW2B, SW16A), terminal A may be coupled to a second modulator capacitance (CmodB) and terminal B may be coupled to a first modulator capacitance (CmodA). This can induce a flyback current from Ls. Due to reverse current (Isen_sc), charge can accumulate on CmodA and discharge from CmodB.

17p shows a seventh phase (Ph6), which can be an optional idle time. In the embodiment shown, Ph6 may be identical to Ph3.

Designs with pseudo-differential sampling can include compensation sections for generating compensation currents, as are described for single-ended designs. Such an arrangement is in 18 shown.

18 18 is a schematic diagram of an inductive scanning device 1800 according to another embodiment. A scanner 1800 may include elements such as those in 16B and such same elements can operate in the same general manner.

18 differs from 16B in that it may include a compensation section 1817 . Compensation section 1817 may include switches SW17, SW18, SW19A, and SW19B. SW17 can be controlled by Ph1_mod to couple node Cc to VDDA. SW18 can be controlled by Ph0_mod to couple node Cc to ground. SW19A can be controlled by Ph0_mod to couple node Cd to the first modulator node 1606A. SW19B can be controlled by Ph1_mod to couple node Cd to the second modulator node 1606B. Through a capacitor switching action, a compensation section 1817 may generate a first compensation current Icomp_sc that sinks current from the modulator node 1806A and a second compensation current Icomp_sn that injects current into the second modulator node 1806B.

It is understood that a compensating section like that in 18 or an equivalent thereof may be included in any of the pseudo-differential sampling embodiments disclosed herein.

Embodiments may take any suitable circuit form, however, some embodiments may be parts of larger integrated circuit (IC) devices, such as systems-on-chips (SoCs). 19 Figure 12 is a block diagram of one such embodiment.

19 1930 is a block diagram of a system 1930 according to one embodiment. A system 1930 may include an IC device 1932 and one or more inductive sensor cells (two shown as 1916A, 1916B). IC device 1932 may be an inductive sensing device. In some versions For example, an IC device 1932 may be programmable and have configuration data configured into an inductive sensing device.

The IC device 1932 may include the analog interconnect 1934 , configurable analog switches 1938 , and a configurable analog circuit block 1940 in communication with each other via an analog bus system 1942 . The IC device 1932 may also include configurable digital blocks 1946 that may be coupled to configurable programmable analog switches 1938 and configurable analog circuit blocks 1940 by a digital bus system 1944 .

Analog interconnect 1934 may be coupled to external pins (one shown as 1907) and may comprise a matrix formed of programmable pins (a portion shown as 1936). Interconnections can be established within analog interconnect 1934 with analog configuration data 1952 . Configurable analog switches 1938 can include analog switches (one shown as SWx) that can be controlled by signals (PhX_mod_fb, PhX_mod, PhX) provided by a digital bus. The configurable analog circuit block 1940 may include various analog circuit blocks including one or more comparators and one or more programmable capacitors (and/or IDACs). One or more outputs (Vout) of the comparators can be provided to the digital bus system 1944. Programmable capacities can be programmed by cap codes via the 1944 digital bus system.

Configurable digital blocks 1946 may include digital circuitry configurable by digital configuration data 1954 to various arithmetic logic functions. Such various arithmetic logic functions may include feedback logic 1914, digital sequencers 1915, and FFs 1910 as described herein. Configurable digital blocks 1946 can also include a capacitor controller 1950 that can store and provide capacitance codes for programmable capacitances in the configurable analog circuit block 1940.

Analog configuration data 1952 and digital configuration data 1954 can configure device 1932 into an inductive sensing device by coupling together the various circuit components according to any of the embodiments disclosed herein or equivalents thereof.

In some embodiments, a system 1930 can sample the inductance of multiple sensor cells 1916A/B. If such sampling is not simultaneous, sampling circuits can be shared. For example, different sets of analog switches can be configured as retrace sections and coupled to each sensor cell 1916A/B. However, a set of analog switches can be configured into a balancing section that uses programmable capacitance. The programmable capacitance can be set to different values by capacitor codes to sample with each sensor cell 1916A/B. A series of analog switches can be similarly configured into a compensation section.

20 10 is a diagram of a system 2030 according to another embodiment. A system 2030 may include an inductive sensor 2016 and an IC device 2032 formed on a circuit board 2034 . The IC device 2032 may include an inductive sensing device 2000 according to any of the embodiments shown herein or an equivalent.

In some embodiments, the inductive sensor 2016 may be formed with circuit board traces. Inductive sensor 2016 may be coupled to IC device 2032 via circuit board traces 2036A, 2036B, and 2036C. The circuit board trace 2036C may include a resistor Rext. In some embodiments, circuit board traces 2036A, 2036B, and 2036C may have a three-point connection to scanner 2000, as shown in FIG 3 shown form. In some embodiments, multiple inductive sensors 2016 may be formed on circuit board 2034 and coupled to sensing device 2000 .

While the various devices and systems have disclosed a number of inductive sensing methods, other methods will now be described with reference to a number of flow charts.

21 2140 is a flow diagram of a method according to one embodiment. A method 2140 may include exciting a sensor inductance 2140-0. One such action can be pairing of terminals of an inductive sensor via a potential through the operation of an integrated circuit. A sensor inductance may be coupled to generate a flyback current at a capacitive modulator node 2140-2. Such an action may include coupling one terminal to the modulator node and the other terminal to a voltage that may induce the flyback current. In some embodiments, a flyback current may charge a modulator node. In some embodiments, a flyback current may discharge a modulator node. A method 2140 may sigma-delta modulate 2140-4 a voltage at the modulator node. Such an action may include quantizing a modulator voltage at the modulator node over time to generate a bitstream indicative of sensor inductance. In some embodiments, such quantization can be done through the operation of a comparator. However, the embodiments should not be considered limited to one-bit quantization.

22 FIG. 2240 is a flow chart of a method according to another embodiment. A method 2240 may include coupling a first node of a sensor inductance to an excitation voltage 2240-0. Such an action may include coupling a first node of a sensor inductor to one voltage while the other node is coupled to a different voltage. The coupling of a first node to the excitation voltage can be static or dynamic. After the sensor inductance is excited, a second node of the sensor inductance can be coupled to a modulator capacitance to generate a modulator voltage with a flyback current, 2240-2.

A method 2240 may also include generating a transient current, as opposed to the flyback current, at the modulator node in response to the modulator voltage 2240-4. One such action may include generating a transient current that reduces the modulator voltage during a sampling period, 2240-4. In some embodiments, a transient current can be generated with switched capacitor operation. Switched capacitor operation may include charging a reference capacitor with a voltage at a first node and then switching the voltage at the first node while the second node is coupled to the modulator capacitance. In some embodiments, a reference capacitor is programmable and the transient current can be programmed by adjusting the reference capacitor. In addition or as an alternative, a compensating current can be varied by switched-capacitor timing.

A method 2240 may include generating a pulse train (e.g., a bitstream or a pulse train generated from higher order quantization) from the modulator voltage 2240-6. In some embodiments, such an action may include applying the modulator voltage to a comparator and latching a comparator output according to a clock signal. In some embodiments, the transient current may be generated in response to switching signals modulated by the pulse train.

Digital codes can be generated from the pulse train representing the sensor inductance 2240-8. In some embodiments, such an action may include activating a counter with the pulse train. The counter values can be sampled and the counter reset at regular intervals. The stored counter values can represent the sensor inductance. Embodiments may also include one or more first or higher order digital filters and decimators.

23 FIG. 2340 is a flow diagram of a method 2340 for pseudo-differential inductance sensing, according to one embodiment. A method 2340 may include coupling a sensor inductance to an excitation voltage 2340-0. Such a coupling can be static or dynamic. After the sensor inductance is excited, a sensor inductance can be coupled to a first modulator capacitance to induce a first flyback current on a first modulator capacitance. The first direction return flow may have a first direction of flow.

A method 2340 may include recoupling a sensor inductance to an excitation voltage 2340-4. Such a coupling can be static or dynamic. Such pairing may be the same as or different from the pairing made in 2340-0. A sensor inductance may be coupled to a second modulator capacitance to induce a second flyback current across a second modulator capacitance, 2340-6. A second return current may flow in an opposite direction to the first direction.

A method 2340 may include generating a bitstream from a differential voltage developed across the first and second modulator capacitances 2340-8. Such an action can include quantization of the differential voltage over time according to any of the embodiments disclosed herein or equivalents.

24 FIG. 2440 is a flow diagram of a method 2440 for pseudo-differential sensing of a sensor inductance according to another embodiment. A method 2440 may include coupling a sensor inductance to an excitation voltage 2440-0. Such action may take the form of any of the actions disclosed herein or the equivalent thereof. After the sensor inductance is excited, nodes of the sensor inductance may be coupled to the first and second modulator capacitances to induce a first flyback current 2440-2. Such action may include coupling one node of the sensor inductance to a first modulator capacitance and another node of the sensor inductance to a second modulator capacitance. A resulting return current can charge a first modulator capacitance and discharge a second modulator capacitance.

A method 2440 may include coupling a sensor inductance to an excitation voltage 2440-4. Such an action may be the same as or different from action 2440-0. After the second excitation of the sensor inductance, nodes of the sensor inductance may be coupled to the first and second modulator capacitances to induce a second direction flyback current 2440-6. Such action may include coupling nodes of a sensor inductance to the first and second modulator capacitances to generate a flyback current capable of discharging a first modulator capacitance and charging a second modulator capacitance.

A method 2440 may include generating a bitstream from a differential voltage developed across the first and second modulator capacitances 2340-8. Such action may include any of the embodiments disclosed herein (such as those made with reference to 1A described) or equivalents.

According to embodiments, an inductance-to-code converter based on a flyback principle may be insensitive to clock frequencies, current sources, and supply and reference voltage fluctuations. Such a converter architecture can be more flexible than traditional approaches, as it allows adjustment of sampling frequency, resolution, and sensitivity over a wide range of sensor inductance.

Embodiments can provide inductive sensing solutions where sensitivity and resolution can be varied over a wide range. In some embodiments, this may include using balance currents and/or reference currents to maximize a modulator current produced for a given sensor inductance variation.

According to embodiments, an inductance sensing device may include a simple analog front end for inductance sensing using only analog switches and a comparator. According to embodiments, inductance-to-code conversions can be relatively linear, in contrast to conventional approaches that exhibit an inverse square relationship.

According to embodiments, a simple set of hardware (e.g., analog switches) can be used to implement multiple possible sampling modes (e.g., single-ended, capacitor divider, pseudo-differential) as well as multi-sampling (i.e., sampling the inductance of multiple sensors).

According to embodiments, an inductance sensor excitation frequency may be determined and may be selected by a user. This is in contrast to traditional approaches where sensor inductance can dictate an acceptable range of excitation frequencies. Furthermore, in some embodiments, a selected inductance sensor excitation frequency may be used for other sensors of a system, such as capacitive sensors.

According to embodiments, an inductance sensor system can operate regardless of any expected variations in supply voltage levels.

In embodiments with a pseudo-differential configuration, if the internal routing is done symmetrically, essentially all common mode noise at the comparator inputs can be rejected.

Embodiments can provide easy and accurate calibration. If a reference inductance value is known, an absolute value generated by the sampling system can be used to calibrate a conversion transfer function.

While embodiments disclose inductor excitation and flyback current generation based on a same clock (e.g., Fmod), alternative embodiments may employ different timing of such phases to optimize performance.

Embodiments may enable inductor sensing with lower power consumption than conventional approaches.

It should be understood that reference throughout this specification to "one embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention . It is therefore emphasized and should be understood that two or more references to "an embodiment" or "an alternative embodiment" in different parts of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments of the invention.

Also, in the foregoing description of example embodiments of the invention, it should be understood that in order to streamline the disclosure and to facilitate an understanding of one or more of the various inventive aspects, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof . However, this method of disclosure is not to be construed as reflecting an intention that the claims may require more features than are expressly recited in each claim. Rather, inventive aspects lie in less than all features of a single embodiment disclosed above. Thus, the claims that follow the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Claims (21)

A procedure that includes: in a first phase of a sensing operation, controlling at least a first switch to energize a sensor inductance; in a second phase of the scanning operation, which follows the first phase, Controlling at least a second switch to couple the sensor inductance to a first modulator capacitance to induce a first flyback current from the sensor inductance, the first flyback current producing a first modulator voltage across the first modulator capacitance, and in response to the first modulator voltage, controlling at least one third switch to generate a transient current flowing in the opposite direction to the flyback current at the first modulator node; repeating the at least first and second phases to generate a first modulator voltage across the first modulator capacitance; and converting at least the first modulator voltage to a digital value representing sensor inductance. procedure according to claim 1 wherein: controlling at least the first switch comprises electrically coupling a first terminal of the sensor inductance to a first power supply; and controlling at least the second switch comprises coupling a second terminal of the sensor inductance to the first modulator capacitance. procedure according to claim 1 , further comprising: in the second phase of the sampling operation, controlling at least a fourth switch to generate a compensation current on the first modulator capacitance that has the opposite direction to the flyback current. procedure according to claim 1 , further comprising: in the first phase of a sensing operation, electrically coupling a first terminal of the sensor inductance to a first supply node with at least the first switch; in the second phase of the sensing operation, electrically coupling a second terminal of the sensor inductance to the first modulator capacitance with at least the second switch; in a third phase of the sensing operation subsequent to the second phase, electrically coupling the second terminal of the sensor inductance to the first supply node; in a fourth phase of the sensing operation subsequent to the third phase, electrically coupling the second terminal of the sensor inductance to a second modulator capacitance to induce a second flyback current, the second flyback current producing a second modulator voltage across the second modulator capacitance; and repeating the at least first through fourth phases to produce a differential voltage between the first and second modulator capacitances; and converting the differential voltage to the digital value representing the sensor inductance. procedure according to claim 1 wherein: controlling at least the first switch comprises electrically coupling a second terminal of the sensor inductor to a first supply node through the first switch while a second node of the sensor inductor is coupled to a reference voltage; and controlling at least the second switch comprises coupling the second terminal of the sensor inductance to the first modulator capacitance. procedure according to claim 1 , further comprising: in the first phase of a sensing operation, a first terminal of the sensor inductance being coupled to a first supply node; in the second phase of the sensing operation, electrically coupling a second terminal of the sensor inductance to the first modulator capacitance with at least the second switch; in a third phase of the sensing operation following the second phase, exciting the sensor inductance a second time; in a fourth phase of the sensing operation subsequent to the third phase, electrically coupling the second terminal of the sensor inductance to a second modulator capacitance; repeating the at least first through fourth phases to create a differential voltage between the first and second modulator capacitances; and converting the differential voltage to the digital value representing the sensor inductance. procedure according to claim 1 , further comprising: in the first phase of a sensing operation, a first terminal of the sensor inductance being coupled to a first supply node; in the second phase of the sensing operation, electrically coupling a second terminal of the sensor inductor to the first modulator capacitance with at least the second switch, and electrically coupling the first terminal of the sensor inductor to a second modulator capacitance with at least a fourth switch; in a third phase of the sensing operation following the second phase, exciting the sensor inductance a second time; in a fourth phase of the sensing operation subsequent to the third phase, electrically coupling the second terminal of the sensor inductor to the second modulator capacitance with at least the second switch, and electrically coupling the first terminal of the sensor inductor to the first modulator capacitance with at least the fourth switch; repeating the at least first through fourth phases to create a differential voltage between the first and second modulator capacitances; and converting the differential voltage to the digital value representing the sensor inductance procedure according to claim 1 , further comprising: in the first phase of a sensing operation, a first terminal of the sensor inductance being coupled to a first supply node; in the second phase of the sensing operation, electrically coupling a second terminal of the sensor inductor to the first modulator capacitance with at least the second switch, and electrically coupling the first terminal of the sensor inductor to a second modulator capacitance with at least a fourth switch; in a third phase of the sensing operation following the second phase, exciting the sensor inductance a second time; in a fourth phase of the sampling operation following the third phase, electrically coupling the second terminal of the sensor inductance to the second modulator capacitance with min at least one fifth switch, and electrically coupling the first terminal of the sensor inductance to the first modulator capacitance with at least one sixth switch; repeating the at least first through fourth phases to create a differential voltage between the first and second modulator capacitances; and converting the differential voltage to the digital value representing the sensor inductance. A device that includes: a plurality of inputs/outputs (I/Os), including at least a first I/O configured for coupling to a first terminal of an inductive sensor and a second I/O configured for coupling to a second terminal of an inductive sensor is configured; various switches; a switch control circuit configured to: in a first phase of a sensing operation, operating at least a first switch to excite a sensor inductance of the first inductive sensor by activating a current path to the sensor inductance, in a second phase of the sensing operation subsequent to the first phase, operating at least a second a switch to couple the second I/O to a first modulator node and to induce a first flyback current from the sensor inductance producing at least a first modulator voltage at the first modulator node, and in response to the first modulator voltage, operating at least a third switch to generate a transient current that is subtracted from the first flyback current at the first modulator node; and an analog-to-digital conversion (ADC) circuit, comprising: a modulator circuit configured to generate a train of pulses in response to at least the first modulator voltage, and an encoder configured to encode the train of pulses into digital values representing sensor inductance. Device according to claim 9 , wherein: the I/Os, the switches, the first modulator node, the ADC circuitry, and the switch control circuitry are part of the same integrated circuit device. Device according to claim 9 wherein: the switch control circuit is configured to apply a balancing capacitance code to set a programmable balancing capacitance; wherein the transient current varies in response to the programmable transient capacitance. Device according to claim 9 , further comprising: the switch control circuit configured to, in a third phase of the sensing operation subsequent to the second phase, operate at least a fourth switch to energize the sensor inductance a second time in a fourth phase of the sensing operation subsequent to the third phase follows, operating at least a fifth switch to couple the second I/O to a second modulator node to generate a second retrace current at the second modulator node, the second retrace current flowing in a different direction than the first retrace current; and the modulator configured to generate the train of pulses in response to a differential voltage between the first modulator node and the second modulator node. Device according to claim 9 , further comprising: the switch control circuit configured to, in the second phase of the sampling operation, operate at least a fourth switch to couple the first I/O to a second modulator node, the first flyback current to the first modulator node and from the second modulator node flows, in a third phase of the sensing operation following the second phase, operating at least a fifth switch to excite the sensor inductance a second time, in a fourth phase of the sensing operation following the third phase, operating at least a sixth switches to couple the second I/O to the second modulator node, and operating at least a seventh switch to couple the first I/O to the first modulator node, and the modulator configured to generate the train of pulses in response to a differential voltage between the first modulator node and the second modulator node. Device according to claim 9 , wherein: the switch control circuit is configured to, in the second phase of the sampling operation, operate at least a fourth switch to generate a reference current that is subtracted from the first flyback current at the first modulator node, the reference current being independent of the first modulator voltage. Device according to Claim 14 , wherein: the control circuit is configured to apply a reference capacitance code to set a programmable reference capacitance; wherein the reference current varies in response to the programmable reference capacitance. A system that includes: a sensor having a sensor inductance, a first terminal and a second terminal; an inductive scanning device comprising: a plurality of inputs/outputs (I/Os) including a first I/O coupled to the first terminal and a second I/O coupled to the second terminal, a variety of switches, a switch control circuit configured to, in a first phase of a sensing operation, operate at least a first switch to excite the sensor inductance and in a second phase of the sensing operation subsequent to the first phase, operate at least a second switch to couple a second I/O to a first modulator node to induce a first flyback current from the sensor inductance that generates a first modulator voltage on the first modulator node; an analog-to-digital conversion (ADC) circuit, comprising: a modulator configured to generate a train of pulses in response to at least the first modulator voltage, and an encoder configured to encode the train of pulses into digital values representing sensor inductance. system according to Claim 16 wherein: the switch control circuit is configured to, in the first phase of a sampling operation, couple the first I/O to a first supply node with at least the first switch, and couple the second I/O to a second supply node with at least a third switch; wherein the first supply node is selected from the group consisting of: a high power supply node and a reference supply node having a voltage intermediate between the high and low power supply nodes. system according to Claim 16 wherein: the inductive sensing device comprises: the switch control circuit configured to, in a third phase of the sensing operation subsequent to the second phase, operate at least a third switch to excite the sensor inductance a second time and in a fourth phase of the sensing operation following the third phase, operating at least a fourth switch to couple the second I/O to a second modulator node to induce a second flyback current from the sensor inductor that produces a second modulator voltage on the second modulator node, wherein the second flyback current has a current flow opposite to that of the first flyback current with respect to the sensor inductance; and the modulator configured to generate the train of pulses in response to a differential voltage between the first and second modulator nodes. system according to Claim 16 , wherein: the inductive sampling device comprises: the control circuit configured to, in the second phase of the sampling operation, operate at least a third switch to couple the first I/O to a second modulator node, wherein the first flyback current from the second modulator node and flowing to the first modulator node, in a third phase of the sensing operation subsequent to the second phase, operating at least a fourth switch to energize the sensor inductance a second time and in a fourth phase of the sensing operation subsequent to the third phase follows, operating at least a fifth switch to couple the second I/O to the second modulator node, and operating at least a sixth switch to couple the first I/O to the first modulator node to induce a second flyback current from the sensor inductance having a current flow opposite to that of the first flyback current; and the modulator configured to generate the train of pulses in response to a differential voltage between the first and second modulator nodes. system according to Claim 16 , wherein: the control circuit is configured to, in the second phase of the sampling operation, in response to at least the first modulator voltage, operate at least a third switch to generate a transient current, wherein the transient current is subtracted from the first flyback current at the first modulator node. system according to Claim 16 , further comprising: a circuit board comprising circuit board traces comprising: a first conductive path between the first terminal and the first I/O, a second conductive path between the second terminal and the second I/O, and a third conductive path between the second terminal and the second I/O, the third conductive path having a greater resistance than the second conductive path.

Images