DE102019131460B3 - Delay control for time-of-flight measuring devices - Google Patents

Abstract

The invention relates to a device for generating a shutter control signal (SOD) for actuating an electronic shutter (SORX) of a light-sensitive sensor device. The device comprises first means (LSL, LD, PLD, LTX) for edge-affected light signal generation at a first point in time and a shutter control signal (SO) at a second point in time, second means (LFR) for edge detection with generation of a stop signal (STP) at a third point in time, a high-resolution time base (DLL) operated with a reference clock (RCLK), a time measuring device (TM) and a delay control (DC) for generating a start signal (STR) from the shutter control signal (SO) with an adjustable delay. The high-resolution time base (DLL) has a delay line output bus (DLO), the signal profiles of the lines (DLO [1] to DLO [n]) of the delay line output bus (DLO) representing the reference clock (RCLK) with different delays to one another. The time measuring device (TM) detects the logical content of the delay line output bus (DLO) as a function of the start signal (STR) and the stop signal (STP) and uses it to generate a memory register output value (SRV) that depends on the time delay between depends on the first point in time and the third point in time. The delay control (DC) generates the start signal (STR) from the shutter control signal (SO) as a function of the memory register output value (SRV) with a controllable delay, so that the time offset is controlled to zero. The shutter control signal (SOD) is dependent on the start signal (STR).

Description

Generic term

The invention is directed to an apparatus and a method for generating a delayed shutter control signal ( SOD ) for actuating an electronic lock of a light-sensitive measuring or sensor device.

General introduction and state of the art

Cameras based on the time-of-flight principle indirectly measure the transit time between the transmitted light pulse and the received light signal (see also 1 ).

A light source, for example an LED or a laser, sends a light pulse ( LP ) out. The light pulse ( LP ) has a temporal light pulse duration ( T _trig ).

The light pulse ( LP ) is reflected on an object and returns as a reflected light pulse ( RP ) back.

The reflected light pulse ( RP ) compared to the light pulse ( LP ) by a delay time ( T _d ) delayed and thus out of phase.

The reflected light pulse ( RP ) is received in a photo detector.

The photodetector can be activated by means of a first shutter signal ( SS1 ), which controls a first electronic shutter of the photodetector, can be switched to be light-sensitive and light-insensitive. Is the photodetector activated by the first shutter signal ( SS1 ) is switched to be light-sensitive, it collects the charge carriers generated by the reception and generation of the electron-hole pair as a first amount of charge ( Q1 ).

The photodetector can be activated by means of a second shutter signal ( SS2 ), which controls a second electronic shutter of the photodetector, can be switched to be light-sensitive and light-insensitive. Is the photodetector activated by the second shutter signal ( SS2 ) is switched to be light-sensitive, it collects the charge carriers generated by the reception and generation of the electron-hole pair as a second amount of charge ( Q2 ) temporally and / or spatially separate from the first charge quantity ( Q1 ).

Simultaneously with the light pulse ( LP ) (LED pulse, or as in 1 shown, laser pulse) is this first electronic shutter (English: Shutter) by means of the said first shutter signal ( SS1 ) for the duration corresponding to the temporal light pulse duration ( T _trig ) opened and the first charge ( Q1 ) generated and stored in a light-sensitive circuit of the photodetector. With the end of the light pulse ( LP ) after the expiry of the light pulse duration ( T _trig ) closes said first shutter signal ( SS1 ) also synchronously the first electronic shutter of the photodetector for the first amount of charge ( Q1 ) and the second electronic shutter of the photodetector for the second amount of charge ( Q2 ) is activated by means of the second shutter signal ( SS2 ) for the duration of the light pulse duration ( T _trig ) opened and after the said light pulse duration ( T _trig ) closed again.

Neben dem in 1 dargestellten Zeitschema sind weitere, im Prinzip ähnliche, Zeitschemata möglich, die hier nicht beansprucht werden.From the first amount of charge ( Q1 ) and the second amount of charge ( Q2 ) the travel time and thus the distance d can be calculated using the speed of light c using the formula given below. $$d=\frac{c}{2}{T}_{triG}\frac{Q2}{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="DE102019131460B3\_0003.png,DE102019131460B3\_0005.png"\; state="\{\{state\}\}">Q</figure-callout>}1+\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="DE102019131460B3\_0002.png"\; state="\{\{state\}\}">Q</figure-callout>}2}$$

In addition to the in 1 The time scheme shown, further, in principle similar, time schemes are possible, which are not claimed here.

The measurement of the distance is based on the time-synchronized opening of the first electronic shutter to detect the first amount of charge ( Q1 ) and the second electronic shutter to detect the second amount of charge ( Q2 ) and the emission of the light pulse ( LP ). If the first shutter signal is delayed ( SS1 ) and / or the second shutter signal ( SS2 ) and / or the real transmission of the Light pulse ( LP ), the measurement of the distance by the delay time is wrong. A delay time of 1 ns delay corresponds to a resulting distance error of approx. 15 cm.

The two publications are based on the prior art DE 10 2017 106 071 B3 and US 9,584,105 B1 emerged. From the DE 10 2017 106 071 B3 a method for improving methods and devices for time-of-flight measurement is known. In this described method, the delay between a light pulse and a shutter-on signal is measured. This delay is measured or readjusted via a slave delay chain.

The US 9,584,105 B1 describes an apparatus having a timer, an edge combiner and a masking circuit. The timer comprises a fine and coarse delay circuit which generates a finely delayed signal of the rising and falling edge from a reference timing signal. A combiner generates a timing signal from these finely delayed signals. A masking circuit generates masking signals for the rising and falling edges to control the generation of the rising and falling edges of the timing signal.

task

The proposal is therefore based on the object of creating a solution which does not have the above disadvantages of the prior art and has further advantages. The object to be achieved is therefore to specify a method and / or a device in which the delay times of the various stages have no effect.

This object is achieved by a device according to claim 1 and a method according to claim 2.

Solution of the task

The invention presented below describes a method for regulating and keeping constant the delay time between the light pulse ( LP ) and the electronic locks.

The invention is explained by way of example with reference to the figures.

Figure 2

2 shows the basic circuit of the clock generation of a time-of-flight camera.

In the example of the 2 solves the problem with just one electronic shutter ( SORX ) described. The problem can be solved in the same way for several electronic locks.

A central laser / shutter control logic ( LSL ) generates a light pulse control signal ( LO ) for the generation of a light pulse ( LP ) and the shutter control signal ( SO ) for controlling the electronic shutter ( SORX ). At the output of the central laser / shutter control logic ( LSL ) are the light pulse control signal ( LO ) and the shutter control signal ( SO ) generally still synchronous, as the central laser / shutter control logic ( LSL ) the light pulse control signal ( LO ) and the shutter control signal ( SO ) typically by means of a central clock ( ZCLK ) generated.

Typically, essential parts of the device are the 2 in an integrated circuit ( IC ) realized together.

The said integrated circuit ( IC ) typically includes a driver ( SD ) for the electronic shutter ( SORX ) and a driver ( LD ) for a power driver ( PLD ) of a lamp ( LTX ) to emit the light pulse ( LP ). A power driver ( PLD ) intended for a laser (or an LED), for example, since the electricity for the laser and / or the LED - i.e. the light source ( LTX ) - is generally a few amps or a few tens of amps, and is therefore no longer useful on an integrated circuit. In 2 are the system boundaries of the integrated circuit ( IC ) drawn in as an example.

Both the internal drivers ( LD , SD ) as well as the external performance driver ( PLD ) of the lamp ( LTX ) lead to undesirable delays ( T _lod , T _sod , T _ltx ), which are examined in more detail below and which falsify the distance measurement. In particular, these time delays ( T _lod , T _sod , T _ltx ) a strong temperature drift and lead to the fact that the distance image shifts with the temperature.

Figure 3

Essentially, the following time delays occur in a device according to the signal pattern of FIG 3 and the following table: Reference number meaning T _lod The time delay between the rising edge of the light pulse control signal ( LO ) and the rising edge of the delayed light pulse control signal (LOD); T _ltx The time delay between the rising edge of the light pulse control signal ( LO ) and the rising edge of the intensity of the light pulse (LP); T _sod The time delay between the rising edge of the shutter control signal ( SO ) and the rising edge of the delayed shutter control signal (SOD);

The resulting effective time delay ( T _e ) between the rising edge of the light pulse ( LP ) and the rising edge of the delayed shutter control signal ( SOD ) to control to almost 0 s, and to minimize the temperature drift, is the subject of this disclosure.

Figure 4

1. 1. eine hochauflösende Zeitbasis (DLL),
2. 2. eine Zeitmessung (TM),
3. 3. eine Lichtpulsflankenerkennung (LFR),
4. 4. eine Verzögerungsregelung (DC).

The control circuit of the proposed solution is shown in 4th simplified schematically and exemplarily shown. The control circuit of the 4th has four main components:

1. 1. a high-resolution time base ( DLL ),
2. 2. a timing ( TM ),
3. 3. a light pulse edge detection ( LFR ),
4. 4. a delay rule ( DC ).

The high-resolution time base (DLL)

As a time base ( DLL ) is a delay locked loop ( DLL ) with high resolution. The times to be measured are in the order of magnitude of approx. 20 ns. The required resolution is in the range of approx. 50 ps.

The time base ( DLL ) consists of a phase detector ( PD ), a charge pump ( CP ) (English: Charge-Pump), a loop filter ( LF ), a controller / buffer ( BDLL ) for buffering the loop filter signal and a delay line ( DL ).

The controller / buffer ( BDLL ) controls with the help of a DLL control signal ( DLCL ) depending on a loop filter output signal ( LFO ) of the loop filter ( LF ) the delay within the delay line ( DL ). The delay line ( DL ) is typically composed of individual delay elements, the respective delay of which is determined by the DLL control signal ( DLCL ) depends on the controller / buffer ( BDLL ) depending on the output signal of the phase detector ( PD ) is produced. Typically the DLL control signal ( DLCL ) a voltage ready from which the delay in the delay line ( DL ) overall then depends. The output of the delay line ( DL ) is the delayed clock ( DCLK ) to the phase detector ( PD ) for comparison with the reference clock ( RCLK ) goes.

Circuit concepts for delay-locked loops with sub-gate delay resolutions have been extensively described in the literature (e.g. Stefan Henzler, Time-to-Digital Converters, Springer-Verlag). Furthermore, a delay-locked loop still requires detection circuits for recognizing the so-called “false locking”, which are not shown here. For example, if you take a reference clock ( RCLK ) from 40 MHz and if you want to achieve a resolution of 50 ps, for example, then there would be 500 outputs of the chain of delay elements in the delay line ( DL ) that the multiplexer must select.

One implementation possibility for achieving a sub-gate delay resolution of this selection process is the so-called “passive interpolation” (not the subject of the invention).

A circuit example for "passive interpolation" is shown 5 (see also the literature mentioned).

The individual resistance taps (here 5 as an example) make it possible to achieve a much finer time resolution than would be possible through the running time of the delay cell alone.

Timekeeping (TM)

The time measurement in the time measurement block ( TM ) is done by a memory register ( SR ) with a start-stop function via a start signal ( STR ) and a stop signal ( STP ).

The shutter control signal ( SO ) the time measurement starts as soon as the light pulse ( LP ) through the lamp ( LTX ) is sent out. The stop signal ( STP ) the time measurement in the block time measurement ( TM ) completed. The output of the storage register ( SR ) is a kind of thermometer code and the sum of the logical "1" signals is a measure of the time difference between the arrival of the edge of the start signal ( STR ) and the arrival of the edge of the stop signal ( STP ). Instead of edge control, level control is also possible at this point, but this is less good.

With the arrival of the stop signal ( STP ) takes over the memory register ( SR ) the vector of binary numbers from the delay line ( DL ). Each output of a delay element of the delay line ( DL ) one line of a delay line output bus ( DLO ), which here in the example of 4 n Lines [1 to n] ( OT1 to OTn ) includes. The logical contents of the delay line output bus ( DLO ) typically represent different delays of the reference clock ( RCLK ) or one of the reference clock ( RCLK ) dependent signal. The logical content of this delay line output bus ( DLO ) also represents the vector that is defined by the storage register ( SR ) is accepted.

An example of the storage register ( SR ) shows 7th .

An adder ( ADD ) preferably adds up the number of "1" values in the binary memory register output vector ( BSRV ) and thus generates a memory register output value ( SRV ).

Delay control (DC)

In the delay regulation ( DC ) first subtracts a second adder ( A2 ) from the memory register output value ( SRV ) an offset value, also known as leakage value ( LK ) called. Typically, this leakage value ( LK ) set as a register value via a data bus using software. A subsequent integrator ( INT ), for example an up / down counter, integrates the result value of this subtraction of the leakage value ( LK ) from the memory register output value ( SRV ) over time. A digital-to-analog converter ( THERE ) converts the integration result of the integration of the result value by the integrator ( INT ) into a digital-to-analog converter output signal and feeds this digital-to-analog converter output signal to a controller ( CTR ) to. The regulator ( CTR ) controls with the help of a shutter control signal control signal ( SODC ) the time delay of a shutter control signal delay unit ( DLS ). The shutter control signal delay unit ( DLS ) generated from the shutter control signal ( SO ) a delayed shutter control signal ( SOD ). The output stage of the shutter control signal delay unit ( DLS ) is preferably designed in terms of driver strength and speed in such a way that the electronic shutter ( SORX ) (in 2 ) can control.

Light pulse edge detection (LFR)

The central laser / shutter control logic ( LSL ), as in the description of the 2 mentioned the light pulse control signal ( LO ) and the shutter control signal ( SO ). The shutter control signal ( SO ) is again the already mentioned input signal of the shutter control signal delay unit ( DLS ). The driver ( LD ) for the power driver ( PLD ) of the lamp ( LTX ) generated from the light pulse control signal ( LO ) a delayed light pulse control signal ( LOD ) for the power driver ( PLD ) of the lamp ( LTX ). The lamp ( LTX ) sets the signal in the light pulse ( LP ), whose intensity edge is determined by a light pulse edge detection ( LFR ) is detected and into the said stop signal ( STP ) is converted.

Figure 5

5 (see also the literature mentioned) shows an unclaimed circuit example for “passive interpolation”. It is a differential delay unit with passive interpolation via the typically similar resistors, which are preferably designed to match within an integrated circuit. The delay in the differential amplifier depends on the DLL control signal ( DLCL ) from.

In the example of the 5 the signals are designed differentially. A non-differential signal routing is known from the literature and is assumed here.

By repeatedly chaining the two inputs of a subsequent delay unit ( DVZ ) of this type with the corresponding outputs of a respective preceding delay unit ( DVZ ) of this type arises from several delay units ( DVZ ) the delay line ( DL ).

In the example of the 5 assigns the delay unit ( DVZ ) exemplary four delayed output signals ( S1 to S4 ) on. The second delayed output signal ( S2 ) compared to the first delayed output signal ( S1 ) delayed and the third delayed output signal ( S3 ) is opposite to the second delayed output signal ( S2 ) delayed and the fourth delayed output signal ( S4 ) is opposite to the third delayed output signal ( S3 ) delayed. The delayed output signals ( S1 to S4 ) of the several, for example m, delay units (DVZ1 to DVZm) [not shown in the figures] form the vector of binary numbers from the delay line ( DL ) that the storage register ( SR ) with the arrival of the stop signal ( STP ) takes over.

By using the series connection of the individual, typically identical resistors and setting the granularity of the resistor cascade, the time resolution can be designed to a certain extent in accordance with the requirements.

Figure 6

6th shows an exemplary delay line with exemplary five delay elements accordingly 5 . Each of the five delay elements, for example, has four delayed outputs ( S1 to S4 ), so that 20 delayed outputs are shown here as an example, the delays of which are preferably based on the potential of the DLL control line ( DLCL ) depend. The total delay between the reference clock ( RCLK ) and the delayed clock ( DCLK ) also depends on the potential of the DLL control line ( DLCL ) from.

Figure 7

7th shows an example of the memory register ( SR ) in cooperation with the delay unit ( DVZ ) of the 5 . The exemplary four outputs ( S1 , S2 , S3 , S4 ) the delay unit ( DVZ ) are each with the clock input ( CLK ) a first, the respective output of the four outputs ( S1 , S2 , S3 , S4 ) associated first flip-flops. Thus, these clock inputs are controlled by a differently delayed reference clock or a differently delayed signal that depends on the reference clock. In the example of the 7th are four first fip-flops ( FFla , FF2a , FF3a , FF4a ) with its clock input ( CLK ) with a respective output ( S1 , S2 , S3 , S4 ) the delay unit ( DVZ ) connected. The data inputs ( D. ) these four first flip-flops ( FFla , FF2a , FF3a , FF4a ) are with the stop signal ( STP ) connected.

The measuring process now runs in such a way that the central laser / shutter control logic ( LSL ) typically the light pulse control signal ( LO ) and the shutter control signal ( SO ) generated. The light pulse control signal ( LO ) leads, as described above, to the emission of a light pulse ( LP ) through the lamp ( LTX ). The edge of this light pulse ( LP ) is detected by the light pulse edge detection ( LFR ) recognized by their detectors when they arrive and included in the stop signal ( STP ) converted.

The shutter control signal ( SO ) is controlled by the shutter control signal delay unit ( DLS ) in the start signal ( STR ) converted. The combination of the start signal (SRT) and the stop signal ( STP ) to the combined start-stop signal ( STRSTP ), for example through an EXOR link. In the example of the 4th is the start signal ( STR ) equal to the delayed shutter control signal ( SOD ). The reference clock ( RCLK ) is entered from the left into the input of the first delay unit ( DVZ ) differential fed in and then passes through the cascade of the delay units connected in series of the delay line ( DL ). Due to the delay in the delay units, the first delayed output signal of the delay unit ( DVZ ), then the second delayed output signal of the delay unit ( DVZ ) and so on up to the nth delayed output signal of the delay unit ( DVZ ) in a fixed phase relationship to the reference clock ( RCLK ) or actively delayed a signal derived from this. This causes the first flip-flop to scan first ( FF1a ) of the first memory register bit of the memory register ( SR ) the combined start-stop signal ( STRSTP ), which is generated, for example, by an EXOR link from the start signal ( STR ) and the stop signal ( STP ) can be obtained. Then the first flip-flop (FF12a) of the second memory register bit of the memory register ( SR ) the start-stop signal ( STRSTP ) from and so on, until finally the first flip-flop (FFna) of the nth memory register bit of the memory register ( SR ) the start-stop signal ( STRSTP ) scans. For example, if the logic is set up so that the start-stop signal ( STRSTP ) with the arrival of the light pulse ( LP ) changes from logical 1 to logical 0, the outputs of the first flip-flops change ( FFla , FF2a , FF3a , FF4a ), which this sampling before the change of state of the stop signal ( STP ) have made the condition. This means that an edge appears at the respective flip-flop output. The second flip-flop ( FF1b , FF2b , FF3b , FF4b ) at his data input ( D. ) attached exemplary logical 1. In contrast to this, the outputs of the first flip-flops change in the same case ( FFla , FF2a , FF3a , FF4a ), which this sampling after the change of state of the stop signal ( STP ), the logic state does not, but remains in its reset value 0.This means that at the respective flip-flop output ( Q ) now no flank. Thus, in contrast to the previously mentioned flip-flops, the second flip-flop following these flip-flops takes over ( FF1b , FF2b , FF3b , FF4b ) at his data input ( D. ) attached exemplary logical 1 not.

The time period T corresponds to the interval between the point in time of the change in state of the start signal ( STR ) and the time of the change of state of the stop signal ( STP ). During the period T in which the start signal ( STR ) is at a logic value of 1, the first flip-flops toggle the logic value 1. This is stored in the second flip-flops (see also the literature cited). In preparation for a new measurement, the flip-flops may be reset after the measurement.

For e.g. 500 outputs, 500 x 2 flip-flops are required. Each logical 1 in the 500 chain corresponds to an approximately equal delta time duration of e.g. 50 ps.

The adder ( ADD ) determines the number of lines DLO [1] to DLO [n] of the delay line output bus ( DLO ), which have a logical value of 1. To do this, he prefers to add the 1 values to a number. It thus supplies the memory register output value ( SRV ) as n-bit code.

Common circuit concepts for time measurement require that the start signal ( STR ) before the stop signal ( STP ) lies.

Light pulse edge detection ( LFR )

The shutter signal is usually already available internally as a digital signal and therefore does not need any additional edge detection. For the amplitude-modulated signal of the lamp ( LTX ) but a circuit for the detection of the switch-on torque is required. In 4th was the light pulse edge detection ( LFR ) with a fast photodiode ( APD ), a transimpedance amplifier ( TV ) and a comparator ( CMP ) realized. The photodiode ( APD ) is placed near the lamp ( LTX ), preferably the laser / LED, places and supplies power as soon as the lamp ( LTX ) sends the light pulse. The transimpedance amplifier ( TV ) and the comparator ( CMP ) set the light signal to the stop signal ( STP ) around.

The delay of the transimpedance amplifier ( TV ) and the comparator ( CMP ) must be significantly smaller than the delay of the power driver ( PLD ) of the lamp ( LTX ) and the delay of the driver ( LD ) for the power driver ( PLD ) of the lamp ( LTX ) in total. Other concepts for edge detection are possible, e.g. an inductive coupling to detect the current flow in the lamp ( LTX ) to detect the timing of the onset of the current flow.

Delay control ( DC )

The actual delay controller consists of an integrator ( INT ), a digital-to-analog converter ( THERE ), a controller ( CTR ) and a shutter control signal delay unit ( DLS ) between the central laser / shutter control logic ( LSL ) and the electronic shutter ( SORX ) and with the shutter control signal ( SO ) of the controller ( CRT ) is controlled.

The regulator ( CTR ) controls the delay of this shutter control signal delay unit ( DLS ) in such a way as to avoid the delay of the delay of the power driver ( PLD ) of the lamp ( LTX ) and the delay of the driver ( LD ) for the power driver ( PLD ) of the lamp ( LTX ) and the delay of the lamp ( LTX ) corresponds in total.

A second adder ( A2 ) subtracts the leakage value ( LK ) from the memory register output value ( SRV ). The integrator ( INT ) sums up the signal of the time measurement obtained in this way cumulatively over time and generates it with the help of the subsequent digital-to-analog converter ( THERE ) a control voltage that regulates the difference between the time of the change in status of the start signal (start time) and the time of the change in status of the stop signal (stop time) to zero.

Since the time measurement can only recognize positive times (the stop time is always after the start time) a small leakage signal in the form of the said leakage value ( LK ) required to use the controller ( CRT ) close to the optimal value.

The phase difference between the cycle of the signal control of the light source ( LTX ) and the timing of the delayed shutter control signal ( SOD ) is thus regulated to almost zero.

Figure 8

8th shows the settling of the control.

The small, triangular fluctuation after settling is caused by the leakage mentioned. The fluctuation is not important in practice, since a 3-D image requires a large number of light pulses and this fluctuation is averaged out.

Short version:

The subject of the invention is the description of a digital, integrating control for the synchronization of the delayed shutter control signal ( SOD ) with the real light pulse ( LP ), which is actually from the lamp ( LTX ) is sent out.

This regulation minimizes the delay between the light pulse emission by the light source ( LTX ), e.g. a laser, and the delayed shutter control signal ( SOD ) of the electronic shutter ( SORX ) and thus minimizes manufacturing and temperature influences in particular.

• - Zeitbasis, bestehend aus einer hochauflösenden Delay-Locked-Loop (DLL)
• - Zeitmessung (TM) (Start-Stop Erkennung)
• - Lichtpulsflankenerkennung (LFR) zur Bestimmung des Einschaltmoments des Lichtpulses (LP)
• - digitale Verzögerungsregelung (DC)

The control consists of the following components:

• - Time base, consisting of a high-resolution delay-locked loop ( DLL )
• - timing ( TM ) (Start-stop detection)
• - light pulse edge detection ( LFR ) to determine the switch-on moment of the light pulse ( LP )
• - digital delay control ( DC )

The control signal for the delay line ( DL ) in the shutter line is stored digitally. The entire control loop does not need to be switched on all the time, which significantly reduces power consumption.

The delay of the light pulse edge detection ( LFR ) is not covered by the regulation. It is therefore essential that these circuit components are fast compared to the total time delay from the delay of the power driver ( PLD ) of the lamp ( LTX ) and the delay of the driver ( LD ) for the power driver ( PLD ) of the lamp ( LTX ) and the delay of the lamp ( LTX ) are themselves. However, an LED or a laser when used as a light source ( LTX ) even a switch-on time in the range of nano seconds, which meets the requirements for light pulse edge detection ( LFR ) reduced.

Features of the invention

The invention relates to a device for generating a delayed shutter control signal ( SOD ) to operate an electronic lock ( SORX ) a light-sensitive measuring or sensor device. It includes first funds ( LSL , LD , PLD , LTX ) for generating an amplitude-modulated light signal and second means ( LFR ) for edge detection in the amplitude-modulated light signal. It also includes a high-resolution time base ( DLL ), which with a reference clock ( RCLK ) is operated, a time measuring device ( TM ) and a delay rule ( DC ). The first means ( LSL , LD , PLD , LTX ) are intended and suitable for the amplitude-modulated light signal, in particular a light pulse ( LP ), with a time characteristic, in particular an edge, to be generated at a first point in time and with a fixed time offset, based on the first point in time, at a second point in time to generate a shutter control signal SO ), whereby the fixed time offset can also be 0 s. The second means ( LFR ) are intended and suitable to detect the said temporal feature, in particular an edge, of the amplitude-modulated light signal at a third point in time and to generate a stop signal ( STP ) to create. The delay regulation ( DC ) generated from the shutter control signal ( SO ) with an adjustable delay a start signal ( STR ). The high-resolution time base ( DLL ) is with a reference clock ( RCLK ) operated. The high-resolution time base ( DLL ) has a delay line output bus ( DLO ) on. The waveforms of the lines (DLO [1] to DLO [n]) of the delay line output bus ( DLO ) at least temporarily provide the reference clock ( RCLK ) or a dependent signal with different delays to each other. The time measuring device ( TM ) recorded depending on the start signal ( STR ) and the stop signal ( STP ) the logical content of the delay line output bus ( DLO ) and uses it to generate a memory register output value ( SRV ), which depends on the time lag between the first point in time and the third point in time. The delay regulation ( DC ) generated from the shutter control signal ( SO ) the start signal ( STR ) in such a way that it depends on the memory register output value ( SRV ) and that the time offset between the second point in time and the third point in time is reduced in terms of amount and is regulated to zero except for control errors and system noise. The shutter control signal ( SOD ) depends on the start signal ( STR ) from or is equal to the start signal ( STR ).

1. 1. Erzeugen eines amplitudenmodulierten Lichtsignals, insbesondere eines Lichtpulses (LP), mit einem zeitlichen Merkmal, insbesondere einer Flanke, zu einem ersten Zeitpunkt;
2. 2. Erzeugen eines Shutter-Steuersignals (SO) zu einem zweiten Zeitpunkt und mit einem festen Zeitversatz bezogen auf den ersten Zeitpunkt, wobei der feste Zeitversatz auch 0 s sein kann;
3. 3. Detektieren des besagten zeitlichen Merkmals, insbesondere einer Flanke, des amplitudenmodulierten Lichtsignals zu einem dritten Zeitpunkt und Erzeugen eines Stop-Signals (STP) in einem festen Zeitbezug zu diesem dritten Zeitpunkt;
4. 4. Erzeugen eines Start-Signals (STR) aus dem Shutter-Steuersignal (SO) mit einer regelbaren Verzögerung;
5. 5. zumindest zeitweises Erzeugen der Signalverläufe der Leitungen (DLO[1] bis DLO[n]) eines Verzögerungsleitungsausgangsbusses (DLO) auf Basis eines Referenztakts (RCLK) oder eines aus einem Referenztakt (RCLK) abgeleiteten Signals mittels unterschiedlicher Verzögerungen des Referenztakts (RCLK) oder des aus diesem Referenztakt (RCLK) abgeleiteten Signals zu den Signalverläufen der Leitungen (DLO[1] bis DLO[n]) eines Verzögerungsleitungsausgangsbusses (DLO);
6. 6. Erfassen des logischen Inhalts des Verzögerungsleitungsausgangsbusses (DLO) in Abhängigkeit von dem Start-Signal (STR) und dem Stop-Signal (STP) und Erzeugung eines Speicherregisterausgangswerts (SRV) in Abhängigkeit von diesem logischen Inhalt, der von der zeitlichen Verzögerung zwischen dem ersten Zeitpunkt und dem dritten Zeitpunkt abhängt und
7. 7. Erzeugen des Start-Signals STR) aus dem Shutter-Steuersignal (SO) mit einer regelbaren Verzögerung in der Art,
   1. a. dass das Start-Signal (STR) von dem Speicherregisterausgangswert (SRV) abhängt und
   2. b. dass der Zeitversatz zwischen dem zweiten Zeitpunkt und dem dritten Zeitpunkt betragsmäßig vermindert und bis auf Regelfehler und Systemrauschen zu Null geregelt wird.

Furthermore, the invention comprises a method for generating a delayed shutter control signal ( SOD ) to operate an electronic lock ( SORX ) a light-sensitive measuring or sensor device. It includes the steps:

1. 1. Generation of an amplitude-modulated light signal, in particular a light pulse ( LP ), with a time feature, in particular an edge, at a first point in time;
2. 2. Generation of a shutter control signal ( SO ) at a second point in time and with a fixed time offset relative to the first point in time, wherein the fixed time offset can also be 0 s;
3. 3. Detecting the said temporal feature, in particular an edge, of the amplitude-modulated light signal at a third point in time and generating a stop signal ( STP ) in a fixed time reference to this third point in time;
4. 4. Generation of a start signal ( STR ) from the shutter control signal ( SO ) with an adjustable delay;
5. 5. at least temporarily generating the signal curves of the lines (DLO [1] to DLO [n]) of a delay line output bus ( DLO ) based on a reference clock ( RCLK ) or one from a reference clock ( RCLK ) derived signal by means of different delays of the reference clock ( RCLK ) or from this reference cycle ( RCLK ) derived signal to the signal courses of the lines (DLO [1] to DLO [n]) of a delay line output bus ( DLO );
6. 6. Acquiring the logical content of the delay line output bus ( DLO ) depending on the start signal ( STR ) and the stop signal ( STP ) and generation of a memory register output value ( SRV ) as a function of this logical content, which depends on the time delay between the first point in time and the third point in time and
7. 7. Generation of the start signal STR ) from the shutter control signal ( SO ) with an adjustable delay such as
   1. a. that the start signal ( STR ) from the memory register output value ( SRV ) depends and
   2. b. that the time offset between the second point in time and the third point in time is reduced in terms of amount and is regulated to zero except for control errors and system noise.

advantage

Such a device and method for generating a delayed shutter control signal ( SOD ) to operate an electronic lock ( SORX ) a light-sensitive measuring or sensor device enable an improved temporal resolution. The advantages are not limited to this.

List of reference symbols

ADD

Adder;

APD

Photodiode;

A2

second adder;

BDLL

Controller / buffer;

BSRV

Memory register output vector;

CLK

respective clock input of the flip-flops ( FFla , FF1b , FF2a , FF2b , FF3a , FF3b , FF4a , FF4b );

CP

Charge pump;

CMP

Comparator;

CTR

Regulator;

D.

respective data input of the flip-flops ( FFla , FF1b , FF2a , FF2b , FF3a , FF3b , FF4a , FF4b );

THERE

Digital-to-analog converter;

DC

Delay control;

DCLK

delayed clock;

DL

Delay line;

DLCL

DLL control signal;

DLL

Delay-locked loop, which is used as a high-resolution time base;

DLO

Delay line output bus;

DLS

Shutter control signal delay unit;

DVZ

Delay unit. In the example of the 5 it is a differential delay unit. Typically, the concatenation of several such differential delay units results in the delay line ( DL ). A short delay line can possibly consist of a delay unit;

FF1a

first flip-flop ( FF1a ) of the first memory register bit of the memory register ( SR );

FF1b

second flip-flop ( FF1b ) of the first memory register bit of the memory register ( SR );

FF2a

first flip-flop ( FF2a ) of the second memory register bit of the memory register ( SR );

FF2b

second flip-flop ( FF2b ) of the second memory register bit of the memory register ( SR );

FF3a

first flip-flop ( FF3a ) of the third memory register bit of the memory register ( SR );

FF3b

second flip-flop ( FF3b ) of the third memory register bit of the memory register ( SR );

FF4a

first flip-flop ( FF4a ) of the fourth memory register bit of the memory register ( SR );

FF4b

second flip-flop ( FF4b ) of the fourth memory register bit of the memory register ( SR );

IC

integrated circuit;

INT

Integrator;

LD

Driver ( LD ) for the power driver ( PLD ) of the lamp ( LTX );

LF

Loop filter;

LFR

Light pulse edge detection;

LFO

Loop filter output signal;

LK

Leakage value. The leakage value is a fixed value or a value that can be set using a register, for example, which is used as an offset value within the delay control ( DC ) is used.

LO

Light pulse control signal;

LOD

delayed light pulse control signal;

LP

Light pulse;

LSL

central laser / shutter control logic;

LTX

Light sources (e.g. an LED or a laser);

OT1

first line DLO [1] of the delay line output bus ( DLO ), which is the output of the memory register ( SR ) is;

OT2

second line DLO [2] of the delay line output bus ( DLO ), which is the output of the memory register ( SR ) is;

OT3

third line DLO [3] of the delay line output bus ( DLO ), which is the output of the memory register ( SR ) is;

OT4

fourth line DLO [4] of the delay line output bus ( DLO ), which is the output of the memory register ( SR ) is;

OTn

nth line DLO [n] of the delay line output bus ( DLO ), which is the output of the memory register ( SR ) is;

PD

Phase detector;

PLD

Performance driver ( PLD ) of the lamp ( LTX );

Q

respective data output of the flip-flops ( FFla , FF1b , FF2a , FF2b , FF3a , FF3b , FF4a , FF4b );

Q1

first amount of charge generated in the photodetector;

Q2

second amount of charge generated in the photodetector;

RCLK

Reference clock;

RP

reflected light pulse;

S1

first delayed output signal ( S1 ) the delay unit ( DVZ );

S2

second delayed output signal ( S2 ) the delay unit ( DVZ );

S3

third delayed output signal ( S3 ) the delay unit ( DVZ );

S4

fourth delayed output signal ( S4 ) the delay unit ( DVZ );

SD

Driver ( SD ) for the electronic shutter ( SORX );

SO

Shutter control signal;

SOD

delayed shutter control signal;

SODC

Shutter control signal control signal;

SR

Storage register;

SORX

electronic shutter;

SRV

Memory register output value;

SS1

first shutter signal;

SS2

second shutter signal;

STR

Start signal;

STRSTP

combined start-stop signal;

STP

Stop signal;

t

Time;

T ₀

Start time;

T _d

Delay Time;

T _e

effective delay between the rising edge of the light pulse ( LP ) and the rising edge of the delayed shutter control signal ( SOD );

T _lod

time delay between the rising edge of the light pulse control signal ( LO ) and the rising edge of the delayed light pulse control signal ( LOD );

T _ltx

time delay between the rising edge of the light pulse control signal ( LO ) and the rising edge of the intensity of the light pulse ( LP );

TM

Timing;

T _sod

time delay between the rising edge of the shutter control signal ( SO ) and the rising edge of the delayed shutter control signal ( SOD );

T _trig

Light pulse duration;

TV

Transimpedance amplifier;

ZCLK

central clock;

List of the cited writings

Stefan Henzler, Time-to-Digital Converters, Springer-Verlag

Claims (2)

Device for generating a delayed shutter control signal (SOD) for actuating an electronic shutter (SORX) of a light-sensitive measuring or sensor device - With first means (LSL, LD, PLD, LTX) for generating an amplitude-modulated light signal; - With second means (LFR) for edge detection in the amplitude-modulated light signal; - With a high-resolution time base (DLL) that is operated with a reference clock (RCLK); - with a time measuring device (TM); - with a delay control (DC); - The first means (LSL, LD, PLD, LTX) are intended and suitable for generating the amplitude-modulated light signal, in particular a light pulse (LP), with a time feature, in particular an edge, at a first point in time and with a fixed one Time offset based on the first point in time to a second point in time to generate a shutter control signal (SO), wherein the fixed time offset can also be 0 s, and - wherein the second means (LFR) are intended and suitable to detect said time feature, in particular an edge, of the amplitude-modulated light signal at a third point in time and to generate a stop signal (STP), and - The delay control (DC) generating a start signal (STR) from the shutter control signal (SO) with a controllable delay and - The high-resolution time base (DLL) is operated with a reference clock (RCLK) and - wherein the high resolution time base (DLL) has a delay line output bus (DLO) and - The signal profiles of the lines (DLO [1] to DLO [n]) of the delay line output bus (DLO) at least temporarily representing the reference clock (RCLK) or a signal dependent thereon with different delays to one another and - wherein the time measuring device (TM) detects the logical content of the delay line output bus (DLO) as a function of the start signal (STR) and the stop signal (STP) and generates a memory register output value (SRV) therefrom, which depends on the time delay depends between the first point in time and the third point in time and - the delay control (DC) generating the start signal (STR) from the shutter control signal (SO) with a controllable delay in the manner - That it depends on the memory register output value (SRV) and - That the time offset between the second point in time and the third point in time is reduced in terms of amount and, apart from control errors and system noise, is regulated to zero and - wherein the shutter control signal (SOD) depends on the start signal (STR) or is equal to the start signal (STR). Method for generating a delayed shutter control signal (SOD) for actuating an electronic shutter (SORX) of a light-sensitive measuring or sensor device with the following steps: Generating an amplitude-modulated light signal, in particular a light pulse (LP), with a time feature, in particular an edge , at a first point in time; - Generating a shutter control signal (SO) at a second point in time and with a fixed time offset in relation to the first point in time, wherein the fixed time offset can also be 0 s; - Detecting said temporal feature, in particular an edge, of the amplitude-modulated light signal at a third point in time and generating a stop signal (STP) in a fixed time reference at this third point in time; - Generating a start signal (STR) from the shutter control signal (SO) with an adjustable delay; - At least temporarily generating the signal profiles of the lines (DLO [1] to DLO [n]) of a delay line output bus (DLO) on the basis of a reference clock (RCLK) or a signal derived from a reference clock (RCLK) by means of different delays of the reference clock (RCLK); - Detection of the logical content of the delay line output bus (DLO) as a function of the start signal (STR) and the stop signal (STP) and generation of a memory register output value (SRV) as a function of this logical content, which depends on the time delay between the first Time and the third time depends and - generating the start signal (STR) from the shutter control signal (SO) with a controllable delay in such a way that the start signal (STR) depends on the memory register output value (SRV) and - that the time offset between the second point in time and the third point in time is reduced in terms of amount and is regulated to zero except for control errors and system noise.

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