DE102018111944A1 - Measuring device for determining a dielectric value - Google Patents

Abstract

The invention relates to a measuring device for determining a dielectric value (DK) of a filling material (3). The following components comprise the measuring device (1): a signal path (11) which can be brought into contact with the filling material (3) with a signal input (111) and a signal output (112); A signal generator (12) for generating a periodic measurement signal (s) at the signal input (111); A signal processing unit, wherein an adder (131) sums the number (Σ) of periods of the measurement signal (s) corresponding to the signal propagation time (s) from the signal input (111) to the signal output (112). A phase detector (132) of the signal processing unit measures the phase shift (φ) of the measurement signal (s) between the signal input (111) and the signal output (112); An evaluation circuit (13) determines the dielectric value (DK) based on the phase shift (φ) and the summed periods (Σ). The invention is thus based on the idea of roughly determining the signal transit time (t) of the measurement signal (s) dependent on the dielectric value (DK) on the basis of the summed periods (Σ) and precisely on the basis of phase shift (φ). Thus, it is possible to measure the dielectric value (DK) very precisely and simultaneously over a wide range of values.

Description

The invention relates to a measuring device for determining a dielectric value of a filling material and a corresponding method for operating the measuring device.

In automation technology, in particular in process automation technology, field devices are often used which serve for detecting and / or influencing process variables. For the detection of process variables, sensors are used which are used, for example, in level gauges, flowmeters, pressure and temperature measuring devices, pH redox potential measuring devices, conductivity meters, etc. They record the corresponding process variables, such as level, flow, pressure, temperature, pH value, redox potential, conductivity or the dielectric value. A large number of these field devices are manufactured and sold by Endress + Hauser.

The determination of the dielectric value (also known as "dielectric constant" or "relative permittivity") of fillings in containers is of great interest both for solids and for liquid fillers such as fuels, waste water or chemicals, since this value is a reliable indicator of Impurities, the moisture content or the composition can represent. The term "container" in the context of the invention, non-closed containers, such as pools, lakes or flowing waters understood.

In order to determine the dielectric value, it is possible to resort to the capacitive measuring principle according to the prior art, especially in the case of liquid filling products. In this case, the effect is used that changes the capacitance of a capacitor in proportion to the dielectric value of that medium, which is located between the two electrodes of the capacitor.

Alternatively, it is also possible to determine the dielectric value of a (liquid) medium in a container interior quasi parasitically in its level measurement. This requires the measuring principle of the guided radar, in which microwaves are guided via an electrically conductive waveguide in the medium. Described is this combined level and dielectric measurement in the published patent application DE 10 2015 117 205 A1 ,

Another alternative to capacitive or microwave-based dielectric value measurement is inductive measurement. This measuring principle is based on the fact that the resulting impedance of a coil depends not only on its number of turns, the winding material and the material of the coil core, but also on the filling material, which is respectively adjacent to the coil and thus penetrated by the magnetic field of the coil. Accordingly, the dielectric value can be determined by measuring the complex coil impedance.

In the previously described measuring principles, the corresponding measuring device has to protrude at least partially into the interior of the container or tube, so that it does not terminate flush with the container inner wall. In the case of a capacitive measurement, at least one of the two capacitor electrodes must be inserted into the container. Interior stand out. In the case of guided radar, the electrically conductive waveguide must at least partially submerge in the medium. As a result, there is the danger that the measuring device forms a disruptive body in the container or pipe, on which also deposits or germs can accumulate. With regard to the dielectric value measurement, this can in turn lead to a falsification of the measured value.

A further limitation of the measuring principles known from the prior art can be that the dielectric value can be measured either very precisely, but only over a small measuring range, or vice versa.

The invention is therefore based on the object to provide an improved measuring device for measuring the dielectric.

• - Einen mit dem Füllgut in Kontakt bringbaren Signalpfad, mit
  • ◯ einem Signaleingang, und
  • ◯ einem Signalausgang,
• - einen Signalgenerator, der ausgelegt ist, ein periodisches Messsignal am Signaleingang einzuspeisen,
• - eine Signalverarbeitungseinheit, mit
  • ◯ einem Addierer, der ausgelegt ist, eine Anzahl an Perioden des Messsignals, die der Signallaufzeit des periodischen Messsignals vom Signaleingang bis zum Signalausgang entsprechen, zu summieren, und/oder
  • ◯ einem Phasendetektor, der ausgelegt ist, die Phasenverschiebung des Messsignals zwischen dem Signaleingang und dem Signalausgang zu messen, und
• - eine Auswerteschaltung, die ausgelegt ist, anhand der gemessenen Phasenverschiebung und/oder anhand der summierten Perioden den Dielektrizitätswert zu bestimmen.

The invention solves this problem by a measuring device for determining a dielectric value of a filling material. It includes:

• - One can be brought into contact with the medium in contact signal path, with
  • ◯ a signal input, and
  • ◯ a signal output,
• a signal generator designed to feed a periodic measurement signal at the signal input,
• - A signal processing unit, with
  • ◯ an adder configured to sum a number of periods of the measurement signal corresponding to the signal propagation time of the periodic measurement signal from the signal input to the signal output, and / or
  • ◯ a phase detector designed to measure the phase shift of the measurement signal between the signal input and the signal output, and
• - an evaluation circuit which is designed to determine the dielectric value on the basis of the measured phase shift and / or on the basis of the summed periods.

According to the invention, the relationship is used by this measuring device that the signal propagation time of the periodic measurement signal from the signal input to the signal output of the signal path is proportional to the root of the dielectric value. The idea of the invention is based on roughly determining the signal propagation time based on the sum of added periods. The fine determination of the signal propagation time is based on the measured phase shift. Thus, based on the invention, it is possible to measure the dielectric constant very precisely and simultaneously over a wide measuring range. It is also not necessary to average the measured dielectric value over a large number of measurements in order to achieve the desired accuracy. This in turn lowers the power consumption of the meter.

The term "period" is defined in the context of the invention as the time within which the voltage or current profile of the measuring signal cyclically repeats. In the case of a sine signal, this therefore corresponds to a signal passage of 360 ° or the corresponding time; For a pulse or square wave signal, this corresponds to the time between the positive or negative edges of two cyclically consecutive pulses / squares.

Accordingly, according to the invention, in principle it is not stipulated which shape (that is to say, for example, sinusoidal, triangular, sawtooth or rectangular) must have the measuring signal. Depending on the design, it is, for example, conceivable to design the signal generator such that the measurement signal is generated in the form of a rectangular signal with a predefined pulse-pause ratio.

Also with regard to the frequency of the measuring signal, there are no rigid specifications. However, it is advantageous if the signal generator is designed to generate the measuring signal with a frequency of at least 0.5 GHz or in particular with a frequency between 0.5 GHz and 6 GHz. Higher frequencies can be generated by correspondingly more compact signal generators. At lower frequencies, moreover, the conductivity of the filling material increasingly affects the measuring accuracy.

According to the invention, the adder must be designed to sum the number of periods of the measurement signal which correspond to the signal propagation time of the periodic measurement signal from the signal input to the signal output. For this purpose, the adder may for example be designed such that the periods at the signal input or at a reference oscillator (starting from the measuring signal at the signal input) are summed until the adder reaches the arrival of the measuring signal at the signal output, for example by means of a reset input of a set Reset block (also known as set-reset gate) of the adder, detected.

With regard to the summation of the periods, the adder can also be designed in any suitable manner. A technical realization possibility is that the adder sums periods of the measurement signal by the adder corresponding charge values of the positive or negative half-waves of respective periods of the measurement signal, in particular by means of at least one capacitor or a capacitor, cumulative, that is added up. By means of the accumulated charge value, the adder can subsequently, e.g. Using a look-up table, determine the sum of periods.

• - Kaskade, bestehend aus
  • ◯ zumindest einem Frequenzteiler zur Frequenzteilung des am Signalausgang empfangenen Messsignals,
  • ◯ und jeweils einen vor- bzw. nachgeschalteten Kondensator

umfasst. In diesem Fall ist der Addierer so auszulegen, dass die Summe an Perioden des Messsignals bestimmt wird, indem der Addierer zwei verschiedenen Ladungszuständen der Kondensatoren jeweils einen Bitwert zuordnet. Der Addierer kann anhand der zugeordneten Bitwerte im Anschluss einen Binärwert generieren, welcher der Summe an Perioden entspricht. Somit liegt die Summe bereits im Addierer selbst als digitaler Wert vor. Genutzt wird bei dieser Ausgestaltungsvariante des Addierers, dass das Signalende des Messsignals am Signalausgang pro Frequenzhalbierung jeweils invertiert wird.An alternative way of summing the periods is for the adder to have a

• - Cascade, consisting of
  • ◯ at least one frequency divider for frequency division of the measurement signal received at the signal output,
  • ◯ and one upstream or downstream capacitor

includes. In this case, the adder is to be designed so that the sum is determined at periods of the measurement signal in that the adder assigns a bit value to two different charge states of the capacitors. The adder can then use the assigned bit values to generate a binary value which corresponds to the sum of periods. Thus, the sum is already present in the adder itself as a digital value. Is used in this embodiment variant of the adder, that the signal end of the measuring signal at the signal output per frequency bisection is respectively inverted.

In a further development, the measuring device according to the invention can determine not only the dielectric value but also the dielectric loss factor of the filling material. For this purpose, the measuring device comprises an amplifier arranged at the signal output. Its gain factor is to be regulated such that the received and amplified measurement signal has a constant amplitude. In this case, the evaluation circuit, if it is designed accordingly, determine the dielectric loss factor of the filling material on the basis of the amplification factor.

According to the invention, the signal path of the measuring device must only be brought into contact with the filling material insofar as the electric field of the signal path, which is caused by the measuring signal, penetrates sufficiently into the filling material that a change in the dielectric value de contents leads to a corresponding attenuation of the electric field, or to a change in the signal speed in the signal path. Accordingly, no direct contact of the signal path to the product is required. Rather, the signal path can be separated from the filling material by a dielectric material, for example a glass or ceramic coating. As a result, the measuring device can be designed with a surface that is planar with respect to the filling material, so that the measuring device is flush and flat with the container inner wall.

ca. 13 mm beträgt. Analog hierzu ergibt sich in einem Signalpfad aus Kupfer (DK ca. 3) eine theoretische Wellenlänge von ca. 17,3 mm. Unter der vereinfachten Annahme, dass das Messsignal zu 2/3 im Signalpfad und zu 1/3 als elektromagnetische Welle im Füllgut verläuft, ergibt sich gemäß der Gewichtung $$\frac{1}{3}\ast \mathrm{4,7}mm+\frac{2}{3}\ast \mathrm{17,32}mm=\mathrm{13,1}mm$$

eine effektive Wellenlänge von ca. 13,1 mm. Entsprechend dieser effektiven Wellenlänge von 1311 mm, multipliziert mit der Signallänge, die der Signallaufzeit des Messsignals vom Signaleingang bis zum Signalausgang entspricht (also bspw. 1.5 Perioden = 1.5 ns bei 1 GHz), ergibt sich eine exemplarische Mindestlänge des Signalpfades von 19.65 mm.In the context of the invention, it is advantageous to dimension the signal path with a defined path length by taking into account the frequency of the measurement signal and the expected range of the dielectric value. The basis of such a dimensioning is that the path length has a minimum length that corresponds to the effective wavelength of the measurement signal in the medium: at a frequency of, for example, 1 GHz, the electromagnetic wave corresponding to the measurement signal has a wavelength of 30 mm in vacuum, wherein the theoretical wavelength in the medium (at an expected dielectric value of about 90) according to $$\lambda =\frac{{\lambda }_0}{{\left(DK\right)}^{1/2}}=\frac{30mm}{{\left(40\right)}^{1/2}}~4.7mm$$

about 13 mm. Analogously, in a signal path of copper ( DK approx. 3) a theoretical wavelength of approx. 17.3 mm. Under the simplified assumption that the measurement signal runs 2/3 in the signal path and 1/3 as the electromagnetic wave in the medium, the weighting results $$\frac{1}{3}*4.7mm+\frac{2}{3}*17.32mm=13.1mm$$

an effective wavelength of about 13.1 mm. Corresponding to this effective wavelength of 1311 mm, multiplied by the signal length which corresponds to the signal propagation time of the measurement signal from the signal input to the signal output (ie 1.5 cycles = 1.5 ns at 1 GHz), an exemplary minimum signal path length of 19.65 mm results.

However, the path length does not have to be constant. Rather, the signal path may have a variable path length. For if a control unit provided for this purpose sets the path length such that the output signal of the phase detector (between the mixer and the capacitor) has an approximately constant pulse-pause ratio of, in particular, 50% each, the evaluation circuit can, with a corresponding design, use the set path length to determine the dielectric value determine in an alternative way. To set the path length changeable, for example, different lengths path segments can be kept, which can be optionally switched.

To determine the dielectric value, it is advantageous by means of the idea according to the invention if the signal generator is designed to generate the measuring signal not continuously but with a defined signal length, that is to say a defined number of periods. In this case, it is particularly appropriate if the signal generator can control the signal length of the measuring signal in dependence on the signal propagation time of the signal between the signal input and the signal output, that the signal length increases proportionally with increasing signal propagation time, for example. This has the advantage that the signal generator only has to generate the measuring signal as long as it is necessary to carry out the method according to the invention. For this purpose, the signal generator can be designed so that the generation of the measuring signal is stopped as soon as the reaching of the measuring signal at the signal output is detected. In this case, an error detection could also be implemented: In the event of a fault, ie if the signal length exceeds a predefined maximum value, for example due to non-recognition of the measurement signal at the signal output, the evaluation circuit can output a corresponding error signal.

• - Einspeisen des Messsignals am Signaleingang mittels des Signalgenerators,
• - Summieren der Perioden des Messsignals am Signaleingang mittels des Addierers, bis das Messsignal am Signalausgang detektiert wird, und/oder Messung der Phasenverschiebung des Messsignals zwischen dem Signaleingang und dem Signalausgang mittels des Phasendetektors, und
• - Ermittlung des Dielektrizitätswertes anhand der gemessenen Phasenverschiebung und/oder anhand der summierten Perioden durch die Auswerteschaltung.

The basic method according to the invention comprises, corresponding to the measuring device according to one of the aforementioned embodiments, the following method steps:

• Feeding the measuring signal at the signal input by means of the signal generator,
• - Summing the periods of the measuring signal at the signal input by means of the adder, until the measuring signal is detected at the signal output, and / or measurement of the phase shift of the measuring signal between the signal input and the signal output by means of the phase detector, and
• - Determining the dielectric value based on the measured phase shift and / or on the basis of the summed periods by the evaluation circuit.

• 1: Ein Messgerät zur DK-Messung an einem Behälter mit einem Füllgut,
• 2: einen schematischen Aufbau des erfindungsgemäßen Messgerätes,
• 3: zeitliche Verläufe eines Messsignals im Messgerät,
• 4: eine Realisierungsvariante des Phasendetektors des Messgerätes,
• 5: eine Realisierungsvariante des Addierers des Messgerätes,
• 6: zeitliche Verläufe des Messsignals am Frequenzteiler, und
• 7: eine Realisierungsvariante des Frequenzteilers des Addierers.

Based on the following figures, the invention will be explained in more detail. It shows:

• 1 : A measuring device for DK Measurement on a container with a filling material,
• 2 : a schematic structure of the measuring device according to the invention,
• 3 : temporal courses of a measuring signal in the measuring device,
• 4 : an implementation variant of the phase detector of the measuring device,
• 5 : an implementation variant of the adder of the measuring device,
• 6 : temporal courses of the measuring signal at the frequency divider, and
• 7 : an implementation variant of the frequency divider of the adder.

For a general understanding of the measuring device according to the invention 1 is in 1 a schematic arrangement of the measuring device 1 on a container 2 with a filling 3 shown: To determine the dielectric value DK of the contents 3 is the measuring device 1 laterally at a connection of the container 2 , For example, arranged a flange connection. For this is the meter 1 mounted approximately positively to the container inner wall, so that one of the meter 1 generated electric field in the medium 3 can penetrate. For the contents 3 they can be liquids such as drinks, paints, cement or fuels, such as liquefied gases or mineral oils. However, it is also conceivable to use the measuring device 1 for bulk goods 3 , such as cereals.

The measuring device 1 can with a parent unit 4 , for example a process control system. The interface can be implemented as "PROFIBUS", "HART", "Wireless HART" or "Ethernet". This can be the dielectric value DK be transmitted. But it can also provide other information about the general operating condition of the meter 1 be communicated.

The basic circuit design of the measuring device according to the invention 1 is in 2 The structure is based on a signal path 11 , which is connected to a signal input 111 from a signal generator 12 is controlled. As a measuring signal s _HF generates the signal generator 12 a periodic electrical signal with a predefined frequency _HF , for example, 1 GHz.

After passing along the signal path 11 becomes the measuring signal e _HF at a corresponding signal output 112 through a phase detector 132 and an adder 131 receive. According to the invention this serves to that number Σ at periods of the measuring signal s _HF to sum up the signal transit time t _s of the periodic measurement signal s _HF from the signal input 111 to the signal output 112 correspond; Respectively, this serves a phase shift φ of the measuring signal s _HF between the signal input 111 and the signal output 112 to eat. So that the phase detector 132 the phase shift φ of the measuring signal s _HF between the signal input 111 and the signal output 112 can measure, and thus the adder 131 one of the signal transit times t _s corresponding number Σ at periods of the measuring signal s _HF can sum, are the phase detector 132 and the adder 131 each also corresponding to the signal input 111 connected.

The signal path 11 can be realized as a metallic conductor, for example as a copper-based interconnect structure on a printed circuit board substrate. As a mechanical protection against the filling material, the printed circuit board can optionally be encapsulated by means of a corresponding glass or ceramic coating. In this case, if appropriate, parallel to the signal path, a corresponding counterelectrode can also serve as the reference ground. Alternatively to a design of the signal path 11 as a loop, as in 2 It would also be possible to see the signal path 11 be interpreted that the signal input 111 and the signal output 112 at the same end of the signal path 11 are arranged. In this case, the signal input would be 111 and the signal output 112 to disconnect via a corresponding transceiver.

mit $$v_s\sim \frac{c_0}{{\left(DK\right)}^{1/2}}$$

vom Dielektrizitätswert DK des Füllgutes 3 abhängig (l₁₁ ist hierbei die Pfadlänge des Signalpfades 11; v_s ist die Signalgeschwindigkeit des Messsignals s_HF; c₀ ist die bekannte Lichtgeschwindigkeit in Vakuum). Dabei kann die Proportionalitätskonstante zwischen der Signalgeschwindigkeit v_S und der Wurzel des Dielektrizitätswertes DK beispielsweise durch Kalibration des Messgerätes 1 an einem Füllgut 3 mit bekanntem Dielektrizitätswert DK bestimmt werden (bspw. H₂O: DK = 80 bei 20° C und Atmosphärendruck).The summation or the determination of the phase shift is used φ According to the invention, the signal transit time over this t _s of the measuring signal s _HF from the signal input 111 to the signal output 112 to determine. The signal transit time t _s is again according to the context $$t_s=\frac{l_{11}}{v_s\left(DK\right)}$$

With $$v_s~\frac{c_0}{{\left(DK\right)}^{1/2}}$$

from the dielectric value DK of the contents 3 dependent ( ₁₁ Here is the path length of the signal path 11 ; v _s is the signal speed of the measurement signal s _HF ; c ₀ is the known speed of light in vacuum). The proportionality constant between the signal speed v _p and the root of the dielectric value DK for example, by calibration of the meter 1 on a medium 3 with known dielectric value DK be determined (eg H ₂ O: DK = 80 at 20 ° C and atmospheric pressure).

Because the frequency _HF of the measuring signal s _HF reciprocally at each one period of the measurement signal s _HF is, the relationship between the signal transit time arises t _s , the sum Σ at periods and the phase shift φ according to $$t_s={\displaystyle \Sigma {\left(f_{HF}\right)}^{-1}+\phi }$$

Based on this relationship between the sum Σ at periods, the phase shift φ and the dielectric value DK can be a correspondingly programmed evaluation circuit 13 of the measuring device 1 , as in 2 shown, the dielectric value DK of the contents 3 determine.
The invention is thus based on the idea of signal propagation time t _s or the dielectric value DK roughly based on the summed periods Σ during the fine determination of the dielectric value DK by phase shift φ he follows.

Basically, it is not relevant if the evaluation circuit 13 as a standalone computer, for example, is designed as a microcontroller or FPGA. It is also conceivable, the evaluation circuit 13 together with the signal generator 12 , the phase detector 132 or the adder 131 to realize as a common monolithic semiconductor device. Alternatively, the evaluation circuit 13 in the form of an external processing unit, such as a corresponding program of the higher-level unit 4 be implemented.

Based on 3 becomes the idea according to the invention, that of the dielectric value DK dependent signal transit time t _s of the measuring signal s _HF roughly based on the summed periods Σ and by phase shifting φ to determine precisely, in more detail using a rectangular measuring signal s _HF (In the specific example, with a pulse-pause ratio of about 25% to 75%; the levels could be, for example, 0 V and 5 V) illustrates: There has the measurement signal s _HF In the embodiment shown, a signal length of six periods. In addition to the time course of the measurement signal s _HF at the signal input 111 is also the same time course of the signal output 112 received measurement signal e _HF shown. As can be seen, the measuring signal is e _HF by the signal transit time t _s along the signal path 11 after reception at the signal output 112 temporally to the signal input 111 added. As can be seen, the offset in this illustrative example is about 1.5 periods. At a frequency _HF of the measurement signal of 1 GHz this corresponds to a signal propagation time t _s through the signal path 11 of about 1.5 ns.

This striking signal delay t _s 1.5 ns or 1.5 periods results from the defined path length ₁₁ the signal path 11 of about 19.65 mm and the measured dielectric value DK ~ 90 according to $$t_s~\frac{l_{11}}{c_0}*{\left(DK\right)}^{1/2}$$

Like also in 3 is shown, the adder sums 131 corresponding to this exemplary signal transit time t _s of about 1.5 ns two periods (Σ = 2), the phase detector detects a phase shift of about φ = - 180 ° = - 0.5 ns.

Thus the in 2 shown signal generator 12 the measuring signal s _HF not endless, but generated only with a defined, limited signal length (in 3 corresponds to the signal length of the measuring signal s _HF respectively. e _HF six periods), the signal generator can 12 via a corresponding input by the arrival of the measurement signal e _HF at the signal output 112 be stopped again (not in 2 ) Shown. As a result, the signal length or the number of its emitted periods is controlled so that they with increasing signal propagation time t _s (ie as a function of the dielectric value DK ) proportionally increases.

A circuit technology possibility for the realization of the phase detector 132 for rectangular measuring signals s _HF is in 4 shown: The local phase detector 132 includes an input for the measurement signal s _HF , at the signal input of the signal path 11 is tapped, and an input for the received measurement signal e _HF that at the signal output 112 the signal path 11 is tapped (see also 2 ). Each of these inputs is preferably a non-clocked edge detector 134 .
134` downstream. In this case, the edge detectors 134 . 134` in principle be designed both for detecting the positive and the negative edge. By the edge detectors 134 . 134` loses the measurement signal s _HF . e _HF each its amplitude information and only retains its phase shift φ as relative time information.

Following the edge detector 134 . 134 ' becomes the measuring signal s _HF . e _HF in each case one (again preferably non-clocked) frequency divider 135 . 135` fed, each of which generates a signal with a pulse-pause ratio of 50%. The signals thus obtained become a mixer 136 fed. For the in 4 shown embodiment of the phase detector 132 offers itself as a mixer 136 in particular a Gilbert cell. Depending on the type of measurement signal s _HF . e _HF however, it may be advantageous as a mixer 136 use an XOR gate or an equivalence gate (XNOR). The basis of the mixer 136 The signal obtained has a pulse-pause ratio that is (linear) proportional to the phase shift φ is.

To further improve the phase accuracy, it would also be possible to use the frequency dividers 135 . 135 ' to add further frequency dividers or to increase the divider factor. As in 4 pictured, can the mixer 136 also a low pass filter 137 be downstream to filter out high-frequency interference signal components. By means of the signal thus obtained becomes a capacity 138 loaded. Here is the charge or the voltage at the capacity 138 again (linear) proportional to the pulse-pause ratio of the signal of the mixer 136 , and accordingly also (linear) proportional to the phase shift φ of the measuring signal s _HF . e _HF between signal input 111 and signal output 112 , By a corresponding analog / digital conversion of the analog voltage value of the capacitance 138 can therefore phase shift φ as digital value of the evaluation circuit 13 (please refer 2 ) be transmitted. To reset the capacity 138 after the measurement signal s _HF . e _HF in full signal length the capacity 138 has loaded, serves a corresponding reset signal r , This can be the capacity 138 For example, be grounded or discharged for the next measurement cycle.

In the 4 shown embodiment of the phase detector 132 includes at the input for the received measurement signal e _HF in addition an input amplifier 133 , This serves to reduce the amplitude of the received measurement signal e _HF by the electrical impedance of the signal path 11 compensate. The input amplifier can do this 133 be designed in a further development of the invention so that its amplification factor A is regulated so that the received, amplified measurement signal e _HF has an approximately constant amplitude. The reason for a different attenuation can be the dielectric loss factor of the filling material 3 depending on the type of product 3 can be different. In this case, the dielectric loss factor of the filling material represents 3 the complex-valued electrical impedance of the filling material 3 , Accordingly, the evaluation circuit 13 be designed in this advancement, based on the input amplifier 133 set amplification factor A the dielectric loss factor of the filling material 3 For example, by assigning the determined gain factor to an equivalent loss factor using a look-up table. Thus, the contents could be 3 based on the dielectric value DK and the dielectric loss factor.

• Zum einen kann das Ausgangssignal des AND-Gatters 140 (analog zum Phasendetektor, vgl. 4) lediglich einer einzigen Kapazität 138` zugeführt werden. Dementsprechend erhöht sich die Ladung bzw. die Spannung der Kapazität 138` proportional zu der Anzahl ∑ an Perioden. Durch Auslesen bzw. digitalisieren des analogen Spannungswertes, der an dieser Kapazität 138' anliegt, kann ein korrespondierender Digitalwert erstellt werden. Dabei könnte die Digitalisierung wiederum durch Zuordnung des anliegenden Spannungswertes zu einem korrespondierenden Digitalwert einer look-uptable, der eine definierte Anzahl ∑ an Perioden repräsentiert, erfolgen.

In 5 is a possible circuit implementation variant of the adder 131 shown: According to the local interpretation of the adder sums 131 the number Σ at periods of the measuring signal s _HF , the signal propagation time t _s of the periodic measurement signal s _HF from the signal input 111 to the signal output 112 match by the adder 131 the periods at the signal input 111 sums up until the measurement signal s _HF at the signal output 112 arrives. For this purpose, the adder detects 131 the arrival of the measuring signal e _HF at the signal output 112 through a reset input 1R a set-remainder gate 139 , At the set entrance 1S of the set reset gate 139 becomes the measuring signal s _HF of the signal input 111 tapped (compare also 2 ). The output of the set-remainder gate 139 gets to the input of an AND gate 140 led, with the further input of the AND gate 140 the measuring signal s _HF at the signal input 111 taps. This is due to the output of the AND gate 140 the measuring signal SHF only on until the measuring signal eHF the signal output 112 or the set reset gate 139 reached. That at the output of the AND gate 140 adjacent signal thus corresponds to the lowest, in 3 shown signal Σ = 2. The summation of the periods of the output of the AND gate 140 applied signal can be done in principle in various ways. Two possible execution options are based on 5 illustrates:

• On the one hand, the output signal of the AND gate 140 (analogous to the phase detector, cf. 4 ) are only supplied to a single capacity 138 '. Accordingly, the charge or voltage of the capacitance increases 138` proportional to the number Σ at periods. By reading out or digitizing the analog voltage value at this capacity 138 ' is present, a corresponding digital value can be created. In this case, the digitization could in turn be made by assigning the applied voltage value to a corresponding digital value of a look-uptable having a defined number Σ represented at periods, take place.

• In 6 ist zum einem das Ausgangssignal des AND-Gatters 140 (oben, sieh auch 3, unterste Reihe) dargestellt. Zum anderen ist dieses Signal nach Frequenzteilung durch den Frequenzteiler 135" (unten) in 6 dargestellt: Wie zu erkennen ist, herrscht am Ausgang des AND-Gatters 140 nach Durchlauf der zwei Perioden des Messsignals s_HF ein tiefer Spannungspegel vor. Dementsprechend weist die Kapazität 138`, die am Ausgang des AND-Gatters 140 anschließt, einen niedrigen Ladungszustand (entspricht logisch = 0) auf. Nach Frequenzteilung durch den Frequenzteiler 135" verhält es sich an der zweiten Kapazität 138" genau umgekehrt (siehe unten in 6): Dort ist der Ladungszustand entsprechend des hohen Signalpegels „hoch“ bzw. „geladen“ (entspricht logisch = 1).

An extended circuit for summing the periods of the output of the AND gate 140 applied signal consists in a cascaded arrangement of frequency dividers 135 ' and capacities 138 ' . 138 ' as it is in 5 at the output of the NAND gate 140 is shown (in the example shown, the cascade consists of illustrative purposes only of a cascade stage). For a cascaded design, the capacities are 138 ' . 138 ' dimensioned with a small compared to the first embodiment, the capacity, so that already a half-period of the measurement signal s _HF a complete loading or unloading of the respective capacity 138 ' . 138 ' (For example, to a state of charge or voltage level greater than 5 V or when discharged to 0 V) causes. In this case, the voltage values / charge states represent the capacitances 138 ' . 138 ' already single bits of a binary value, which in turn is the number Σ represents the summed periods. This functionality is based on 6 illustrates in more detail:

• In 6 on the one hand is the output signal of the AND-gate 140 (above, look too 3 , bottom row). On the other hand, this signal is after frequency division by the frequency divider 135 ' (below) in 6 As you can see, the exit of the AND gate 140 after passing through the two periods of the measuring signal s _HF a low voltage level. Accordingly, the capacity points 138` at the output of the AND gate 140 connects, a low state of charge (corresponds to logic = 0) on. After frequency division by the frequency divider 135 ' it behaves at the second capacity 138 ' exactly the opposite (see below in 6 ): There is the state of charge according to the high signal level "high" or "charged" (corresponds to logic = 1).

So unless the capacity 138` , which is directly at the output of the AND gate 140 is contacted as Isb ("Least Significant Bit") is assigned, and provided the capacity 138 ' that the frequency divider 135 ' is interpreted as msb ("Most Significant Bit"), results in the in 2 and 7 represented signal based on the two capacities 138 ' . 138 ' a binary value of "10", which is a hexadecimal value of "two", ie the number of periods Σ , corresponds. These bits must be stored accordingly in a memory to which the evaluation circuit 13 for determining the dielectric value DK can fall back. According to this interpretation of the adder 131 is at a number of maximum Emax expected periods (this in turn depends on the design of the path length ₁₁ the signal path 11 ab) the adder 131 corresponding to 2 ^Σmax times with a respective frequency divider 135 ' / Capacitor 138 "to cascade.

• Sobald über einen Eingang des Frequenzteilers 135, 135', 135" eine erste positive Flanke desjenigen Signals ∑, dessen Frequenz f_HF zu teilen ist, anliegt, werden über einen hochohmigen Eingangs-Widerstand R₇ die zwei Kondensatoren C₁ , C₂ , (beide jeweils ca. 10 pF) aufgeladen. Allerdings sperrt ein erster Transistor T₁ , dessen Gate am Kondensator C₁ kontaktiert ist; Ein zweiter Transistor T₂ , dessen Gate an den zweiten Kondensator C₂ angeschlossen ist, ist leitend. Dadurch, dass die Gate-Spannung am ersten Transistor T₁ (nach vorherigem Reset, siehe nächster Abschnitt) auf Signalmassepotential liegt, kann sich der erste Kondensator C₁ in Bezug zum zweiten Kondensator C₂ nur geringer aufladen. Daher liegt eine zwischen dem Transistor-Gate T₁ angeordnete Diode D₁ unter Spannung in Sperrrichtung; Eine entsprechende zweite Diode D₂ , die zwischen dem Gate des zweiten Transistors T₂ und dem zweiten Kondensator C₂ zwischengeschaltet ist, ist quasi stromfrei (beidseitig gleiches Potential).

A possible circuit realization of the frequency divider 135 . 135 ' . 135 ' is in 7 The circuit there is based on two parallel capacitors C ₁ . C ₂ , These are by the signal Σ whose frequency _HF to halve is loaded and unloaded in different ways:

• Once via an input of the frequency divider 135 . 135 ' . 135 ' a first positive edge of that signal Σ whose frequency _HF is to be connected, are applied via a high-impedance input resistor R ₇ the two capacitors C ₁ . C ₂ , (both about 10 pF) charged. However, a first transistor blocks T ₁ whose gate is on the capacitor C ₁ is contacted; A second transistor T ₂ whose gate is connected to the second capacitor C ₂ connected is conductive. This causes the gate voltage on the first transistor T ₁ (after previous reset, see next section) is at signal ground potential, the first capacitor can C ₁ in relation to the second capacitor C ₂ only charge a little. Therefore, there is one between the transistor gate T ₁ arranged diode D ₁ under tension in the reverse direction; A corresponding second diode D ₂ between the gate of the second transistor T ₂ and the second capacitor C ₂ is in between, is virtually power-free (the same potential on both sides).

As soon as the voltage at the input of the frequency divider 135 . 135 ' . 135 ' for the frequency to be divided signal Σ changes, the now negative edge of the signal Σ over the two capacitors C ₁ . C ₂ each to the two diodes D ₁ and D ₂ be transmitted. This is now, since the diode D ₂ is current-free, the second capacitor C ₂ back to the first capacitor C ₁ reloaded, with the voltage at the first diode D ₁ momentarily reversed. This change is via the second diode D ₂ to the gate of the second transistor T ₂ transfer. This short negative edge at the gate blocks the second transistor T ₂ again. Due to the simultaneous blocking effect of the first diode D ₁ may be the first transistor T ₁ do not switch.

Because the next edge of the signal Σ at the input of the frequency divider 135 . 135 ' . 135 ' is positive again, this again causes a reloading of the second capacitor C ₂ on the first capacitor C ₁ , Due to the diodes D ₁ and D ₂ can be the positive edge of the input signal Σ however, the gates of the two transistors T ₁ . T ₂ do not influence. As a result, a switching is effected in each case with the negative edges and it results at the gate of the first transistor T ₁ or a downstream output resistance R ₄ with the source of the second transistor T ₂ is interconnected, an output signal Σ / 2 with half the frequency _HF / 2 of the input signal Σ at a pulse-pause ratio of exactly 50:50.

Since the in 7 shown frequency divider 135 . 135 ' . 135 ' is not clocked, this is before each measurement cycle via a reset input r which is the gate of the transistor T ₁ controls, reset: to the reset input r For this purpose, a short pulse of a few nanoseconds is applied. This pulse is transmitted across the two capacities C ₁ . C ₂ to the gates of the two n-channel transistors T ₁ . T ₂ through the two diodes D ₁ . D ₂ only very damped in the reverse direction. When subsequently switching off again at the reset input r This results in a short voltage drop across the current through both diodes D ₁ . D ₂ because the signal is at the first transistor T ₁ is applied directly to the gate, and thus not only affects the edge of the pulse. Since the DC component of the pulse also acts, results at the gate of the transistor T ₁ continue to be a positive tension. By the series connection of the two capacitors C ₁ . C ₂ and a high impedance input resistor R ₇ only the edge reaches the gate of the transistor T ₂ and causes there a short negative amplitude, causing this transistor T ₂ locks. About a third diode D ₃ the pulse of the reset input arrives r on the input for the signal Σ whose frequency _HF to halve is. With this resulting negative edge becomes the capacitor C ₁ momentarily negative and on the capacitor C ₂ transhipped. This is the diode D ₁ short-term in the forward direction (through the negative peak). As a result, this negative peak reaches the gate of the transistor T ₁ , whereby this locks. This effect also occurs on the capacitor C ₂ on. Because the second diode D ₂ However, in the reverse direction, the voltage is not sufficient there to the field effect transistor T ₂ to turn on.

LIST OF REFERENCE NUMBERS

1

gauge

2

container

3

filling

4

Parent unit

11

signal path

12

signal generator

13

evaluation

111

signal input

112

signal output

131

adder

132

phase detector

133

amplifier

134

edge detector

135

frequency divider

136

mixer

137

Low Pass Filter

138

capacity

139

Set Reset Gate

140

AT D gate

A

gain

DK

dielectric value

e _HF

Received measurement signal

_HF

Frequency of the measuring signal

₁₁

Path length of the signal path

r

Reset signal

S _HF

measuring signal

t _s

Signal propagation time

v _s

Signal speed of the measurement signal

φ

phase shift

Σ

Totaled periods of the signal

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 102015117205 A1 [0005]

Claims (12)

Measuring device for determining a dielectric value (DK) of a filling material (3), comprising: - a signal path (11) which can be brought into contact with the filling material (3), with ◯ a signal input (111), and ◯ a signal output (112), - Signal generator (12), which is designed to feed a periodic measurement signal (s _HF ) at the signal input (111), - a signal processing unit, with ◯ an adder (131) which is designed a number (Σ) of periods of the measurement signal (s _HF ) corresponding to the signal propagation time of the periodic measurement signal (s _HF ) from the signal input (111) to the signal output (112), and / or ◯ a phase detector (132) designed to phase shift (φ) the measurement signal (s _HF ) between the signal input (111) and the signal output (112), and - an evaluation circuit (13) which is designed based on the measured phase shift (φ) and / or on the basis of the summed periods (Σ) the dielectric value (DK) to be determined men. Meter after Claim 1 wherein the signal generator (12) is adapted to generate the measurement signal (s _HF ) in the form of a square wave signal with a predefined pulse-pause ratio. Meter after Claim 1 or 2 wherein the signal generator (12) is adapted to generate the signal (s _HF ) at a frequency between 0.5 GHz and 6 GHz. Measuring device according to one of the preceding claims, wherein the adder (131) is designed, the number (Σ) of periods of the measuring signal (s _HF ), the signal propagation time of the periodic measuring signal (s _HF ) from the signal input (111) to the signal output (112 ), in that the adder (131) sums the periods at the signal input (111) or at a reference oscillator until the adder (131) detects the arrival of the measurement signal (e _HF ) at the signal output (112). Measuring device according to one of the preceding claims, wherein the adder (131) is designed to sum periods of the measuring signal (s _HF ) by the adder (131) corresponding charge values of the positive or negative half-waves of respective periods of the measuring signal (s _HF ), in particular by means of at least one capacitor (134, 134 '), and in that the adder (131) determines the sum (Σ) of periods by means of the accumulated charge value, in particular by means of a look-up table. Measuring device according to one of Claims 1 to 4 in which the adder (131) has a cascade, comprising at least one frequency divider (135 ') for frequency division of the measurement signal (s _HF ) received at the signal output (112), and one upstream or downstream capacitor (138', 138 "), wherein the adder (131) is arranged to determine the sum (Σ) at periods of the measurement signal (s _HF ) by the adder (131) having two different charge states of the capacitors (138 ', 138") Bit value, and in that the adder (131) generates, based on the assigned bit values, a binary value corresponding to the sum (Σ) of periods. Measuring device according to one of the preceding claims, comprising: - an amplifier (133) arranged at the signal output (112) whose amplification factor (A) is controlled such that the received, amplified measuring signal (e _HF ) has a constant amplitude, wherein the evaluation circuit ( 13) is designed to determine a dielectric loss factor of the filling material (3) on the basis of the amplification factor (A). Measuring device according to one of the preceding claims, wherein the signal path (11) has a variable path length (l ₁₁ ), wherein a control unit is provided which is adapted to set the path length (l ₁₁ ) such that an output signal of the phase detector (132) in each case has a constant pulse-pause ratio of in each case 50%, and wherein the evaluation circuit (13) is designed to determine the dielectric value (DK) based on the set path length (l ₁₁ ). Measuring device according to one of the preceding claims, wherein the signal generator (12) is designed to generate the measuring signal (s _HF ) with a defined signal length. Meter after Claim 9 in which the signal generator (12) is designed to control the signal length of the measuring signal (s _HF ) in dependence on the signal propagation time of the measuring signal (s _HF ) between the signal input (111) and the signal output (112) such that the signal length increases with increasing signal propagation time , in particular linear, increases. Meter after Claim 10 , wherein the evaluation circuit (13) is designed to output an error signal, if the signal length exceeds a predefined maximum value. Method for determining the dielectric value (DK) by means of the measuring device (1) according to one of the preceding claims, comprising the following method steps: Feeding the measuring signal (s _HF ) at the signal input (111) by means of the signal generator (12), - summing the periods of the measuring signal (s _HF ) at the signal input (111) by means of the adder (131) until the measuring signal (s _HF ) at the signal output (112) is detected, and / or measurement of the phase shift (φ) of the measurement signal (s _HF ) between the signal input (111) and the signal output (112) by means of the phase detector (132), and - Determining the dielectric value (DK) from the measured phase shift (φ) and / or on the basis of the summed periods (Σ) by the evaluation circuit (13).

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