DE102017127478B4 - Device and method for generating a reference voltage - Google Patents

Abstract

Device comprising:
a first series circuit comprising a first resistor (11) and a first diode arrangement (13), the first series circuit to be coupled between a first voltage (10) and a second voltage,
a second series connection comprising a second resistor (12) and a second diode arrangement (14), the second diode arrangement (14) being different from the first diode arrangement (13), the second series connection between the first voltage (10) and the second voltage is to be coupled,
a first capacitor (17), a first terminal of the first capacitor (17) being connected via a first switch (15) to a first node between the first resistor (11) and the first diode circuit (13) and via a second switch ( 114) is to be connected to the second voltage,
a second capacitor (110), a first terminal of the second capacitor (110) being connected via a third switch (16) to a second node between the second resistor (12) and the second diode arrangement (14) and via a fourth switch ( 18) is to be connected to the second voltage,
wherein a second terminal of the first capacitor (17) is connected to a second terminal (110) of the second capacitor, and
a controller (112), the controller being arranged to open the first (15) and the fourth (18) switch and to close the second (114) and the third (16) switch in a first phase of operation, and in a second Operating phase to close the first (15) and the fourth (18) switch and to open the second (114) and the third (16) switch.

Description

technical field

The present application relates to methods and devices for generating reference voltages in electronic circuits.

background

In many cases, integrated circuits include digital and analog circuit parts. A task of one or more analog circuits in such an integrated circuit is in some cases to provide a constant voltage, such as a reference voltage, or a constant current. Constant here means that the voltage or current is approximately constant, i.e. constant within a certain acceptable tolerance, at least over a certain temperature range or a range of an external supply voltage. Such a constant voltage is used, for example, to detect a fault in an external supply voltage in conventional circuits.

So-called bandgap voltage reference circuits (also referred to as bandgap circuits) are widely used to provide constant voltages, which provide a reference voltage that corresponds at least approximately to the bandgap of silicon, i.e. about 1.25 V. However, modern technologies such as 40 nanometer technologies or smaller often use a supply voltage that is in the order of the bandgap voltage (e.g. a supply voltage of 1.3 V) or even lower, since scaling down the technology to smaller sizes due to a corresponding Decreasing the thickness of gate oxides is associated with smaller supply voltages. Due to leakage current requirements, threshold voltages of transistors are not reduced in the same way.

With such low supply voltages, conventional bandgap reference circuits may have a start-up problem and/or generate a voltage that is too high for some purposes.

Furthermore, it is generally desirable to design circuits for generating a constant voltage as simply as possible, for example in order to reduce the area requirement or the implementation complexity.

the GB 2 308 684 A discloses a circuit in which a reference voltage is generated by means of switched capacitors. A first capacitor is selectively connected to a node between a current source and a first diode-connected transistor or to a node between a second current source and a second diode-connected transistor. A second capacitor is selectively connected to the node between the second current source and the second diode-connected transistor or to a reference voltage. Voltages present at the first and second capacitors are then further processed.

Die Karel E. Kuijk, "A precision reference voltage source". In: IEEE Journal of Solid-State Circuits, Vol. SC-8, No. 3, June 1973 discloses a bandgap reference voltage using voltages at nodes between respective resistors and diode-connected transistors.

abstract

A circuit according to claim 1 and a method according to claim 11 are provided. The dependent claims define further embodiments.

• eine erste Reihenschaltung, die einen ersten Widerstand und
• eine erste Diodenanordnung umfasst, wobei die erste Reihenschaltung zwischen eine erste Spannung und eine zweite Spannung zu koppeln ist,
• eine zweite Reihenschaltung, die einen zweiten Widerstand und eine zweite Diodenanordnung umfasst, wobei die zweite Diodenanordnung von der ersten Diodenanordnung verschieden (d.h. unterschiedlich) ist, wobei die zweite Reihenschaltung zwischen die erste Spannung und die zweite Spannung zu koppeln ist,
• einen ersten Kondensator, wobei ein erster Anschluss des ersten Kondensators über einen ersten Schalter mit einem ersten Knoten zwischen dem ersten Widerstand und der ersten Diodenschaltung verbunden ist und über einen zweiten Schalter mit der zweiten Spannung zu verbinden ist,
• einen zweiten Kondensator, wobei ein erster Anschluss des zweiten Kondensators über einen dritten Schalter mit einem zweiten Knoten zwischen dem zweiten Widerstand und der zweiten Diodenanordnung verbunden ist und über einen vierten Schalter mit der zweiten Spannung zu verbinden ist,
• wobei ein zweiter Anschluss des ersten Kondensators mit einem zweiten Anschluss des zweiten Kondensators verbunden ist, und eine Steuerung, wobei die Steuerung eingerichtet ist, in einer ersten Betriebsphase den ersten und den vierten Schalter zu öffnen und den zweiten und den dritten Schalter zu schließen, und in einer zweiten Betriebsphase den ersten und den vierten Schalter zu schließen und den zweiten und den dritten Schalter zu öffnen.

According to one embodiment, there is provided an apparatus comprising:

• a first series circuit including a first resistor and
• comprises a first diode arrangement, wherein the first series connection is to be coupled between a first voltage and a second voltage,
• a second series circuit comprising a second resistor and a second diode arrangement, the second diode arrangement being distinct (ie different) from the first diode arrangement, the second series circuit to be coupled between the first voltage and the second voltage,
• a first capacitor, wherein a first terminal of the first capacitor is connected via a first switch to a first node between the first resistor and the first diode circuit and is to be connected via a second switch to the second voltage,
• a second capacitor, wherein a first terminal of the second capacitor is connected to a second node between the second resistor and the second diode arrangement via a third switch and is to be connected to the second voltage via a fourth switch,
• wherein a second terminal of the first capacitor is connected to a second terminal of the second capacitor, and a controller, wherein the controller is set up to open the first and the fourth switch and to close the second and the third switch in a first operating phase, and to close the first and the fourth switch and to open the second and the third switch in a second phase of operation.

• Verbinden eines ersten Anschusses eines ersten Kondensators mit einer Referenzspannung und Laden eines ersten Anschlusses eines zweiten Kondensators auf eine zweite Knotenspannung zwischen einem zweiten Widerstand und einer zweiten Diodenanordnung in einer ersten Betriebsphase,
• Laden des ersten Anschlusses des ersten Kondensators auf eine erste Knotenspannung zwischen einem ersten Widerstand und einer von der zweiten Diodenanordnung verschiedenen (d.h. unterschiedlichen) ersten Diodenanordnung und Verbinden des ersten Anschlusses des zweiten Kondensators mit der Referenzspannung in einer zweiten Betriebsphase,
• wobei ein zweiter Anschluss des ersten Kondensators mit einem zweiten Anschluss des zweiten Kondensators verbunden ist, und Ausgeben einer Spannung an dem zweiten Anschluss des ersten Kondensators und dem zweiten Anschluss des zweiten Kondensators.

According to another embodiment, a method is provided, comprising:

• connecting a first terminal of a first capacitor to a reference voltage and charging a first terminal of a second capacitor to a second node voltage between a second resistor and a second diode arrangement in a first phase of operation,
• charging the first terminal of the first capacitor to a first node voltage between a first resistor and a first diode arrangement different (ie different) from the second diode arrangement and connecting the first terminal of the second capacitor to the reference voltage in a second phase of operation,
• wherein a second terminal of the first capacitor is connected to a second terminal of the second capacitor, and outputting a voltage at the second terminal of the first capacitor and the second terminal of the second capacitor.

The summary above is intended only as a brief overview of some possible implementations and should not be construed as limiting. In particular, other embodiments may use features other than those discussed above.

character list

• 1A until 1C 10 are circuit diagrams of a circuit according to an embodiment in different phases of operation.
• 2 shows a conventional circuit for generating a bandgap voltage, which is used to explain exemplary embodiments.
• 3 shows example curves to illustrate the circuit 2 .
• 4A and 4B show circuit diagrams for comparing some embodiments with a conventional solution.
• 5 shows a circuit according to an embodiment.
• 6 FIG. 12 is a flowchart illustrating a method according to an embodiment.
• 7-10 show simulation results to illustrate the functioning of exemplary embodiments.
• 11 shows a circuit according to a further embodiment.

Detailed description

Various exemplary embodiments are described in detail below with reference to the accompanying drawings. These embodiments are to be considered as examples only and are not to be construed as limiting. For example, in other embodiments, some of the features or components described may be omitted and/or replaced with alternative features or components. Features or components of different embodiments can be combined to form further embodiments. Variations and modifications described with respect to one embodiment may also be applied to other embodiments. Furthermore, features or components other than those described or shown may be provided, for example features or components used in conventional bandgap circuits or circuits for generating a reference voltage.

Direct connections or couplings shown in the drawings or described below, i.e. electrical connections or couplings without intervening elements (e.g. simple metal conductor tracks) can also be realized by an indirect connection or coupling, i.e. a connection or coupling involving one or more comprises additional intervening elements, and vice versa, as long as the general functioning of the connection or coupling, for example providing a voltage, providing a current or providing a control signal, is essentially retained.

the 1A-1C show a circuit for providing a reference voltage according to an embodiment in different operating phases. the 1A-1C are summarized below as 1 designated.

The circuit of 1 includes a first series connection of a first resistor 11 and a first diode arrangement 13 coupled between a positive supply voltage 10 and ground. Instead of the positive supply voltage 10 and ground, other voltages, provided for example by an external supply voltage, can be used.

The first diode arrangement 13 comprises one or more diodes which can be connected in parallel. A diode within the meaning of the present application is not limited to a pure diode (e.g. a simple PN junction), but diodes within the meaning of the present application can also be implemented as diode-connected transistors, for example by bipolar transistors, their collector and base connections be coupled with each other.

The first resistor 11 has a resistance value R. A voltage U ₁ is present at a first node between the first resistor 11 and the first diode arrangement 14 during operation.

Furthermore, the circuit includes the 1 a second series combination of a second resistor 12 and a second diode arrangement 14, which in turn is coupled between the positive supply voltage 10 and ground. The second diode arrangement 14 is scaled with respect to the first diode arrangement. For example, the first diode arrangement 13 can comprise a single diode and the second diode arrangement 14 can comprise n diodes connected in parallel. In other implementations, one or more diodes of the second diode array are scaled in size (area) with respect to one or more diodes of the first diode array 13 .

The second resistor 12 has in the embodiment of 1 the same nominal resistance value R as the first resistor 11 on. Nominal in this context refers to an intended value. Nominally the same resistance values therefore mean that the resistors 11, 12 are designed to have the same resistance value R. Nevertheless, slight deviations can occur, for example due to manufacturing tolerances. In other embodiments, the resistance values of the resistors 11, 12 can also be nominally different, ie the resistors are designed in such a way that the resistance values are different.

The resistors 11, 12 can be implemented as any circuit component that provides an ohmic resistance that exceeds an ohmic resistance of a simple metal connection, for example a resistance of more than about 5 Ω. In many embodiments, resistance values in the kΩ, MΩ, or even GΩ range can be used. For example, besides conventional resistors such as sheet resistors, resistors can also be implemented as transistors that are biased to provide a desired ohmic resistance between their source and drain or collector and emitter terminals.

During operation, there is a voltage U _n at a second node between the second resistor 12 and the second diode arrangement 14 .

The circuit of 1 furthermore has a first capacitor 17 with a capacitance value C ₁ . A first connection of the first capacitor 17 is connected via a first switch 15 to the first node between the first resistor 11 and the first diode arrangement 13 and is therefore connected to the voltage U ₁ during operation. Furthermore, the first terminal of the first capacitor 17 is connected to ground as a reference voltage via a second switch 114 . A voltage at the first terminal of the first capacitor 17 is in 1 labeled Pre_C1.

Furthermore, the circuit of 1 a second capacitor 110 with a capacitance value C ₂ . A first connection of the second capacitor 110 is connected via a third switch 16 to the second node between the second resistor 12 and the second diode arrangement 14 and thus to the voltage U _n during operation. Furthermore, the first connection of the second capacitor 110 is connected to ground via a switch 18 . A voltage at the first terminal of the second capacitor 110 is labeled Pre_C2.

A second terminal of the first capacitor 17 is connected to a second terminal of the second capacitor 110 and via a fifth switch 113 to ground as shown. Furthermore, the second output of the first capacitor 17 and the second output of the second capacitor 110 are connected via a sixth switch 19 to an output which has an output capacitor 111 connected to ground as shown. The output capacitor 111 has a capacitance C _hold .

A controller 112 is provided to control the switches 15, 114, 16, 18, 113 and 19. The controller 112 can include, for example, a microcontroller, an application-specific integrated circuit (ASIC) or an appropriately programmed processor.

the 1A shows the circuit of the 1 in a first phase of operation. In this, the first switch 15 is open, the second switch 114 closed, the third switch 16 closed, the fourth switch 18 opened, the fifth switch 113 closed and the sixth switch 19 opened. In this state, the voltage Pre_C2 is brought to U _n . The voltage Pre_C1 is equal to 0 (ground) in this state, as is a voltage Post_C at the second terminals of the first capacitor 17 and second capacitor 110.

A second operational phase is in 1B shown. Here the controller 112 causes the first switch 15 to be closed, the second switch 114 to be opened, the third switch 16 to be opened, the fourth switch 18 to be closed and the fifth switch 113 to be opened. The sixth switch 19 remains open. The first connection of the first capacitor 17 is thus connected to the voltage U ₁ . In this state, the first capacitor 17 and the second capacitor 110 are also connected in series between the voltage U ₁ and ground (via the fourth switch 18) and thus act as a capacitive divider, with the resulting voltage Post_C also being divided by the voltage U _n depends on which the second capacitor 110 in 1A was subpoenaed. For the voltage Post_C we get $$\text{Post\_C}=0+{\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1\cdot {\text{<figure-callout id="1" label="C" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">C</figure-callout>}}_1/\left({\text{<figure-callout id="1" label="C" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">C</figure-callout>}}_1+{\text{C}}_2\right)-{\text{u}}_{\text{<figure-callout id="2" label="n ⋅ C" filenames="DE102017127478B4\_0028.png,DE102017127478B4\_0029.png" state="{{state}}">n</figure-callout>}}\cdot {\text{C}}_{}{}_2/\left({\text{<figure-callout id="1" label="C" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">C</figure-callout>}}_1+{\text{C}}_2\right)$$

This can be reshaped to $$\text{Post\_C}\cdot \left({\text{<figure-callout id="1" label="C" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">C</figure-callout>}}_1+{\text{C}}_2\right)/\left({\text{<figure-callout id="1" label="C" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">C</figure-callout>}}_1-{\text{C}}_2\right)={\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1\cdot \left({\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1+{\text{u}}_2\right)\cdot {\text{<figure-callout id="2" label="C" filenames="DE102017127478B4\_0028.png,DE102017127478B4\_0029.png" state="{{state}}">C</figure-callout>}}_2/\left({\text{<figure-callout id="1" label="C" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">C</figure-callout>}}_1-{\text{C}}_2\right)$$

wobei const eine Konstante ist, die von einer Skalierung zwischen den Diodenanordnungen sowie einer Implementierung der Diodenanordnungen abhängt und typischerweise im Bereich 11...12, z.B. bei 11,3, liegt. Diese Bandlückenspannung V_bgp ist relativ weitgehend temperaturunabhängig. Durch Vergleichen der Gleichungen (2) und (3) ergibt sich bei der Wahl $${\text{C}}_1=\left(1+\text{const}\right)/\text{const}\cdot {\text{C}}_2$$

für die Spannung Post_C bei const=11,3 $$\text{Post\_C}={\text{V}}_{\text{bgp}}/\mathrm{23,3}\approx 50\text{mV}$$

As will be explained later, in a conventional bandgap circuit that uses voltages U ₁ and U _n that are as in 1 are generated, for the bandgap voltage V _bgp $${\text{V}}_{\text{bgp}}={\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1+\left({\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1-{\text{u}}_{\text{n}}\right)\cdot \text{const}$$

where const is a constant which depends on a scaling between the diode arrays as well as an implementation of the diode arrays and is typically in the range 11...12, eg at 11.3. This band gap voltage V _bgp is relatively largely independent of temperature. Comparing equations (2) and (3) gives the choice $${\text{C}}_{}$$$${}_1=\left(1+\text{const}\right)/\text{<figure-callout id="2" label="const ⋅ C" filenames="DE102017127478B4\_0028.png,DE102017127478B4\_0029.png" state="{{state}}">const</figure-callout>}\cdot {\text{C}}_{}{}_2$$

for the voltage Post_C at const=11.3 $$\text{Post\_C}={\text{V}}_{\text{bgp}}/23.3\approx 50\text{mV}$$

A reference voltage of about 50 mV is generated here with a typical size of the constant const. In addition, when choosing the capacitances according to Equation (4), since the bandgap voltage V _bgp is essentially temperature-independent, Post_C is also essentially temperature-independent. The voltage Post_C is therefore set to an essentially temperature-independent voltage of the order of 50 mV. It should be noted that equation (4) does not have to be fulfilled exactly and C ₁ /C ₂ can be between 1 and 1.2, for example. In some exemplary embodiments, this can mean a certain degree of robustness, for example with regard to manufacturing tolerances or other deviations in the capacitance values C ₁ , C ₂ of the corresponding capacitors 17 , 110 .

In a third operating phase, which 1C is shown, the fourth switch 19 is then closed in order to output the voltage Post_C set in this way, ie to transfer it to the output capacitor 111 .

If an output voltage other than 50 mV is desired, the Post_C voltage can also be additionally multiplied with conventional devices, such as a multiplier, in order to achieve a desired voltage. this is in 11 shown schematically.

the 11 is based on the 1 , and like elements bear the same reference numerals. In addition to the elements of 1 includes the circuit of 11 an operational amplifier 1101 and a voltage divider of resistors 1102, 1103 connected as shown. As a result, the voltage generated is multiplied by a factor which results from the ratio of the resistance values of the resistors 1102, 1103.

Now, the above Equation (3), which was compared with Equation (2) to derive Equation (5), will be explained with reference to FIG 2 and 3 explained in more detail.

2 illustrates a conventional bandgap circuit. In such a conventional circuit, a voltage is regulated in such a way that an equal current I ₀ is applied to two series circuits. A first series connection comprises a resistor 23 and a first diode arrangement 20, for example a single diode. A voltage U ₁ drops across the diode 20 . A second series connection comprises a resistor 24, a resistor 22 and a second diode arrangement 21 which, for example, can comprise n diodes with n > 1 compared to a single diode in the first diode arrangement 20 and/or in terms of size in relation to the first diode arrangement 20 can be scaled by a factor n with n > 1. A voltage U _n drops across the first diode arrangement 21 and a voltage of U ₁ -U _n drops across the resistor 22, so that the entire voltage drop across of the series connection of the resistor 22 and the second diode arrangement 22 is also U ₁ .

In 3 a curve 31 shows a temperature dependency of U ₁ , a curve 32 shows a temperature dependency of U _n and a curve 33 shows a temperature dependency of the difference U ₁ -U _n . A dotted line 30 illustrates the bandgap voltage at zero Kelvin. This behavior will now be explained mathematically in more detail.

I_S(T) ist ein temperaturabhängiger, aber ansonsten konstanter Strom, der von der bestimmten Diodenimplementierung abhängt, U ist der Spannungsabfall über der Diode, e ist die Elementarladung eines Elektrons, k ist die Boltzmann-Konstante und T ist die Temperatur. Weiterhin gilt: $$\text{dU}/\text{dT}\approx \left({\text{E}}_{\text{g0}}/\text{e}-\text{U}\right)/\text{T}$$

wobei E_g0 die Bandlücke des für die Diodenimplementierung verwendeten Halbleitermaterials, insbesondere Silizium, bei null Kelvin ist.The following equation describes a current I through a diode arrangement: $$\text{I}={\text{I}}_{\text{s}}\left(\text{T}\right)*\left[{\text{e}}^{\left(\text{EU}/\text{kT}\right)}-1\right]$$

I _S (T) is a temperature dependent but otherwise constant current that depends on the particular diode implementation, U is the voltage drop across the diode, e is the elementary charge of an electron, k is the Boltzmann constant, and T is the temperature. Furthermore: $$\text{you}/\text{dT}\approx \left({\text{E}}_{\text{g0}}/\text{e}-\text{u}\right)/\text{T}$$

where E _g0 is the band gap of the semiconductor material used for the diode implementation, in particular silicon, at zero Kelvin.

und für die zweite Diodenanordnung 21, die n Dioden umfasst oder mit einem Faktor n skaliert ist, kann Gleichung (6) wie folgt angenähert werden: $${\text{I}}_0\approx \text{n}*{\text{I}}_{\text{s}}\left(\text{T}\right)*{\text{e}}^{\left(\text{eUn}/\text{kT}\right)}$$

Assuming that eU is greater than kT, equation (1) for the first diode assembly 20 can be approximated as follows: $$\text{I}\approx {\text{I}}_{\text{s}}\left(\text{T}\right)*\left[{\text{e}}^{\left(\text{eu1}/\text{kT}\right)}\right]$$

and for the second diode array 21 comprising n diodes or scaled by a factor n, equation (6) can be approximated as follows: $${\text{I}}_0\approx \text{n}*{\text{I}}_{\text{s}}\left(\text{T}\right)*{\text{e}}^{\left(\text{eUn}/\text{kT}\right)}$$

was auch wie folgt geschrieben werden kann: $${\text{U}}_1-{\text{U}}_{\text{n}}=\text{kT}/\text{e}\ast \text{ln}\left(\text{n}\right)$$

Combining equations (8) and (9) gives: $${\text{e}}^{\left(\text{eu1}/\text{kT}\right)}/{\text{e}}^{\left(\text{eUn}/\text{kT}\right)}=\text{n}$$

which can also be written as follows: $${\text{u}}_1-{\text{u}}_{\text{n}}=\text{kT}/\text{e}\ast \text{ln}\left(\text{n}\right)$$

Equation (11) therefore describes curve 33 from 3 .

und kann die Kurve 32 wie folgt beschrieben werden: $${\text{U}}_{\text{n}}={\text{V}}_{\text{bgp}}-\text{bT}$$

wobei a und b Konstanten sind. Kombinieren der Gleichungen (11), (12) und (13) ergibt: $${\text{U}}_1-{\text{U}}_{\text{n}}=\left(\text{b}-\text{a}\right)\text{T}=\text{kT}/\text{e}*\text{In}\left(\text{n}\right)$$

On the other hand, the curve 31 from 3 be described as follows: $${\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1={\text{V}}_{\text{bgp}}-\text{at}$$

and the curve 32 can be described as follows: $${\text{u}}_{\text{n}}={\text{V}}_{\text{bgp}}-\text{bT}$$

where a and b are constants. Combining equations (11), (12) and (13) gives: $${\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1-{\text{u}}_{\text{n}}=\left(\text{b}-\text{a}\right)\text{T}=\text{kT}/\text{e}*\text{In}\left(\text{n}\right)$$

In a conventional bandgap reference circuit, the first diode arrangement 20 and the series connection of the resistor 22 on the one hand and the second diode arrangement 21 on the other hand are coupled via the respective resistors 23, 24 to a supply. This supply is used in conventional circuits such as that of 2 but provided by a differential amplifier 25 which, as in 2 shown, tapped at nodes between these resistors 23, 24 and between the diode arrangement and the resistor 22, respectively. The resistance values of resistors 23, 24 are conventionally equal and are labeled R _T hereinafter, while a resistance value of resistor 22 is labeled R _B . A voltage supply to these resistors R _T through the differential amplifier mentioned above forces equal currents in both branches, a current I ₀ out 2 .

wobei R_B wie oben erwähnt der Widerstandswert des Widerstands 22 aus 2 ist. (14) und (15) ergeben: $$kT/e\ast In\left(n\right)/R_B=I_0$$

This means: $$\left({\mathrm{<figure-callout\; id="1"\; label="u"\; filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png"\; state="\{\{state\}\}">u</figure-callout>}}_1-u_n\right)/R_B={\mathrm{<figure-callout\; id="0"\; label="I"\; filenames="DE102017127478B4\_0026.png,DE102017127478B4\_0029.png"\; state="\{\{state\}\}">I</figure-callout>}}_0$$

where R _B is the resistance of resistor 22 as mentioned above 2 is. (14) and (15) result in: $$kT/e\ast In\left(n\right)/R_B={\mathrm{<figure-callout\; id="0"\; label="I"\; filenames="DE102017127478B4\_0026.png,DE102017127478B4\_0029.png"\; state="\{\{state\}\}">I</figure-callout>}}_0$$

wobei R_T wie erwähnt der Widerstandswert der Widerstände 23, 24 ist.Furthermore, since V _bgp is the voltage applied to the branches by the differential amplifier mentioned above: $$\left({\text{V}}_{\text{bgp}}-{\text{u}}_1\right)/{\text{R}}_{\text{T}}={\text{<figure-callout id="0" label="I" filenames="DE102017127478B4\_0026.png,DE102017127478B4\_0029.png" state="{{state}}">I</figure-callout>}}_0$$

where R _T is the resistance value of the resistors 23, 24 as mentioned.

Combining (16) and (17) gives: $${\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1={\text{V}}_{\text{bgp}}-\text{kT}/\ast \text{ln}\left(\text{n}\right){\text{R}}_{\text{T}}/{\text{R}}_{\text{B}}$$

Together with (12) (18) leads to: $$\text{a}=\text{k}/\text{e}\ast \text{ln}\left(\text{n}\right){\text{R}}_{\text{T}}/{\text{R}}_{\text{B}}$$

was zusammen mit Gleichung (6) zu Folgendem führt: $${\text{V}}_{\text{bgp}}={\text{U}}_1+\left({\text{U}}_1-{\text{U}}_{\text{n}}\right)\ast {\text{R}}_{\text{T}}/{\text{R}}_{\text{B}}$$

The bandgap voltage V _bgp resulting from this arrangement is a constant, ie is essentially independent of temperature. Equation (18) can also be written as follows: $${\text{V}}_{\text{bgp}}={\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1+\text{kT}/\text{e}\ast \text{ln}\left(\text{n}\right){\text{R}}_{\text{T}}/{\text{R}}_{\text{B}}$$

which together with Equation (6) leads to: $${\text{V}}_{\text{bgp}}={\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1+\left({\text{<figure-callout id="1" label="u" filenames="DE102017127478B4\_0025.png,DE102017127478B4\_0028.png" state="{{state}}">u</figure-callout>}}_1-{\text{u}}_{\text{n}}\right)\ast {\text{R}}_{\text{T}}/{\text{R}}_{\text{B}}$$

With the conventional design off 2 For example, a circuit designer defines n, R _T and R _B according to the characteristics of the diode assemblies 20, 21 to obtain a bandgap voltage V _bgp of about 1.25V.

This equation (21) essentially corresponds to equation (3), where the above-mentioned constant const, eg approximately equal to 11.3, is chosen for the band gap voltage of silicon for R _T /R _B .

More precisely, R _T /R _B and thus const is chosen in such a way that equation (21) at room temperature results in the band gap voltage , which is around 1.2 eV. Equation (20) gives: $$\text{const}={\text{R}}_{\text{T}}/{\text{R}}_{\text{B}}=\left({\text{V}}_{\text{bgp}}-{\text{u}}_1\right)/\left(\text{kT}/\text{e}\ast \text{ln}\left(\text{n}\right)\right)$$

The constant const is thus selected as a function of U ₁ at room temperature and the scaling factor n, for example such that the equations explained above, in particular equation (22), are at least approximately satisfied, for example with a tolerance of 10%. kT/e is 25.7 meV at room temperature. U ₁ results from equation (12), where a is an implementation-dependent constant that depends in particular on the (implementation-dependent) diffusion current. If an operating temperature other than room temperature is intended for the circuit, const can be chosen such that the equations for this operating temperature are satisfied. If a semiconductor material other than silicon is used for the diode arrangements, the band gap V _bgp of this semiconductor material can be used.

For typical diode implementations, U ₁ results in about 600meV at room temperature (at 0K the diode voltage would be at least about the bandgap voltage). The scaling factor n can be chosen equal to 8, for example. This results in the mentioned value of about 11.3 for const.

In the embodiment of 1 is in contrast to the conventional implementation of the 2 the resistor 22 the 2 omitted. It has been found that this has practically no effect on the operation of the circuit 1 , which is why the resistance can be saved. This is now with reference to the 4A and 4B explained.

the 4A Figure 12 illustrates part of the conventional arrangement 2 , in which it is forced that an equal current I ₀ is supplied to the series circuits (23, 29 or 24, 22, 21). In contrast, the 4B an arrangement as in the embodiment of 1 is used, with the first diode arrangement 13 and the second diode arrangement 14 and the first resistor 11 and the second resistor 12. Here at 10 an external supply voltage is provided. As a result, in some exemplary embodiments, the currents flowing through the two series circuits are not exactly the same. Nevertheless, the voltages U ₁ and U _n can also be tapped here and, as shown, used to provide a reference voltage that is at least approximately constant. Since it is not necessary to conduct exactly the same currents through the two series circuits, the resistor 22 of the can accordingly 4A be omitted in embodiments. It should also be noted that the current and thus the voltage supplied at 10 can be varied over a relatively large range, and the reference voltage generated nevertheless remains approximately the same, as will be explained in more detail later using simulation examples. In order to keep the currents approximately the same despite the omission of the resistor 22, in some exemplary embodiments the resistance value of the resistor 48 can also be selected to be somewhat smaller than the resistance value of the resistor 47.

While in the embodiment of 1 Initially no voltage or current feedback to the series circuits 11, 13 or 12, 14 is used, such a current feedback can be used in other embodiments. A corresponding circuit is in 5 shown.

5 12 illustrates a circuit for generating a reference voltage according to an embodiment. The circuit off 5 comprises a first series combination of a resistor 237 and a first diode arrangement 239 and a second series combination of a resistor 238 and a second diode arrangement 2310. The first and second series combinations are coupled between a supply voltage 230 and ground. The second diode array 2310 is scaled with respect to the first diode array 239 as previously discussed. The first and second series circuit can in particular that of 1 correspond.

A voltage U ₁ is tapped off at a node between the first resistor 237 and a first diode arrangement 239 and a voltage U _n is tapped off at a node between the second resistor 238 and the second diode arrangement 2310 . The voltages U ₁ , U _n are supplied to a reference circuit 2311 to provide a reference voltage. The reference circuit 2311 can be configured as previously with reference to FIG 1 be implemented as discussed, i.e. capacitors and switches as in 1 include.

The reference voltage calculated by the reference circuit 2311 is output as a reference voltage and is additionally fed back as indicated by an arrow 2313 to a resistor 231 and a current mirror formed by the transistors 232, 233 to supply a reference current generate. In other embodiments, a different reference voltage may be used instead of the reference voltage generated by calculation circuit 2311 to generate the reference current. This reference current is supplied to a further current mirror comprising transistors 234, 235, 236 to produce two mirrored currents, one supplied to the node between the first resistor 237 and the first diode arrangement 239 and a second to the node between is provided to the second resistor 238 and the second diode arrangement 2310 . This ensures that the same current is added to a current flow through the first and second diode arrays 239, 2310, respectively, in addition to a current from the resistors 237, 238. This reduces a dependency of a total current through the diode arrangements 239, 2310 on the supply voltage 230.

In some embodiments, the current mirrors are designed such that the two mirrored currents in a steady state are significantly larger than currents through resistors 237, 238, for example at least ten times larger. In such embodiments, total current variations caused by supply voltage variations are minimized. For example, currents through resistors 237, 238 may be about 1 nA in a steady state and the two mirrored currents may be about 99 mA or 100 mA.

Steady state here refers to a state some time after start-up. At start-up only current flows through resistors 237 and 238 until the reference voltage builds up and current feedback becomes active.

It should be noted that, unlike in 2 illustrated conventional case the voltage provided at 230 in 5 need not be stabilized, but current feedback is provided. Furthermore, an analog calculation of the reference current is nevertheless carried out, with all the previously discussed variations being possible. Finally, an additional resistor, such as resistor 22, is made 2 , in the embodiment off 5 not required.

the 6 shows a flowchart to illustrate a method according to an embodiment. For illustration, the procedure of 6 with reference to the 1 described. The procedure of 6 however, is also independent of the device 1 usable.

At 60 in 6 a terminal of a second capacitor (eg the second capacitor 110) is charged to a second node voltage between a second resistor and a second diode arrangement, for example to the voltage U _n in 11 . This corresponds to the 1A illustrated operating phase.

In step 61, a first capacitor, for example the first capacitor 17 of the 11 , charged to a first node voltage between a first resistor and a first diode arrangement, for example the voltage U ₁ of 1 . This corresponds to the operating phase of the 1B . In this case, terminals of the first capacitor and the second capacitor are connected to one another, as in 1 shown. In step 62 the capacitors are connected to an output (e.g. closing switch 19 of the 1 ) to get the voltage (Post_C der 1 ) to issue. This corresponds to the 1C illustrated operating phase. In this way, as already referred to 1 explains a reference voltage are provided, for example, a reference voltage of about 100 mV.

The functioning of the exemplary embodiments described here is explained below using simulation results with reference to FIG 7-10 explained. the 7 and 8th show simulation results for ideal switches in an embodiment such as that in 1 shown while the 9 and 10 show corresponding simulation results for real switches. In this case, ideal switches are switches that do not have any parasitic effects, for example due to parasitic capacitances and diodes. Such parasitic capacitances and/or diodes occur, for example, when switches are implemented by transistors.

the 7 shows a generated reference voltage for a value C ₂ equal to 1000fF and C ₁ equal to 1050fF at temperatures of - 50°C, 25°C and 150°C. The different curves indicate different so-called process corners and different supply voltages, starting at 10 in the 1 are supplied, namely 1 V, 1.3 V, 1.7 V and 2 V. In the legend of 7 and also in the following figures, the first number indicates the supply voltage (1 for 1 V, 1.3 for 1.3 V, 1.7 for 1.7 V and 2 for 2 V), followed by the process corner. In particular, a nominal process corner (nom_mc) and the process corners 4p5sfast, 4p5sfs, 4p5ssf and 4p5slow are specified. 4p5 indicates a deviation of 4.5 σ from nominal values, and f and s denote fast and slow vertices, the first specification being for PMOS transistors and the second for NMOS transistors.

As in 7 As can be seen, the output reference voltage varies only between about 0.0545 V and 0.0575 V over a wide range of temperatures, process corners and supply voltages.

the 8th shows the behavior for different values of the capacitance C ₁ between 1090 fF and 1115 fF with C ₂ equal to 1000 fF, again for different temperatures (-50°C, 25°C and 150°C), different process corners and different supply voltages. Again, as can be seen, the variations in the supply voltage generated are much smaller than the temperature and capacitance variations.

the 9 and 10 show simulations corresponding to the simulations of 7 and 8th for real switches, ie with parasitic effects. Here the variations in the generated reference voltage are slightly larger, but still significantly smaller than the variations in temperature, in capacitance and in the supply voltage. The capacitance C ₁ in 9 is slightly smaller than in 7 chosen to take into account that in 9 additional parasitic capacitances are present.

Thus, it can be seen from the simulations that a substantially constant reference voltage can be provided with the techniques discussed, in particular a reference voltage of approximately 50 mV. As explained, this reference voltage can then be brought to a required reference voltage by appropriate circuits such as multipliers.

The illustrated embodiments are for illustrative purposes only and are not to be construed as limiting.

Claims (18)

Device comprising: a first series circuit comprising a first resistor (11) and a first diode arrangement (13), the first series circuit to be coupled between a first voltage (10) and a second voltage, a second series connection comprising a second resistor (12) and a second diode arrangement (14), the second diode arrangement (14) being different from the first diode arrangement (13), the second series connection between the first voltage (10) and the second voltage is to be coupled, a first capacitor (17), a first terminal of the first capacitor (17) being connected via a first switch (15) to a first node between the first resistor (11) and the first diode circuit (13) and via a second switch ( 114) is to be connected to the second voltage, a second capacitor (110), a first terminal of the second capacitor (110) being connected via a third switch (16) to a second node between the second resistor (12) and the second diode arrangement (14) and via a fourth switch ( 18) is to be connected to the second voltage, wherein a second terminal of the first capacitor (17) is connected to a second terminal (110) of the second capacitor, and a controller (112), the controller being arranged to open the first (15) and the fourth (18) switch and to close the second (114) and the third (16) switch in a first phase of operation, and in a second Operating phase to close the first (15) and the fourth (18) switch and to open the second (114) and the third (16) switch. device after claim 1 , wherein the second connection of the first capacitor (17) and the second connection of the second capacitor (110) are to be coupled to the second voltage via a fifth switch (113), wherein the controller (112) is set up to switch the fifth switch (113 ) to close in the first phase of operation and to open in the second phase of operation. Device according to one of Claims 1 or 2 , wherein the second output of the first capacitor (17) and the second output of the second capacitor (110) is coupled to an output via a sixth switch (19), the controller being set up to operate the sixth switch (19) in the first phase of operation and to open the second phase of operation and to close in a third phase of operation. device after claim 3 , further comprising an output capacitor (111) coupled to the output. Device according to one of Claims 1 - 4 , wherein a ratio (1 + const) / const between a capacitance value of the second capacitor (110) and a capacitance value of the first capacitor (17) is selected such that at a specified operating temperature of the device, a voltage U ₁ at the first node and a Voltage U ₂ at the second node satisfies the following condition with a tolerance of no more than 10%: $${\text{V}}_{\text{bgp}}={\text{u}}_1+\left({\text{u}}_1-{\text{u}}_{\text{n}}\right)\cdot \text{const}$$

where V _bgp is the bandgap of a semiconductor used for the first diode array (13) and the second diode array (14) at 0K. device after claim 5 , where const is between 1 and 1.2. Device according to one of Claims 1 - 6 , further comprising a circuit which is set up to multiply a voltage at the second terminal of the first capacitor (17) and the second terminal of the second capacitor (110) by an amplification factor. Device according to one of Claims 1 - 7 , further comprising a feedback circuit (231-236) arranged to supply a current at the first node and the second node based on a voltage output of the device. Device according to one of Claims 1 - 8th wherein the second diode array (14) is scaled in magnitude by a scaling factor relative to the first diode array (13) or comprises more diodes than the first diode array (13). Device according to one of Claims 1 - 9 , wherein the first voltage (10) is a positive supply voltage and the second voltage is ground. Method comprising: Connecting a first terminal of a first capacitor (17) to a reference voltage and charging a first terminal of a second capacitor (110) to a second node voltage between a second resistor (12) and a second diode arrangement (14) in a first operating phase, charging the first terminal of the first capacitor (17) to a first node voltage between a first resistor (11) and a first diode arrangement (13) different from the second diode arrangement (14) and connecting the first terminal of the second capacitor (110) to the reference voltage in a second phase of operation, a second terminal of the first capacitor (17) being connected to a second terminal of the second capacitor (110), and Outputting a voltage at the second terminal of the first capacitor (17) and the second terminal of the second capacitor (110). procedure after claim 11 , wherein the outputting comprises connecting the second terminal of the first capacitor (17) and the second terminal of the second capacitor (110) to an output capacitor (111) in a third phase of operation. procedure after claim 11 or 12 , further comprising connecting the second terminal of the first capacitor (17) and the second terminal of the second capacitor (110) to the reference voltage in the first phase of operation, and disconnecting the second terminal of the first capacitor (17) and the second terminal of the second capacitor ( 110) from the reference voltage in the second phase of operation. Procedure according to one of Claims 11 - 13 , where the reference voltage is ground. Procedure according to one of Claims 11 - 14 , further comprising multiplying a voltage at the second terminal of the first capacitor (17) and the second terminal of the second capacitor (110) by a multiplication factor. Procedure according to one of Claims 11 - 15 , wherein a ratio of a second capacitance value of the second capacitor (110) to a first capacitance value of the first capacitor (17) is between 1 and 1.2. Procedure according to one of Claims 11 - 16 , further comprising generating a current based on a voltage at the second terminal of the first capacitor (17) and the second terminal of the second capacitor (110), and supplying the current to a first node between the first resistor (11) and the first diode arrangement (13) and a second node between the second resistor (12) and the second diode arrangement (14). Procedure according to one of Claims 11 - 17 , The method using the device according to one of Claims 1 - 10 is carried out.

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