GB2308684A - Switched capacitor voltage reference circuit - Google Patents
Switched capacitor voltage reference circuit Download PDFInfo
- Publication number
- GB2308684A GB2308684A GB9526313A GB9526313A GB2308684A GB 2308684 A GB2308684 A GB 2308684A GB 9526313 A GB9526313 A GB 9526313A GB 9526313 A GB9526313 A GB 9526313A GB 2308684 A GB2308684 A GB 2308684A
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- GB
- United Kingdom
- Prior art keywords
- switched
- capacitor
- input
- coupled
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
- G05F3/222—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage
- G05F3/225—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage producing a current or voltage as a predetermined function of the temperature
Description
SWITCHED-CAPACll OR REFERENCE CIRCUIT
Field of the Invention
This invention relates to switched-capacitor reference circuits.
Background of the Invention
Voltage reference circuits having positive and negative temperature coefficient inputs often use bandgap voltage references to provide the first and second voltage inputs, one with a positive and one with a negative temperature coefficient, and sum the two inputs to provide a temperature independent output. The two inputs are scaled at different rates at the inverting input of a differential amplifier which must have a high amplification factor in order to provide virtual ground potential at the inverting input and hence minimise the summation error. The amplifier may additionally amplify the summed voltage at the output, if necessary.
A DC feedback path includes a resistance of a value dependent on the scaling of the inputs. In order to filter out noise from the inputs, which has been amplified by the amplifier, a relatively large capacitor is generally coupled between the input and the output of the amplifier. However, such a high value capacitor cannot easily be integrated on the same chip as the rest of the circuit.
Such circuits are typically switched at a frequency determined by a number of factors. A faster switching speed reduces internally generated noise, and would allow a smaller capacitor which may be integrated on the chip.
However, such a fast switching speed is precluded by the settling times of the bandgap voltage reference transistors within the circuit.
This invention seeks to provide a switched-capacitor reference circuit which mitigates the above mentioned disadvantages.
Summarv of the Invention
According to a first aspect of the present invention there is provided a switched-capacitor reference circuit comprising: a switched reference voltage input, switched at a first switching rate; amplifier means having an input coupled to receive the switched reference voltage input and having an output; a switched DC feedback path coupled between the output and the input of the amplifier means; and, a switched AC feedback path also coupled between the output and the input of the amplifier means, wherein the switched DC feedback path is switched at the first switching rate, and the switched AC feedback path is switched at a second switching rate.
Preferably the second switching rate is substantially equal to a sampling rate of a load coupled to the output, and greater than the first switching rate.
The switched reference voltage input preferably comprises a first input for receiving a voltage signal having a positive temperature coefficient and a second input for receiving a voltage signal having a negative temperature coefficient, the switched reference voltage input being a scaled sum thereof.
Preferably the amplifier means comprises first and second operational amplifiers. The first operational amplifier is preferably coupled to the second operational amplifier via a switched capacitor network, comprising a switched AC path and a switched DC path.
According to a second aspect of the present invention there is provided a switched-capacitor reference circuit comprising: a switched reference voltage input; amplifier means having an input coupled to receive the switched reference voltage input and having an output; an AC feedback path coupled between the output and the input of the amplifier means; and, a switched DC feedback path also coupled between the output and the input of the amplifier means, wherein the amplifier means comprises first and second operational amplifiers, the first operational amplifier being coupled to the second operational amplifier via a switched capacitor network comprising a switched AC path and a switched DC path.
Preferably the switched-capacitor reference circuit further comprises a resampling switched-capacitor, coupled between the switched reference voltage input and the amplifier means, and arranged to isolate the switched reference voltage input and the switched DC path from the amplifier means and the AC path.
According to a third aspect of the present invention there is provided a switched-capacitor reference circuit comprising: a switched reference voltage input; amplifier means having an input coupled to receive the switched reference voltage input and having an output; a re-sampling switched-capacitor coupled between the switched reference voltage input and the amplifier means; an AC feedback path coupled between the output of the amplifier means and a point between the re-sampling switchedcapacitor and the input of the amplifier means; and, a switched DC feedback path coupled between the output of the amplifier means and point between the switched reference voltage input and the re-sampling switched-capacitor.
In this way the entire circuit may be integrated onto a single chip, and erroneous voltage reference values are substantially avoided.
Brief Description of the Drawings
An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIG. 1 shows a prior art switched-capacitor reference circuit.
FIG.2 shows a preferred embodiment of a switched-capacitor reference circuit in accordance with the invention.
Detailed Description of a Preferred Embodiment
Referring to FIG.1, there is shown a prior art switched-capacitor reference circuit 10 including a switched reference voltage arrangement 20 having first and second bipolar transistors 30 and 35 biased by first and second current sources 40 and 45 respectively, in such a way that current per emitter area of the transistors 30 and 35 is different. This produces a voltage with a positive temperature coefficient between emitters of the first and second transistors 30 and 35, which is sampled on a first capacitor 50 by means of a first switch 55. At the same time the emitter-base voltage of the second transistor 35 having a negative temperature coefficient is sampled on a second capacitor 60 by means of a second switch 65. A third switch 70 provides a discharge path for the first and second capacitors 50 and 60.
The sum of sampled charges is temperature-insensitive provided that the following ratios are arranged according to known criteria:the areas of the emitters of the first and second transistors 30 and 35, the capacitances of capacitors 50 and 60; and, the values of the first and second current sources 40 and 45.
Exemplary known criteria are well defined in the prior art. See for example G. Nicollini and D. Senderowicz "A CMOS Bandgap Reference for
Differential Signal Processing", IEEE J. of Solid-State Circuits, v. SSC-26, #1, 1991, pp.41-50.
The prior art switched-capacitor reference circuit 15 also includes an operational amplifier (op-amp) 80 having an AC feedback capacitor 90 and a DC feedback switched-capacitor 92 coupled to the switched reference voltage arrangement 20, and provides voltage scaling, determined by the values of the AC and DC feedback capacitors 90 and 92 respectively.
A switched-capacitor load 95 transfers the reference voltage for further use.
In modern CMOS processes the first and second bipolar transistors 30 and 35 are usually implemented as parasitic lateral or vertical devices which have a relatively high noise level. In order to reduce noise at the output, the
AC feedback capacitor 90 is required to be very large and hence can not be integrated onto a silicon die.
Another problem arises if the switched-capacitor load 95 has to operate at a high switching rate. The first and second switches 55 and 65, and the DC feedback capacitor 92 must be switched at a rate coincident with the settling times of the first and second bipolar transistors 30 and 35, which, in view of their parasitic structure, is relatively slow. However, if the switchedcapacitor load 95 is required to be switched at a higher frequency than the rest of the circuit, the voltages sampled in the DC feedback switchedcapacitor 92 and in the switched-capacitor load 95 would differ in the presence of high frequency noise. The feedback paths would then not correct the voltage and the switched-capacitor load 95 would then sample an erroneous value. Additionally the op-amp 80 working at high sampling rate should be very fast to provide complete settling to achieve high accuracy. Such an op-amp is rather hard to build and if built, would have a relatively high current consumption.
Referring now to FIG. 2 there is shown a switched-capacitor reference circuit 10, including a switched reference voltage arrangement 20 as described above coupled to an amplifier circuit 100, a DC feedback path 200, an error re-sampling switched-capacitor 250 and a AC feedback path 300.
A switched-capacitor load 280 is coupled at an output of the op-amp circuit 100.
The amplifier circuit 100 comprises a first stage op-amp 110, a second stage op-amp 120 and a number of capacitors and switched-capacitors to be further described below.
The first stage op-amp 110 has an inverting input coupled to the third switched-capacitor 70 via the error re-sampling switched-capacitor 250, a non-inverting input coupled to ground and an output. A feedback capacitor 90 is coupled between the output and the inverting input of the first stage opamp 110.
The first stage op-amp 110 is arranged to be relatively slow, because it does not adversely affect output settling. Due to these relaxed settling requirements it is therefore easy to achieve a high DC gain in the first stage op-amp 110. High DC gain is necessary to achieve high accuracy of the whole reference circuit 10.
The second stage op-amp 120 has an inverting input coupled to the output of the first stage op-amp 110 via first and second switch arrangements 130 and 140 respectively, a non-inverting input coupled to ground and an output coupled to the switched-capacitor load 280. A feedback capacitor 165 is coupled between the output and the inverting input of the second stage opamp 120.
The first switch arrangement 130 is a DC coupling switched-capacitor arrangement comprising a capacitor 135 and two switches 132 and 137 arranged to switch the capacitor 130. The second switch arrangement 140 is an AC coupling switched-capacitor arrangement 140 comprising a capacitor 145, two switches 142 and 147 and a further capacitor 150. The
AC coupling arrangement 140 is provided mainly for stability reasons.
The DC feedback path 200 is coupled between the switched-capacitor load 280 and the third switch 70 of the switched reference voltage arrangement 20, and comprises a switched-capacitor 260. The AC feedback path 300 is coupled between the switched-capacitor load 280 and the inverting input of the first stage op-amp 110, and comprises a switched-capacitor 320 and a further capacitor 310.
In operation, the circuit 10 operates at two switching speeds. The first, second and third switches of the switched reference voltage arrangement 20, the switched-capacitor 260 of the DC feedback path 200 and the error resampling switched-capacitor 250 are switched at a low frequency which is slow enough to provide complete settling of the first and second bipolar transistors 30 and 35.
The switched-capacitor 320 of the AC feedback path 300 and all the switches in the amplifier circuit 100 are switched at the same rate as the switchedcapacitor load 280. This prevents an erroneous output reference voltage at the switched-capacitor load 280 caused by differing switching speeds.
When the reference output is sampled the AC and DC coupling paths 130 and 140 are disconnected, so the first and second op-amp stages 110 and 120 are isolated. Hence the output settling process is limited by the second stage 120 frequency response and is not dependent on the first stage.
The switches 132, 137, 142 and 147 states are shown when in first phase.
During this phase the switches transfer the charge on capacitors 130 and 140 to the output stage 120.
During the second phase these switches are in the opposite state and the output of the first stage 110 is sampled on the capacitors 130 and 140.
Thus the input stage 110 is not directly connected to the output stage 120 in either phase. Therefore the settling processes of the input and the output stages 110 and 120 are isolated.
This overcomes the problem of creating a high-gain and fast settling amplifier. The proposed solution provides an amplifier with a gain equal to the multiplication of the gains of the two stages, having a settling time equal to the settling time of just one stage.
The error signal re-sampling switched-capacitor 250 uses a very small capacitor to re-sample a DC error signal and hence reduce the error correction charge which is transferred into the capacitor 310 of the AC feedback path 300.
This results in a greatly increased time constant, providing much better low-pass filtering, and removes the need to decrease the size of the input and DC feedback capacitors, which should be avoided because parasitic effects prevent a precise ratio being achieved when smaller capacitors are used.
The error signal re-sampling switched-capacitor 250 does not affect the DC voltage accuracy because it re-samples an error signal which equals zero if the output voltage is correct and which equals an error value if the output voltage deviates from the desired value. The error charge is integrated on the AC feedback capacitor 310.
It will be appreciated by a person skilled in the art that alternate embodiments to the one described above are possible. For example, the amplifier can be designed in a fully differential form, each stage having two inputs and two outputs. In that case switched capacitors 130 and 140 should be differential as well. One possibility is that they be arranged to transfer a differential component and to reject a common-mode one. In that case common-mode settling can be independent in this two stages, improving the common-mode rejection of the whole circuit.
The switches of the amplifier could also be made non-inverting, providing the positive output cf the first stage to negative input of the second stage and vice versa.
Also the switched capacitor arrangements could be either parasiticsensitive or insensitive implementations. The switched capacitor arrangements could be made inverting such that the charge transferred from input to output has the opposite polarity. In that latter case it might be necessary to exchange the positive and negative inputs of the op-amps in order to ensure that feedback is negative.
The switched capacitor arrangements could be voltage multiplying or dividing, providing voltage scaling and/or diminishing of errors associated with the amplifier. Also, the amplifier circuit 100 or a portion thereof can have auto-zeroing circuitry, ensuring it's offset would not introduce error at the output.
The amplifier circuit 100 could be arranged to have a very fast settling time during just one phase and a slower, typical settling time during the second phase. In this case the time critical functions would be arranged to be performed during the "fast" phase.
Claims (10)
1. A switched-capacitor reference circuit comprising: a switched reference voltage input, switched at a first switching rate; amplifier means having an input coupled to receive the switched reference voltage input and having an output; a switched DC feedback path coupled between the output and the input of the amplifier means; and, a switched
AC feedback path also coupled between the output and the input of the amplifier means, wherein the switched DC feedback path is switched at the first switching rate, and the switched AC feedback path is switched at a second switching rate.
2. The switched-capacitor reference circuit of daim 1 wherein the second switching rate is substantially equal to a sampling rate of a load coupled to the output.
3. The switched-capacitor reference circuit of daim 1 or claim 2 wherein the second switching rate is greater than the first switching rate.
4. The switched-capacitor reference circuit of any preceding claim wherein the switched reference voltage input comprises a first input for receiving a voltage signal having a positive temperature coefficient and a second input for receiving a voltage signal having a negative temperature coefficient, the switched reference voltage input being a scaled sum thereof.
5. The switched-capacitor reference circuit of any preceding claim wherein the amplifier means comprises first and second operational amplifiers.
6. The switched-capacitor reference circuit of claim 5 wherein the first operational amplifier is coupled to the second operational amplifier via a switched capacitor network, comprising a switched AC path and a switched DC path.
7. A switched-capacitor reference circuit comprising: a switched reference voltage input; amplifier means having an input coupled to receive the switched reference voltage input and having an output; an AC feedback path coupled between the output and the input of the amplifier means; and, a switched DC feedback path also coupled between the output and the input of the amplifier means, wherein the amplifier means comprises first and second operational amplifiers, the first operational amplifier being coupled to the second operational amplifier via a switched capacitor network comprising a switched AC path and a switched DC path.
8. The switched-capacitor reference circuit of any preceding claim further comprising a re-sampling switched-capacitor, coupled between the switched reference voltage input and the amplifier means, and arranged to isolate the switched reference voltage input and the switched DC path from the amplifier means and the AC path.
9. A switched-capacitor reference circuit comprising: a switched reference voltage input; amplifier means having an input coupled to receive the switched reference voltage input and having an output; a re-sampling switched-capacitor coupled between the switched reference voltage input and the amplifier means; an AC feedback path coupled between the output of the amplifier means and a point between the re-sampling switched-capacitor and the input of the amplifier means; and, a switched DC feedback path coupled between the output of the amplifier means and point between the switched reference voltage input and the resampling switched-capacitor.
10. A switched-capacitor reference circuit substantially as hereinbefore described and with reference to FIG.2 of the drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9526313A GB2308684B (en) | 1995-12-22 | 1995-12-22 | Switched-capacitor reference circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9526313A GB2308684B (en) | 1995-12-22 | 1995-12-22 | Switched-capacitor reference circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9526313D0 GB9526313D0 (en) | 1996-02-21 |
| GB2308684A true GB2308684A (en) | 1997-07-02 |
| GB2308684B GB2308684B (en) | 2000-03-29 |
Family
ID=10785918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9526313A Expired - Fee Related GB2308684B (en) | 1995-12-22 | 1995-12-22 | Switched-capacitor reference circuit |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2308684B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333673B2 (en) | 1999-12-22 | 2001-12-25 | Telefonaktiebolaget Lm Ericsson (Publ) | Electronic circuit |
| US8502519B2 (en) | 2007-11-30 | 2013-08-06 | Nxp B.V. | Arrangement and approach for providing a reference voltage |
| CN104035469A (en) * | 2014-07-01 | 2014-09-10 | 杭州士兰微电子股份有限公司 | Band-gap reference circuit, integrated circuit and band-gap reference voltage generation method |
| WO2015153025A1 (en) * | 2014-03-31 | 2015-10-08 | Qualcomm Incorporated | Multi-stage switched-capacitor dc blocking circuit for audio frontend |
| EP3487075A1 (en) * | 2017-11-15 | 2019-05-22 | ams AG | Sensor arrangement to sense an external signal |
| DE102017127478A1 (en) * | 2017-11-21 | 2019-05-23 | Infineon Technologies Ag | Device and method for generating a reference voltage |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107368140A (en) * | 2017-09-01 | 2017-11-21 | 无锡泽太微电子有限公司 | Reduce the band-gap reference circuit of offset voltage using switching capacity |
| CN115016589B (en) * | 2022-06-01 | 2023-11-10 | 南京英锐创电子科技有限公司 | Band gap reference circuit |
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|---|---|---|---|---|
| WO1982002806A1 (en) * | 1981-02-03 | 1982-08-19 | Inc Motorola | Switched capacitor bandgap reference |
| EP0093644A2 (en) * | 1982-04-26 | 1983-11-09 | Nippon Telegraph And Telephone Corporation | Switched capacitor circuit |
| EP0282725A1 (en) * | 1987-03-06 | 1988-09-21 | International Business Machines Corporation | CMOS reference voltage generator device |
| JPS63310220A (en) * | 1987-06-12 | 1988-12-19 | Hitachi Ltd | Electric circuit |
| US5059820A (en) * | 1990-09-19 | 1991-10-22 | Motorola, Inc. | Switched capacitor bandgap reference circuit having a time multiplexed bipolar transistor |
-
1995
- 1995-12-22 GB GB9526313A patent/GB2308684B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1982002806A1 (en) * | 1981-02-03 | 1982-08-19 | Inc Motorola | Switched capacitor bandgap reference |
| EP0093644A2 (en) * | 1982-04-26 | 1983-11-09 | Nippon Telegraph And Telephone Corporation | Switched capacitor circuit |
| EP0282725A1 (en) * | 1987-03-06 | 1988-09-21 | International Business Machines Corporation | CMOS reference voltage generator device |
| JPS63310220A (en) * | 1987-06-12 | 1988-12-19 | Hitachi Ltd | Electric circuit |
| US5059820A (en) * | 1990-09-19 | 1991-10-22 | Motorola, Inc. | Switched capacitor bandgap reference circuit having a time multiplexed bipolar transistor |
Non-Patent Citations (1)
| Title |
|---|
| Patent Abstracts of Japan, Vol. E742 page 68, & JP 63 310 220 A * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333673B2 (en) | 1999-12-22 | 2001-12-25 | Telefonaktiebolaget Lm Ericsson (Publ) | Electronic circuit |
| US8502519B2 (en) | 2007-11-30 | 2013-08-06 | Nxp B.V. | Arrangement and approach for providing a reference voltage |
| WO2015153025A1 (en) * | 2014-03-31 | 2015-10-08 | Qualcomm Incorporated | Multi-stage switched-capacitor dc blocking circuit for audio frontend |
| US9391569B2 (en) | 2014-03-31 | 2016-07-12 | Qualcomm Incorporated | Multi-stage switched-capacitor DC blocking circuit for audio frontend |
| CN106464217A (en) * | 2014-03-31 | 2017-02-22 | 高通股份有限公司 | Multi-stage switched-capacitor DC blocking circuit for audio frontend |
| CN104035469A (en) * | 2014-07-01 | 2014-09-10 | 杭州士兰微电子股份有限公司 | Band-gap reference circuit, integrated circuit and band-gap reference voltage generation method |
| CN104035469B (en) * | 2014-07-01 | 2016-08-24 | 杭州士兰微电子股份有限公司 | Band-gap reference circuit, integrated circuit and bandgap voltage reference generate method |
| EP3487075A1 (en) * | 2017-11-15 | 2019-05-22 | ams AG | Sensor arrangement to sense an external signal |
| US11128826B2 (en) | 2017-11-15 | 2021-09-21 | Ams Ag | Sensor arrangement to sense an external signal |
| DE102017127478A1 (en) * | 2017-11-21 | 2019-05-23 | Infineon Technologies Ag | Device and method for generating a reference voltage |
| DE102017127478B4 (en) | 2017-11-21 | 2022-12-29 | Infineon Technologies Ag | Device and method for generating a reference voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2308684B (en) | 2000-03-29 |
| GB9526313D0 (en) | 1996-02-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20011222 |