DE102014103556B4 - Sensor self-diagnosis using multiple signal paths - Google Patents

Abstract

A sensor system implemented in a monolithic integrated circuit comprising: a first sensor device configured to sense a physical feature and connected to a first signal path having a first digital signal processor for a first sensor signal on a semiconductor chip, wherein the first digital signal processor provides a first output signal and a second sensor device configured to sense the same physical feature as the first sensor device and connected to a second signal path for a second sensor signal on the semiconductor chip, the second signal path from the first Signal path is separated and has a second digital signal processor, the second digital signal processor providing a second output signal, wherein a comparison of the first output signal and the second output signal can detect an error in the sensor system.

Description

TECHNICAL AREA

The invention relates generally to integrated circuit (IC) sensors and, more particularly, to an IC sensor self-diagnosis that uses multiple communication signal paths.

STATE OF THE ART

The latest trend in automotive drive technology is turning to established passive safety systems as part of developments in the automotive electronics sector, such as seat belts and airbags that are to be expanded with active safety systems, such as anti-lock braking systems (ABS), electronic stability programs ( ESP) and electric steering systems to provide an increased range of driver assistance functions. As has been the case in the powertrain for some time, the system complexity is also constantly increasing here in order to detect dangerous driving situations and to help prevent accidents by active intervention by a control system. As technology advances, these trends are expected to continue and grow stronger in the future.

The resulting significant increase in the number of electronic components with safety-relevant functions has led to unprecedented requirements in terms of reliability and system availability. In order to be able to achieve this while at the same time meeting cost targets, it is desired to develop efficient methods for functional self-monitoring through integrated test methods together with redundancies. At the same time, progress in design methodologies is desired in order to be able to identify and avoid possible weaknesses in security systems at an early stage. In the field of magnetic field sensors, for example, this was done by introducing the "Safety Integrity Level" (SIL) standard.

In order to meet the SIL standards in the automotive sector, it is desired to implement and use self-tests, including built-in self-tests, not only when starting, but also during normal operation and as automatic monitoring structures or corresponding redundant function blocks and / or signal paths. Conventional magnetic sensor systems, particularly linear Hall measurement systems, have an analog main signal path with a single channel. Technically, it is very difficult or maybe even impossible to meet the SIL requirements for safety-critical applications with this concept. It is therefore no longer possible to cover safety requirements with just one sensor system. Therefore, other conventional solutions have used two identical redundant magnetic field sensors to meet the SIL requirements. Obviously, a significant disadvantage of these solutions is the corresponding doubling of the costs for not just one but two sensors. Still other solutions propose a defined superimposed test signal outside the signal frequency ranges, such as magnetic field sensors with an additional conductor loop on the chip or pressure sensors with a superimposed electrostatic connection to the sensor.

The US 6,167,547 A discloses a self-test system with a plurality of sensor processing channels, each channel having a sensor for providing a digital value. Each channel has two sub-paths. These are used for testing.

Another sensor system with two sensors is disclosed in US 2009/0 128 160 A1. Sensor signal paths can contain analog-digital converters of different resolutions.

The US 6 340 884 B1 discloses another sensor system.

There is still a need for reliable and cost-effective sensor systems and methods, such as those that meet SIL and / or other applicable safety standards.

It is therefore an object of the present application to provide sensor systems and methods which have improved properties with regard to safety.

SUMMARY

A sensor system according to claim 1 and a method according to claim 21 are provided. The sub-claims define further embodiments.

In one embodiment, a monolithic integrated circuit sensor system includes a first sensor device configured to sense a physical feature and connected to a first signal path having a first digital signal processor (DSP) for a first sensor signal on a semiconductor chip, wherein the first digital signal processor provides a first output signal and a second sensor device configured to sense the same physical feature as the first sensor device and is connected to a second signal path for a second sensor signal on the semiconductor chip, the second signal path from the the first signal path is separated and has a second digital signal processor, the second digital signal processor providing a second output signal, wherein a comparison of the first output signal and the second output signal can detect an error in the sensor system.

In one embodiment, a method for comparing signals in a sensor system with a monolithic integrated circuit comprises converting on a single semiconductor chip of a main signal path, which has a main sensor and a first digital signal processor (DSP), converting on the single semiconductor chip of a second signal path, comprising a sub sensor and a second digital signal processor, the main and sub sensors responding to the same physical feature, the sub signal path being different from the main signal path, and the second digital signal processor being different from the first digital signal processor by architecture and / or distinguishes a function, and comparing an output signal of the first digital signal processor with an output signal of the second digital signal processor.

Figure list

• 1A ein System-Blockschaltbild gemäß einer Ausführungsform abbildet.
• 1B ein anderes System-Blockschaltbild gemäß einer Ausführungsform abbildet.
• 2 ein System-Blockschaltbild gemäß der Ausführungsform der 1A abbildet.
• 3 ein System-Blockschaltbild gemäß der Ausführungsform der 1B abbildet.
• 4 ein Blockschaltbild eines digitalen Kerns gemäß der Ausführungsform der 3 abbildet.

The invention will be more fully understood from the following detailed description of various embodiments of the invention, taken in conjunction with the accompanying drawings, in which:

• 1A depicts a system block diagram according to an embodiment.
• 1B depicts another system block diagram according to one embodiment.
• 2nd a system block diagram according to the embodiment of the 1A maps.
• 3rd a system block diagram according to the embodiment of the 1B maps.
• 4th a block diagram of a digital core according to the embodiment of the 3rd maps.

Although the invention is open to various changes and alternative forms, special features have been shown by way of example in the drawings and are described in detail. However, it is clear that there is no intention to limit the invention to the particular embodiments described. On the contrary, it is intended to include all changes, equivalents, and alternatives that are appropriate and fall within the scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

The embodiments relate to systems and methods for self-diagnosis and / or fault detection using multiple signal paths in sensor and other systems. In one embodiment, a sensor system has at least two sensors, such as magnetic field sensors, and separate signal paths associated with each of the sensors. A first signal path may be connected to a first sensor and a first digital signal processor (DSP), and a second signal path may be connected to a second sensor and a second digital signal processor. A signal from the first digital signal processor can be compared to a signal from the second digital signal processor either on-chip or off-chip to detect defects, errors, or other information related to the operation of the sensor system. The embodiments of these systems and / or methods can be configured to meet or exceed relevant security or other industry standards, such as SIL standards.

The SIL standards can include automotive SILs or ASILs. SIL standards can be achieved through the IEC standard 61508 be defined, while ASIL standards by the standard ISO / DIS 26262 can be defined. These standards aim to reduce the risk of failure in increasingly complex systems that may include software, hardware, or other interconnected or interconnected components. There are four different levels (i.e. 1-4 for SIL and AD from ASIL) that specify the level of danger associated with a system or component. level 4th or D is the highest, strictest level while level 1 or A is the lowest, least severe level.

1A forms a conceptual block diagram of a sensor system 100 according to one embodiment. The system 100 has a first sensor 102 and a second sensor 104 on, each with a digital signal processor (DSP) 103 communicate. In one embodiment, the first sensor 102 , the second sensor 104 and the digital signal processor 103 a monolithic integrated circuit based on a single chip 105 is implemented, and the digital signal processor 103 communicates with an external electronic control unit (ECU) 106 .

One of the sensors is a primary or main sensor. In the embodiment of the 1A , is the sensor 102 the main sensor while the sensor 104 is a sub sensor. The main sensor 102 communicates with the digital signal processor 103 over a main signal path, and the Sub sensor 104 communicates with the digital signal processor 103 via a secondary signal path that is at least partially separated from the main signal path, as discussed in more detail below.

In the embodiment of the 1B , each signal path has a separate digital signal processor: the main signal path has a first digital signal processor 103a and the sub signal path has a second digital signal processor 103b on. Any digital signal processor 103a and 103b communicates with the control unit 106 . In one embodiment, a single channel can go to the control unit 106 be communicated, for example, when a comparison is made on the chip, as in 1B pictured and discussed in more detail below, or any digital signal processor 103a and 103b In another embodiment, a separate signal (s) can be sent to the control unit 106 communicate. Referring to either 1A or 1B , are the secondary sensor 104 and its corresponding sub signal path is generally one that, compared to the main sensor 102 , is less precise, slower and / or more noisy, works using different working principles and / or has additional sub-registration tasks. The secondary sensor 104 can therefore be cheaper than the main sensor 102 and may also have fewer positioning, chip area, and other constraints affecting the cost and complexity of the system 100 influence. These secondary acquisition tasks can include measuring compensation signals, such as temperature, mechanical stress, internal operational or preloads, operational or preloads, and / or additional, simpler target measurements. The sensors 102 and 104 have magnetic field sensors in one embodiment, for example, and target measurement of such sensors would be magnetic fields. In embodiments, the sub sensor 104 however, have a plurality of sensors or a sensor arrangement, as in an exemplary embodiment, for example a magnetic field sensor, around the main sensor 102 reflect, as well as a temperature sensor and a load sensor.

In one embodiment, however, the secondary sensor and the signal path can be used in a plausibility comparison with the main sensor and main signal path. Furthermore, the sub sensor and sub signal path can be used for fault detection and for checking the main sensor and main signal path. Such a configuration can offer several advantages. First, SIL compatibility can be achieved. Second, economies of scale and costs can be realized compared to conventional solutions, and self-testing can be carried out during normal operation without significant additional hardware. Additional self-test features of digital signal processing (DSP) and signal processing software can also be implemented. Furthermore, field failures and return rates can also be reduced, which improves the cost efficiencies on both sides, that is to say for the chip manufacturer and for the customer who processes the chip.

Referring again to 2nd 10 is a block diagram of an embodiment of a sensor system 200 based on the in 1A pictured concept. The system 200 has a main magnetic field sensor 202 and a secondary magnetic field sensor 204 , such as a Hall effect sensor or magnetoresistive sensor (xMR, including GMR, AMR, TMR etc.), although the sensors 202 and 204 may be other types of sensors in other embodiments and are not limited to magnetic field sensors. The sensor 202 is conceptually the sensor 102 similar while the sensor 204 conceptually the sensor 104 that above with reference to the 1A and 1B were discussed.

The system 200 also has one or more additional sensors 208 on, which are also considered as auxiliary, auxiliary or additional sensors. The sensor (s) 208 may be temperature, load, current, magnetic field, or any other sensor format in various embodiments.

In one embodiment, the main sensor communicates 202 with a digital part 220 for signal processing (DSP). The DSP part 220 can in turn be connected to an external ECU or other control unit (see for example 1A) via an input / output 210 communicate. According to one embodiment, the sensors communicate 202 and 204 with the DSP part 220 via separate signal paths, which can have structurally different analog signal paths, mixed signal paths and, to a certain extent, digital signal paths as well as procedures and software components. In 2nd is a main signal path leading to the main sensor 202 belongs, shown as a bold line, while a sub signal path leading to the sensor 204 heard as a simple dashed line is shown.

In the embodiment of the 2nd For example, the main signal path may be a signal from the main sensor 202 to an analog-to-digital converter 212 (A / D) and A / D conversion channel switch 214 communicate. A sub signal path communicates a signal from the sub sensor 204 to a multiplexer 216 , which as input / inputs also any signals from additional or additional sensors 208 receives. The secondary signal path sets then from MUX 216 to a second A / D converter 218 continued, which also has its exit to the switch 214 sends.

In one embodiment, elements of the main signal path and elements of the secondary signal path are not identical and / or are implemented using different working principles. The A / D converter 212 For example, in the main signal path may have a third-order sigma-delta converter while the A / D converter 218 may have a first rank sigma-delta converter in the sub-signal path, or one or more of the A / D converters may use a successive proximity register (SAR) or flash technique instead of sigma-delta. In other words, like the sub sensor 204 which is generally one compared to the main sensor 102 is less precise, slower and / or more noisy, works using different working principles and / or has additional auxiliary recording tasks, this can also be the case for the A / D converter 218 compared to the A / D converter 212 be valid.

The outputs of the switch 214 are connected to both the main and the sub signal path and are in one part 220 for digital signal processing (DSP).
The digital signal processor 220 has a state machine in one embodiment 222 , a restriction algorithm 224 and a memory matrix 226 on. In accordance with the main and secondary signal path concept, the digital signal processor can 220 also have a first software part belonging to the main signal path and a second software part belonging to the secondary signal path. Additionally or alternatively, the digital signal processor 220 also implement different DSP methodologies or techniques for the main signal path and the secondary signal path. In one embodiment, the digital signal processor 220 with the I / O 210 via an interface 228 connected, and the I / O 210 is in turn connected to an external ECU (in 2nd not shown) connected.

The main and secondary signal path can therefore provide two different, quasi-redundant analog signal paths that offer numerous advantageous properties. For example, the transmission of the main magnetic field sensor signal from the sensor 202 provide a computational result with high precision in one cycle via the main signal path, the main signal path itself working very precisely, such as by chopping or other techniques, and working quickly, at least with respect to the secondary signal path. The main signal path can also work independently and freely, without being influenced by other system components.

For analysis purposes, the secondary signal path also offers the possibility of providing its data to the control unit, where the data could be processed with either a positive or a negative sign. Any parallel outputs from the digital signal processor 220 to the interface 228 and I / O 210 are in the system 200 shown, while sequential transmissions, for example, could also be implemented using time division multiplexing or on request, as requested externally.

The sensors 202 and 204 and optional 208 may use different sensing principles with respect to their measurements, including how to, technical performance and specifications, size and / or placement of the sensors 202 and 204 itself and bias. An embodiment of the system 200 has two bandgap biasing parts 230 and 232 and a header comparison 234 on. The leader part 230 belongs to the main signal path, and the biasing part 232 belongs to the secondary signal path. The leader parts 230 and 232 offer the option of different preloading of the sensors 102 and 104 , during the header comparison 234 an output signal to the digital signal processor 220 can deliver for consideration.

Embodiments of the system 200 can also use different A / D conversion and / or switching concepts via the A / D converter 212 and 218 and the switch 214 use. As mentioned above, for example, the A / D converter 212 have, for example, a third-order sigma-delta converter in the main signal path, while the A / D converter 218 may have a first rank sigma-delta converter in the sub-signal path, or one or more of the A / D converters may use a successive proximity register (SAR) or flash technique instead of sigma-delta. In various embodiments, these different A / D conversion and / or switching concepts can provide different failure behaviors and / or failure probabilities. The measuring ranges in the embodiments can also be via the inputs mentioned to the A / D converters 212 and 218 in 2nd be changed to capture limitation or limitation effects.

Embodiments can also include the option of switching the sensors 202 and 204 with their respective main and secondary signal paths. For example, the sub sensor 204 be switched into the main signal path, and the same applies to the sensor 202 and the sub signal path. This option can improve fault detection and / or localization by isolating a sensor for example deliver from his way. This switching can also be done for the embodiments of 3rd and 4th discussed below.

Another advantage of the embodiments of the system 200 as well as the system 300 , which is discussed below, is the ability to compare the output signals of both the main and the secondary signal path and to evaluate the result, for example by forming quotients. The result can be evaluated to one or more aspects related to the performance or functioning of these sensors 202 and 204 , the signal paths, the system 200 and / or some other components. For example, comparing the output signals can detect a rapid change in the input signal. In embodiments that use compensation, such as temperature compensation, when the sensor 208 has a temperature sensor, the output signals can be compared as a function of the temperature compensation signal. In other embodiments, limiting or restricting information from the sensors 208 implemented to isolate other signals, properties or information.

Because the digital signal processor 220 software 1 for the main signal path and software 2nd used for the sub signal path, output results of the signal paths can be compared in embodiments. Such a comparison can provide a check of the software algorithms themselves. Internal or external window comparisons can also be used to check the plausibility of the two signal paths or the calculation results of the digital signal processor 220 be used. As part of such a plausibility check, warning and / or failure threshold values can be implemented.

In another embodiment and with reference to the 3rd and 4th , can be a system 300 that the system 200 resembles a first and a second digital signal processor 320 and 321 or other state machines or logic as well as a different signal path configuration compared to the system 200 exhibit. The components and features of the system 300 are generally those of the system 200 discussed above, unless otherwise specified here.

With particular reference to 3rd , indicates the system 300 a main sensor 302 and a sub sensor 304 which may be magnetic field sensors or any other type of sensor (s) in various embodiments in accordance with other embodiments discussed herein. In embodiments, the main sensor detects 302 and the sub sensor 304 the same physical characteristics. In one embodiment, both sensors have 302 and 304 for example magnetic field sensors. The system 300 can also have one or more additional sensors 308 have the sensor (s) 208 of the system 200 are similar that include one or more temperature, stress, current, magnetic field sensors (including Hall effect and / or other magnetoresistive sensors) or any other type of sensor or format in embodiments. In other embodiments, the sensors 308 be omitted. In embodiments, the sensors can 302 and 304 differ from one another in terms of their number, the type of acquisition, the geometry, the size and / or some other features.

Both the main sensor 302 as well as the sub sensor 304 communicate with and within the system 300 via a separate and different signal path. The path leading to the main sensor 302 heard is in 3rd Shown in bold and generally has the highest resolution and precision of the three signal paths while going to the sub sensor 304 belonging way is shown in simple dashed lines. As with the embodiment of the 2nd , the implementation of these two different, separate ways enables a plausibility comparison between the two, because the sensors 302 and 304 typically capture the same physical amount and provide similar or the same temporal resolution between the main and sub signal paths. The system 300 also has a third signal path leading to the auxiliary sensor (s) 308 that appear in dotted and dashed lines in 3rd are pictured, belongs on. The auxiliary sensor (s) 308 are typically of a type different from that of the sensors 302 and 304 is different, such as non-magnetic physical variables that can be used to measure the measurement signals from the sensors 302 and 304 and to compensate their respective signal paths for temperature, mechanical stress, supply voltage or other effects. Each signal path is discussed individually.
As above with reference to 2nd discussed, elements of the main, secondary and third signal path are not identical and / or are implemented in embodiments using different working principles. The A / D converter 312 For example, in the main signal path may have a third-order sigma-delta converter while the A / D converter 313 may have a first rank sigma-delta converter in the sub-signal path, or one or more of the A / D converters may use a successive proximity register (SAR) or flash technique instead of sigma-delta. In other words, like that Sub sensor 304 which is generally one compared to the main sensor 302 is less precise, slower and / or more noisy, works using different working principles and / or has additional auxiliary recording tasks, this can also be the case for the A / D converter 312 , 313 and or 318 be valid.

Referring to the main sensor 302 and its signal path, the sensor communicates 302 with an A / D converter 312 and with a first digital signal processor 320 . As mentioned above, the system 300 a first and a second digital signal processor 320 and 321 in contrast to the only DSP block 220 of the system 200 on. The main signal path sets from the digital signal processor 320 to an output interface 328 away. The bias circuit 330 is with the sensor 302 connected, also with bias comparison circuit 334 and then with the digital signal processor 321 connected is.

The secondary sensor 304 communicates with an A / D converter 313 and without an intervening multiplexer in an embodiment like the system 200 . The omission of a multiplexer from the sub signal path in the embodiment of FIG 3rd can speed up the processing and clocking of signals within the system 300 improve. The A / D converter 313 may be of a different type and / or a different filter architecture or in some way from the and / or the A / D converters 312 and 318 vary in embodiments and communicates with the digital signal processor 321 , the digital signal processor other than the one with which the sensor 302 connected is. In other embodiments, the digital signal processors can 320 and 321 be reversed so the sensor 302 with the digital signal processor 321 is connected and the sensor 304 with the digital signal processor 320 , and / or circuitry can be in the system 300 be implemented to the digital signal processors 320 and 321 to switch between different signal paths. The digital signal processors 320 and 321 are in 3rd For example, depicted as connected, for example, to exchange data, states, or other information, although these connections may be omitted in other embodiments. The digital signal processors 320 and 321 are more fully below with additional reference to 4th discussed.

In the sense of even greater diversity between the main and secondary sensors 302 and 304 and corresponding signal paths, a sensor can 307 be connected to the sub signal path, for example to provide compensation. In one embodiment, the sensor 307 for example, a stress sensor to provide stress compensation information about the sensor 304 and the sub signal path via the bias circuit 332 to deliver. The bias circuits 330 and 332 can with each other through the bias comparison circuit 334 and / or the digital signal processor 321 are compared to detect a malfunction in one or the other or both and / or a deviation from a nominal value in the embodiments. Based on information from the sensor 307 , may be a voltage, a current, or some other feature related to the sensor 304 can be adjusted to for load, temperature or other factors that affect the precision of the sensor 304 impact, compensate.

In addition, further diversity can be provided between the main and sub signal paths by providing analog compensation in one signal path and digital compensation in the other. In the system 300 can the bias circuit 332 for example analog compensation in the sub signal path by adapting one or more features associated with the sensor 304 based on analog information from the sensor 307 deliver. In the meantime, the digital signal processor 320 provide digital post compensation in the main signal path, for example by taking information from the auxiliary sensors into account 308 by the digital signal processor 321 or can be received in any other way. The analog and digital compensation can be reversed, split, or otherwise connected to or between the main signal path and the sub signal path in various embodiments. In general, however, different embodiments may use a different compensation technique in each signal path, such as an analog compensation technique in one signal path and a digital compensation technique in the other, or a first analog technique in one signal path and a second analog technique in the other signal path , or a first digital technique in one signal path and a second digital technique in the other signal path.

Image sensors 308 are in one embodiment with the multiplexer (MUX) 316 and then with the A / D converter 318 connected. In embodiments, such as one in which only a single auxiliary sensor 308 is present, the MUX 316 be omitted. The A / D converter 318 communicates with the digital signal processor via the third signal path 321 or the same digital signal processor 320 or 321 with which the sub sensor 304 communicates. As mentioned above, variety of signal paths can be provided, at least in part by the A / D converter 318 which has a different architecture, resolution and / or is of a different type than one or both of the A / D converters 312 and 313 . However, this can vary in other embodiments. In another embodiment, for example, the auxiliary sensors 308 for example connected to either the main or secondary signal path by a MUX. In an exemplary embodiment, the A / D converter 318 are omitted, with auxiliary sensors and the main sensor 302 with MUX 316 , then the A / D converter 312 and the digital signal processor 320 are connected. Or the sub sensor 304 can with the auxiliary sensors 308 with the MUX 306 , then the A / D converter 313 and the digital signal processor 321 be connected. As the skilled person understands, other variations can also be implemented.

In embodiments, the digital signal processor 320 and the digital signal processor 321 with different supply voltages, each vs 336 and vs 338 be connected. More generally, one and / or both of the different analog power supplies can be for the main signal path and the sub signal path and / or digital signal processor 320 and digital signal processor 321 implemented in embodiments to provide additional variety and / or separation between the signal paths and / or circuit parts and components. Although this is in 3rd is not shown, for example, a first analog power supply with the sensor 302 and / or the main signal path, and a second analog power supply can be connected to the sensor 304 and / or the sub signal path in addition to Vs 336 and vs 338 be connected on the digital side. The first or the second power supply can also be the auxiliary sensors 308 and / or supply a third signal path, or a third analog power supply can be implemented in various embodiments. In other embodiments, an analog supply is provided and a digital supply is provided.
In addition, in one embodiment, the digital signal processor 320 with a first oscillator 340 be connected, and the digital signal processor 321 can with a different, second oscillator 342 be connected. In embodiments, the oscillators 340 and 342 be different or the same, i.e. two separate devices of the same type. In other embodiments, the oscillators 340 and 342 separate devices and have different types of oscillator devices. This can provide further diversity between the main and the secondary signal path and the independence between the digital signal processors 320 and 321 increase.

In another embodiment, the digital signal processor 321 used to perform a recalculation or plausibility check of a calculation or other process of the digital signal processor 320 or vice versa. In 1 this optional feature is through additional input signals to the digital signal processor 321 illustrates: input signal 350 from the A / D converter 312 to the digital signal processor 321 , and input signal 351 from the digital signal processor 320 to the digital signal processor 321 . Therefore, the digital signal processor 321 perform the same calculation or process as the digital signal processor 320 by the signals 350 and 351 may be used, for example at the same or a lower data rate in one embodiment and / or in embodiments in which the digital signal processor 320 and 321 are the same, similar or different from each other to check whether the digital signal processor 320 works properly. The new signaling or setting up additional connections can do it to the digital signal processor 320 enable the functionality of the digital signal processor 321 to consider in place of or in addition to the opposite configuration in various embodiments.

Although they may be identical in other embodiments, the digital signal processor 320 and the digital signal processor 321 even in the embodiments of FIG 3rd and 4th not identical. Not identical or different implementations of the digital signal processor 320 and 321 may be advantageous in embodiments to reduce the risk of systematic errors associated with development or other processes that typically cannot be considered with the same or similar probability when two identical hardware implementations are used. Although particular features are spoken here in relation to one another, those skilled in the art understand that these features can be reversed in other embodiments, or that still other configurations or features for the digital signal processor 320 and / or the digital signal processor 321 may be present in other embodiments that still provide signal processing and / or signal path diversity. In the embodiment of the 3rd , the digital signal processor 320 have a higher resolution and / or only the processing of the main signal path and information from the main sensor 302 be dedicated while the digital signal processor 321 Larger and more complex but may be responsible for more information and the processing of the secondary and third signal path. In one embodiment, the digital signal processor 320 for example, have a dedicated hardware block with sequentially running multiplication and subtraction / addition stages. Any digital signal processor 320 and 321 can use different compensation methods and implement different distinctions to provide increased diversity between the main and sub signal paths.

With reference, for example, to 4th , is an embodiment of the implementation of the two digital signal processors 320 and 321 pictured. In the embodiment of the 4th , are the digital signal processors 320 and 321 as part of a single digital core 402 implemented, although every digital signal processor 320 and 321 in other embodiments, may have a separate digital core with additional signal paths implemented as needed. In general, including in ways that are in 4th are shown, as well as others, the digital signal processor differ 320 and the digital signal processor 321 in their architectures to provide additional diversity between the main and sub signal path and such that the likelihood of systemic errors occurring is reduced. Error coverage can also be improved if a plausibility check or recalculation is carried out in embodiments in which the signals 350 and 351 or other similar signals to the digital signal processor 321 and or 320 to be delivered.

The digital signal processor 320 is connected to the main signal path leading to the main sensor 302 heard and as input a signal from the A / D converter 312 receives. The digital signal processor 321 is connected to the secondary signal path and third signal path in one embodiment and receives as input a signal from the A / D converter 313 . As mentioned above, the digital signal processor 320 and the digital signal processor 321 associated with different signal paths may be reversed or otherwise perform different special functions specifically depicted in the embodiments. In one embodiment, the digital signal processor 320 the RAM 404 and an analog and / or digital hardware block 406 to implement one or more functions, including compensation for offset, sensitivity, load, temperature and / or other effects. In embodiments, the RAM 404 of the digital signal processor 320 for example with the RAM 408 of the digital signal processor 321 connected to data related to the auxiliary sensors 308 for use in compensation calculations by RAM 404 to recieve. This connection between the RAM 404 and the RAM 408 is optional in embodiments and can be eliminated in one embodiment, for example to improve the variety of main and sub signal paths. The analog and / or digital hardware block 406 can implement post-processing and other functions, such as linearization calculations, and can also use the firmware 410 of the digital signal processor 321 in embodiments communicate to exchange post-processing and other information, though, such as connection that occurs between RAM 404 and RAM 408 the connection between the hardware block 406 and the firmware 410 can also be optional in embodiments. In one embodiment, the firmware 410 a mask programmable state machine or other suitable configuration.

Eliminating one or more of these connections in embodiments may include one or both digital signal processors 320 and 321 make it more complex but also more diverse. The connection between RAM 404 and RAM 408 can work for example to the digital signal processor 320 with compensation information from the sensor (s) 308 to deliver, this information from the digital signal processor 321 before being passed on to the digital signal processor 320 were processed. The omission of the connection therefore requires additional calculations and processing by the digital signal processor instead 320 is to be carried out, although this may be advantageous in embodiments in which more complete diversity between the main and sub signal path is required or desired. With or without connection (s) between each other, use the digital signal processors 320 and 321 different compensation methodologies and / or algorithms in embodiments in order to influence influences on temperature, mechanical stress and other factors on the sensors 302 and 304 to compensate. The algorithms for the digital signal processor 320 and the digital signal processor 321 can differ, for example, with regard to the chronological sequence of the calculations and / or the functionality used. In embodiments, the various functionalities can be achieved, for example, by using polynomials that have different mathematical ranks. In embodiments, the complexity of one or both of the compensation algorithms can be reduced, or the algorithm can be completely omitted if temperature, mechanical stress and other effects are reduced or eliminated even through analog circuit implementations.

Signals from the analog and / or digital hardware block 406 and the firmware 410 become the digital output interface 328 or to other circuits before the output interface 328 given so that a comparison of the output signals from the digital signal processor 320 and the digital signal processor 321 can be carried out to detect a possible error in the system 300 capture. In another embodiment, a comparison of the output signals of the digital signal processor 320 and the digital signal processor 321 executed outside the chip, such as in a control unit (for example, the control unit 106 of the 1B) . In yet another embodiment, a first comparison is performed on the chip, and a second comparison is performed off-chip, in a controller, or by other circuitry such that the first and second comparisons themselves can be compared.

In embodiments, the respective output signals should be from the digital signal processor 320 and the digital signal processor 321 despite the different paths taken by each of the sensors 302 and 304 taken here may be the same or similar at this point, and may be delivered simultaneously or in time, such as within a few milliseconds of each other in an exemplary embodiment. A difference between the two, such as a lack of identity or a variation that is greater than a certain percentage or value, such as greater than about 10 percent or about 20 percent in exemplary embodiments, may indicate an error, a malfunction or indicate another problem. In embodiments, a comparison can be made between the signals from the digital signal processor 320 and the digital signal processor 321 run on the chip, such as within or through the output interface 328 or elsewhere within the digital core 402 , or the signals from any digital signal processor 320 and 321 may be communicated to an engine control unit (ECU) or other control device outside of the chip, for example for comparison and / or other processing.

In embodiments, the two digital signal processors 320 and 321 have, or in the embodiment of 2nd that have a single digital signal processor 220 has, additional features and functions can also be implemented within each digital signal processor itself. For example, a protected memory and working register area may be provided using additional security bits in the data signals, such as those according to parity logic, Hamming code, or other suitable methodology that those skilled in the art will understand.

Protected memory, working register area, and signal buses can also be provided in an embodiment having a forward error correction block (FEC). One or more of the digital signal processors can also be used 220 , 320 and 321 use a redundant instruction decoder and / or control bus as well as a redundant instruction set and security bits or by using an FEC block or a redundant data path, such as an arithmetic logic unit (ALU) and data bus, which are also replaced by appropriate security bits or by using an FEC Blocks are protected.

Embodiments can therefore provide security standard compatibility as well as error self-diagnosis in a sensor system. While the handling of errors may vary according to type and severity, as well as according to the particular system and / or the relevant security standards, embodiments may provide opportunities to warn system users of detected problems. In a safety critical automotive electronics power steering sensor application that uses magnetic field sensors, detected errors can cause an ECU to warn a driver of a critical system problem so that appropriate action can be taken. In certain applications, an ECU can be programmed to switch to a safe mode or a safe operating protocol in the event of a failure situation.

Furthermore, embodiments are more space and cost efficient than conventional solutions that use redundant main sensors. For example, the main / sub sensor and signal path can increase chip area by less than 10% in embodiments while using a single main sensor instead of two, the sub sensor typically being a cheaper device in view of the reduced performance requirements. Given the cheaper sub-sensor, there are also advantages compared to conventional solutions that use two main sensors on a single chip.

Various embodiments of systems, devices and methods have been described here. These embodiments are given by way of example only and are not intended to limit the scope of the invention. It is also clear that different features of the embodiments that have been described can be combined in different ways to create numerous additional embodiments. Although various materials, dimensions, shapes, configurations and locations, etc. have been described for use with the disclosed embodiments, others may be used in addition to the disclosed ones without exceeding the scope of the invention.

Those skilled in the art will recognize that the invention may have fewer features than illustrated in any single embodiment described above. The embodiments described herein are not intended to be an exhaustive presentation of the ways in which the various features of the invention can be combined. The embodiments are therefore not mutually exclusive combinations of features, rather the invention may have a combination of different individual features selected from different individual embodiments, as one of ordinary skill in the art understands. In addition, the elements described with reference to one embodiment may be implemented in other embodiments even if they are not described in such embodiments and unless otherwise noted. Although a dependent claim in the claims may refer to a specific combination with one or more claims, other embodiments may also include a combination of the dependent claim with the subject of any other dependent claim or a combination of one or more features with other dependent or independent claims. Such combinations are suggested herein unless it is stated that a specific combination is not intended. Furthermore, features of the claim should also be contained in any other independent claim, even if this claim is not made directly dependent on the independent claim.

Any incorporation by reference to the above documents is limited in such a way that no object is included that contradicts the explicit disclosure given here. Any incorporation by reference to the above documents is further restricted such that no claims contained in the documents are incorporated by reference here. Any incorporation by reference to the above documents is further restricted in such a way that no definitions contained in the documents are incorporated here by reference except as expressly.

For the purposes of interpreting the claims for the present invention, it is expressly the intention that one should not rely on the regulation of section 112 , Sixth Paragraph, 35 USC appeals unless the specific expressions "Means to" or "Step to" are mentioned in a claim.

Claims (33)

A sensor system implemented in a monolithic integrated circuit comprising: a first sensor device which is set up to detect a physical feature and which is connected to a first signal path which has a first digital signal processor for a first sensor signal on a semiconductor chip, the first digital signal processor providing a first output signal, and a second sensor device that is configured to detect the same physical feature as the first sensor device and that is connected to a second signal path for a second sensor signal on the semiconductor chip, the second signal path being separate from the first signal path and having a second digital signal processor , the second digital signal processor providing a second output signal, wherein a comparison of the first output signal and the second output signal can detect an error in the sensor system. Sensor system according to Claim 1 , wherein the sensor system is set up to carry out the comparison within the sensor system. Sensor system according to Claim 1 , whereby the comparison is carried out outside the sensor system. Sensor system according to Claim 3 , wherein the comparison is carried out by a control unit which is connected to the sensor system. Sensor system according to one of the Claims 1 to 4th , wherein an architecture and / or a function of the first digital signal processor differs from an architecture or a function of the second digital signal processor. Sensor system according to one of the Claims 1 to 5 , wherein the first digital signal processor is configured to communicate with the second digital signal processor. Sensor system according to one of the Claims 1 to 6 , wherein the first and the second digital signal processor are each connected to the first and the second signal path by a first and a second analog-digital converter. Sensor system according to Claim 7 , wherein the first analog-to-digital converter differs from the second analog-to-digital converter. Sensor system according to one of the Claims 1 to 8th , which further comprises at least one additional sensor device. Sensor system according to Claim 9 , wherein the at least one additional sensor device is part of a third signal path that is at least partially separated from the first and second signal paths. Sensor system according to Claim 9 or 10th , wherein the at least one additional sensor device is connected to either the first signal path or the second signal path by a multiplexer. Sensor system according to one of the Claims 9 to 11 , wherein the at least one additional sensor device is selected from the group consisting of a temperature sensor, a load sensor, a current sensor, a voltage sensor and a magnetic field sensor. Sensor system according to one of the Claims 1 to 12 , wherein the first and the second sensor device each comprise a magnetic field sensor. Sensor system according to one of the Claims 1 to 13 , further comprising a compensation sensor device connected to the first or the second signal path for supplying an analog compensation signal therefor, and wherein the other of the first and the second signal path is arranged to receive a different compensation signal different from the compensation signal. Sensor system according to Claim 14 , wherein the other compensation signal comprises a digital compensation signal. Sensor system according to one of the Claims 1 to 15 , wherein the first signal path compared to the second signal path has at least one feature that is selected from the group that is selected from faster, more precise, less noise and having a different working principle. Sensor system according to one of the Claims 1 to 16 , wherein the sensor system corresponds to at least one standard safety integrity level. Sensor system according to one of the Claims 1 to 17th , further comprising a first power supply connected to the first signal path and a second power supply connected to the second signal path. Sensor system according to one of the Claims 1 to 18th further comprising a first power supply connected to the first digital signal processor and a second power supply connected to the second digital signal processor. Sensor system according to one of the Claims 1 to 19th further comprising a first oscillator device connected to the first digital signal processor and a second oscillator device connected to the second digital signal processor. A method of comparing signals in a sensor system implemented in a monolithic integrated circuit, comprising: Implementing a main signal path having a main sensor and a first digital signal processor on a single semiconductor chip, Implementing a secondary signal path having a sub sensor and a second digital signal processor on the single semiconductor chip, the main and sub sensors responding to the same physical feature, the secondary signal path being different from the main signal path and the second digital signal processor being different from that distinguishes first digital signal processor by an architecture and / or a function, and Comparing an output signal of the first digital signal processor with an output signal of the second digital signal processor. Procedure according to Claim 21 , further comprising implementing at least one auxiliary sensor and a third signal path on the single semiconductor chip, the third signal path being at least partially separated from the main signal path and the secondary signal path. Procedure according to Claim 22 , further comprising: compensating a signal of the main signal path and / or a signal of the secondary signal path by a signal of the third signal path. Procedure according to Claim 23 , further comprising: compensating for the other of the signal of the main signal path or the signal of the secondary signal path by a digital compensation signal. Procedure according to one of the Claims 21 to 24th , further comprising: implementing a first analog-digital conversion technique on the main signal path and implementing a second analog-digital conversion technique on the secondary signal path, the first and second analog-digital conversion techniques being different from one another. Procedure according to one of the Claims 21 to 25th , further comprising: implementing a first algorithm by the first digital signal processor and implementing a second algorithm by the second digital signal processor, the second algorithm being different from the first algorithm. Procedure according to Claim 26 , the second algorithm differing from the first algorithm with regard to a chronological sequence of processes and / or an executed function and / or an applied compensation technique. Procedure according to one of the Claims 21 to 27th further comprising providing protected circuitry by implementing security bits in the first digital signal processor and / or the second digital signal processor. Procedure according to Claim 28 , wherein the protected circuit comprises a memory circuit and / or a register area and / or a control bus and / or a signal bus and / or a data bus and / or a data path. Procedure according to one of the Claims 21 to 29 , wherein the first digital signal processor and / or the second digital signal processor has a forward error correction block. Procedure according to one of the Claims 21 to 30th , further comprising: interchanging the main sensor and the sub sensor such that the main sensor is connected to the second digital signal processor and the sub sensor is connected to the first digital signal processor. Procedure according to one of the Claims 21 to 31 , further comprising: performing a plausibility check of the first or second digital signal processor by the other one of the second or first digital signal processor. Procedure according to Claim 32 wherein performing a plausibility check further comprises performing the plausibility check using a lower data rate and / or a different implementation between the first and second digital signal processors.

Images